------------------------------------------------------------- Author : http://www.teahlab.

com/
--- Circuit: Half Adder
--- Note
: This VHDL program is a structural description of
-the interactive Half Adder on teahlab.com. The
-program shows every gate in the circuit and the
-wires linking the gates. It is very important to
-learn structural design (RTL) strategies because
-as your assignments become larger and larger,
-knowledge of register transfer level (RTL) design
-strategies become indispensable.
------------------------------------------------------------Here we define the AND gate that we need for
-- the Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B;
end func;
--*=========================================================
-Here we define the XOR gate that we need for
-- the Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity xorGate is
port( A, B : in std_logic;
F : out std_logic);
end xorGate;
architecture func of xorGate is
begin
F <= A xor B;
end func;
--*=========================================================
-- At this point we construct the half adder using
-- the AND and XOR gates
library ieee;
use ieee.std_logic_1164.all;
entity halfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end halfAdder;

architecture halfAdder of halfAdder is

component andGate is -- import AND Gate
port( A, B : in std_logic;
F : out std_logic);
end component;
component xorGate is -- import XOR Gate
port( A, B : in std_logic;
F : out std_logic);
end component;
begin
G1 : xorGate port map(A, B, sum);
G2 : andGate port map(A, B, Cout);
end halfAdder;
---------------------------------------------------------END
---------------------------------------------------------END

-- 3 x 8 decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dec IS
PORT (
s : IN std_logic_vector(2 DOWNTO 0);
y : OUT std_logic_vector(7 DOWNTO 0));
END dec;
ARCHITECTURE arch OF dec IS
-- SIGNAL s_temp : std_logic_vector(2 DOWNTO 0);
BEGIN
PROCESS(s)
BEGIN
CASE s IS
WHEN "000" =>
c <= "00000001";
WHEN "001" =>
c <= "00000010";
WHEN "010" =>
c <= "00000100";
WHEN "011" =>
c <= "00001000";
WHEN "100" =>
c <= "00010000";
WHEN "101" =>
c <= "00100000";
WHEN "110" =>
c <= "01000000";
WHEN "111" =>
c <= "10000000";
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END arch;