Ifyou find conoc' Please send us ci jons in figui tones IEICE TRANS. ELECTRON, VOL_EV2-C, NOG TUNE009 [PAPER _ Special Section on Analog Circuits and Related SoC Integration Technoiogies ] Architectural Exploration and De: ign of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters ‘Sergio SAPONARA™®, Pierluigi NUZZO"', Claudio NANI", Geert Van der PLAS" SUMMARY Time-inteleaved (TP) analog-o-dgal converters (ADCS) ane frequently acated as a powerfcen solution to realize the high sampling rates required in single-chip wanscivers forthe emerging com munication schemes: ultra-wideband, fet serial inks, cognitive radio and softvare-detined radio. However, the combined effets of muliple ds ‘orion sources due to channel mismatches (bandwidth, ofc, gain and Sming) severely aet system performance and power consumption of a ‘TL ADC and need t be accounted for since the earlier design phases. To this pape, systemevel design of TT ADCs is addressed through platform-based methodology. enabling effective vestigation of diferent Speediesolution scenarios aswell a the impact of parallelism on accuracy, ‘eld, samplingrate, area and power consumption. Design space explo tation of aT successive approximation ADC is performed top-down via Monte Caro simulations, by exploiting behavioral models built bottom-up alter characterizing feasible implementations of the main bulng blocks ina 90.nm I-V CMOS process. AS a result, two implementation ofthe ‘TLADC are proposed that are capable to provide an oustanding figure-of. merit below 015 pl/coaerson-step. key words: AD converters, ine interleaving, analog CMOS crits, 9 tem eel design, SAR, low power design Introduction 1.1. State of the Artin Time-Interleaved ADCs, ‘The single-chip integration of complex transceivers for fast serial inks and emerging wireless communications, such as cognitive radio, software-defined radio and ultra-wideband (UWB), has fostered the interest in high-speed analog-to- digital converters (ADCs) with low power consumption and low implementation costs [1] [2]. In particular, ADCs with ‘medium resolutions, 4-6bits, and a sampling frequency up to 1 GS/s are required in serial links, Hard Disk drives and UWB receivers [2}-[17]. ‘At the state of the art, flash-type ADCs are the pre- ferred choice for high speed applications [7]-[10}; however, the higher speeds and transistor densities afforded by deep “Manuscript received October 16, 2008. ~ Manuscript revised January 21, 2009. ” "The authors are with the University of Pisa, via Caruso 16, 56122, Pisa, Italy “The authors withthe Dept. of Electr. Eng. and Computer Sci ences, University of California at Berkeley, 205 Cory Hall, Berke- ley, CA 94720, US.A. The author is with Ni hhoven, The Nether The author Belgium, 8) E-mail: sergio saponara@iet.unipi.it DOK: 10.1587jtransele-E92.C.1 High Tech Campus 37 S656AE Eind- with IMEC, Kapeliref 75, B-3001, Leuven, ‘Nonmembers, and Luca FANUCCT', Member Table _Pesornnes of sear TISAR ADCS ] Terr Speed | Power | FOM | Process [size [PNOB| its | Gis | mW | piteony lun | Emr | 6 [ao] s | os | 6 | os los | Sar | a6 [aaa [s [02s | oa | oan nae wo | os Won 16 lon | Pp [7 [se fo | 2 | at | os oem w [eee] is [77 [20 [13s | us | os w | iv | ts [79 [wo] ae | eo | ot Won lon [ome s| « [of sos | mm | a [ isoam | 2 | es lon [eae 39 [6 | a2 | ose | 008 sub-micron (DSM) CMOS technologies make traditionally slower ADC architectures applicable to higher bandwidth signals. The exponential dependence of area and power on the number of bits makes flash ADCs maximally efficient for lower resolutions, up to 4-5 bits [9], [11]. For resolutions higher than 5 bits, successive approximation (SAR) convert- cers are being increasingly used in parallel arrays, to realize high effective sampling rates with decreased power and area ‘costs [4], [11}-119]. Exploiting a mostly digital architecture amenable to parallelization, SAR ADCs can offer excellent power efficiency [20], and are expected to respond better to DSM CMOS design challenges such as low supply volt- age and parameter variability (21]. As reported in Table 1, Time-Interleaved (TI) SAR converters recently proposed in the literature feature sampling frequencies from 200MS/s {0 1.8 GS/s with corresponding power consumptions from a few mW to 420mW. The offered ENOB ranges from 3 10 roughly 8, ‘Time- interleaving can also be used in combination with other ADC topologies, such as pipeline, flash or sigma- delta, However, designs reported in the literature show that Ti flash and pipeline A/D converters tend tobe inefficient for system-on-chip (SoC) wireless terminals. Infact, 8-channel Tlarrays of 6-bit flash ADCs and pipeline ADCs have been proposed, respectively, in [10] and [22]. A sampling fre- quency of several GS/s is achieved in both cases but at the expense of 1.6-W power consumption and an effective num- ber of bits (ENOB) limited to 5. On the other side, TI arrays based on sigma- delta ADC channels allow good Signal to Copyright © 2009 The Institute of Electronics, Information and Communication Engineers BS AW BG. SAAT on, Please confire: |Noise and Distortion Ratios (SNDR), 79 4B in [23], but the achieved signal bandwidths of a few MHz are generally not, enough for high speed wireless and wired communications, In this paper, we focus on TL SAR ADCs. Like all parallel topologies, these ADCs end with facing challenges such as the realization of the sampling function at high speed, and minimization or compensation of mismatch be- ‘tween the numerous elements in terms of bandwidth, off- set, gain and clock timing skew {6}, [14],[24]-(28]. Accu- rate quantitative evaluation of the impact of parallelism on global system performance and efficiency is less straightfor- ward than commonly thought, finally making the design of a TI ADC array a daunting task, likely to be unsuccessful if, not carefully planned at system-level. Traditionally, TI ADC specifications are mostly determined a priori by relying on designer's experience and heuristics, However, increasing, parallelism affects multiple ADC parameters among which an optimal trade-off needs to be found: accuracy, area, power consumption, clock frequency of the ADC channels, and overall sampling rate. Evaluation of these trade-offs, ‘which turn out to play a crucial role for successful design, are rarely performed at system-level, possibly leading 10 large discrepancies between desired performances and mea- sured results: compare as example the “ENOB” and “bits” columns in Table 1. 1.2. Mixed-Signal Design Space Exploration To overcome the possible limitations of traditional design, flows, in this work, we perform the design space exploration of a TI ADC through a rigorous mixed-signal system-level, methodology following a platform-based approach [29]. We ‘extend the seminal analysis reported in our conference pa- per (30] with the support of additional experimental results and discussions, further details on ADC modeling and de- sign, and comparison with the state of the art, To demon- strate our methodology, we focus on medium resolution fast, ADCs (up to 6 bits and 1 GS/s) for UWB receivers, where the SAR topology is particularly suitable to implement each, array channel ADC, according to the analysis in Sect. 1.1. However, our approach can be reused for any ADC topol- ogy. To allow fast but still accurate design space explo- ration, a meet-in-the-middle strategy is deployed based on a bottom-up and a top-down phase. A reconfigurable TI SAR, ADC platform is built, in which the number, sample rate ‘and resolution of the parallel components can be separately configured to investigate top-down several possible scenar- jos. A statistical behavioral model of the system is hierar- chically obtained by composing the models of its analog and, digital building blocks. Behavioral models include the prin- cipal circuit non-idealities, such as noise, non-linearity, and the combined effects of gain, offset, sample time and band- width mismatches. Model parameters are extracted bottom- up from real implementations of the ADC building blocks in 90nm I V digital CMOS technology. ADC performances are then computed in term of ENOB, SNDR and spurious, IEICE TRANS. ELECTRON, VOL.E92-C,NO.6JUNE 2008 free dynamic range (SFDR) through Monte Carlo simula- tions, Moreover, total power consumption and Figure of| Merit (FoM) are also evaluated as a function of resolution. ‘The FoM, traditionally employed to compare different ADC implementations in terms of energy per conversion-step, is calculated as Power/(f,-2*°%) (9 f, being the ADC sam- pling frequency. Since the ADC behavioral models are quickly executable and still anchored to feasible building block performances, our approach allows efficient and accu- rate performance estimations. The results of the design ex- ploration phase provide useful insight in performance degra- dations, which are usually hard to predict in the earlier de sign phases, thus avoiding time-consuming iterations in the design flows, a erucial issue when dealing with complex VLSI systems 2. Combined Channel Mismatch Analysis in TI-ADCs An M channel TI-ADC is made up of M ADC blocks that operate at only a fraction f,/M of the required sample rate Jo, and are connected as in Fig. 1. Every sampling time, a ‘de-multiplexer feeds the input of one of them with the ac- tual analog signal. Then it switches to the next converter. ‘Once the conversion cycle from every channel is completed, a digital multiplexer retrieves the corresponding data, The final result is therefore an ADC that operates atthe required sample rate f,. The ADC performance is heavily affected by undesired spectral components due to multiple types of ‘mismatches in the parallel channel parameters: offset, gain, timing (ie. clock skew) and bandwidth. While most TI ADC designs in the literature consider mainly gain and offset mis- ‘matches, inthis work we investigate the combined effects of all the above mismatches. To this aim we refer to the behav- ioral ADC channel model in Fig. 2. For each channel I the timing mismatch, ie. the devia- tion from the ideal sampling period 7, is modeled as a time shift of the input signal x(1). The transfer function Gi(jo), ideally equal to 1, captures the finite bandwidth filtering ef- sent) Digital fem Fig. 1 Block diagram of a TI ADC. wate Ty ie oid Fig.2_ Behavior model ofa T-ADC channel x“This “papaw Please confirm. SSAFONARA etal: ARCHITECTURAL EXPLORATION AND DESIGN OF TIMED fect of the sample-and-hold circuit (S/H) in each channel. Since a unique front-rank S/H, running at the overall high speed sampling rate f,, ends with limiting the number of channels that can be driven, we adopt a distributed time- interleaved S/H in this work. Finally, each channel has an ideal sampler and quantizer with a gain gy and an offset 0, Based on the channel model in Fig. 2, we briefly review the effect of these error sources on the sampled ADC output y(t) In absence of bandwidth mismatch, ie. Gi(ju) Fig. 2, fora given input signal x(¢) = A-sin(«pt), the Fourier transform of the sampled output y(t) assumes the form in Eq. (1) (see also [24)): > [Sol ~ oy KF) — yew = Ho (w+ am ~ 452) + s(o#%)| 2n YUw) = 4o E95 0 als ~ where 7, is the sampling period, , = 2x/;, alk] is the | discrete Fourier Transform (DFT) of the sequence 2) ge", BIR] is the DFT of the offset parameter sequence ‘01 and * denotes the complex conjugate. Equation (1) de- scribes the combined effects of offset, gain and timing mis- matches, leading to the following conclusions: 4) Offset mismatch. If offsets are not identical forall channel ADCS, spurious tone appears in the spectrum. The error assumes the form of additive noise causing peaks at frequencies multiples of /,/M. SNDR degradations duc to is error are independent of the signal amplitude and fre- quency. b) Gain mismatch. Gain mismatch errors are caused by differences in the gains gy of the various channels. The basic error occurs with a period of M/{, but the magnitude of the error is modulated by the input signal. ‘The error i ‘multiplicative in the time domain (like amplitude modula tion) and causes spectrum peaks at frequencies that depend on the input signal frequency. As inthe offset case, the error power is independent of fo although it depends on the input amplitude A. <) Clock timing mismatch. In addition of random clock jitter, affecting every ADC architecture, a systematic clock skew is also problematic for TI ADCs causing timing ations At; = ri from the ideal sampling period 7, for each channel ADC. Similar to a phase modulation noise, clock skew mismatch creates spurs atthe same frequencies as gain mismatch and therefore both errors interact with each oth- ers and cannot be distinguished. The error power in this case depends on both the amplitude and the frequency of the in- put signal. Moreover, as fy increases the signal power atthe ‘output is also decreased thus producing larger degradations in the SNDR. The last relevant source of SNDR degradation in TL ADCS is the mismatch between the finite bandwidths of the S/H in each channel, analyzed in literature in [26] but lim- will be printed tw nancchrome, ] to gles Dicins 1 ABC oe contd Gea — (ssn ek sean) ce tere re F/M] | | | ited to only 2 channel arrays. In this work, we extend the analysis (0 an arbitrary number of channels. The sampled ‘output from each channel can be approximated as the result Of the input signal passing trough a linear filter with transfer function given by: 2 ‘where 7 isthe time constant of the sampling circuit inthe track-mode, approximated as a first-order low-pass filter, and the tracking time is 7, For a sinusoidal signal, band. width mismatch includes @ combination of gain and phase mismatches. Differently from classical gain mismatches, both gain and phase errors predicted by (2) depend on the input frequency as well as the S/H bandwidth. Moreover, phase errors induced by bandwidth mismatch are a nonlin- ear function of fa as opposed tothe linear behavior of clock skew effects. As a final remark, we note that bandwidth mismatch limitations significantly decrease if the S/H band- width can be made much higher than the maximum signal that has to be digitized. ‘As an example, Fig.3 shows atypical output spectrum G a 6-bit TI ADC with M = 6 channels, sampling frequency ‘and input signal tone fo; we highlight the distortion con- Luibutions due to offset (inggeen), gain (i (blue), clock skew Cingrangs)and bandwidth (ined) 3. TI-ADC Design for UWB Applications 3.1 UWB Receiver Requirements We target our ADC to orthogonal frequency division multi- plexing (OFDM) UWB receivers for high data rates, hun- dreds of Mbjs, over short distances. Determining ADC specifications is a complex problem, which is mostly solved priori, in the literature, by simply relying on designer ex- perience and heuristics. A complete circuit level simulation and verification of an interleaved system in nominal condi- tions -left alone the feasibility of Monte Carlo runs- mayFig.4 Impact of the ADC accuracy on UWB system performances ‘become soon problematic. ‘An ADC sample rate of approximately 1 GS/s is gener- ally deemed as sufficient for wireless battery-powered con- sumer electronics applications {1],{2]. Determining the needed resolution, however, involves complex trade-offs among channel conditions, arithmetic accuracy and com- plexity in the baseband section. By simulating a whole UWB chain, including a transmitter (TX), a receiver (RX) and a channel, we have determined that an ADC resolution ranging from 4 to 6 bits is typically required atthe receiver side under reasonable channel conditions to minimize the mean square error (MSE) between transmilter and receiver data, Figute 4 reports the MSE as a function ofthe received power level P, (expressed in dBm), and considering differ ent resolution scenarios for the ADC and the digital process- ing part. The UWB scheme is implemented according to the Simulink system model in (31], based on a mode ! operation (200 Mbjs in the first three channels) and different channel conditions. When the received power level P, is lower than =754Bm, the MSE has a weak dependence on the digital resolution; therefore, a ¢-bit ADC is the best choice, since it allows reaching the same system performance of higher resolution ADCs with lower complexity and power costs Conversely, when the received power is inereased (due £0 better channel conditions ora shorter TX-RX distance or an increased transmitted power) a higher resolution ADC will improve the MSE system performance. We observe that such MSE improvement saturates with 6 or 7bits. Hence, 4 number of bits ranging from 4 to 6 leads to good trade- offs between accuracy and circuit complexity: 4 bits tend to be sufficient for very low power but lower rate applications (eg wireless sensor networks), while 6 bits are more suited for wireless multimedia connectivity o achieve high band- ‘width communication exploiting full channel capabilities. 3.2. TISAR ADC Design When a TLSAR architecture is selected to implement the ADC, mismatch induced performance degradations and en- ergy efficiency considerations may end with playing a cru- cial role in the final decision, In our approach, TI-ADC de- sign translates into mapping system specifications to a re- IEICE TRANS. ELECTRON, VOI.E92-C,NO.6JUNE 2009 Vine — Vay $4 ana Dac | ew Digital controler JP Bobs, Fig.5Digram of the reference channel SAR ADC. 4 Peed ye cant Fig.6 Dynamic comparator cite configurable platform, which means to properly select the key system parameters, such as sampling rate, number of channels M and resolution to match the requirements. To solve the mapping problem, the mixed-signal plat- form design space is first quantitatively explored through fast Monte Carlo simulations on behavioral models, anno- tated with bottom-up architectural constraints, The results of the preliminary study are then used to take system-level architectural decisions while defining, at the same time, the requirements of the ADC sub-blocks. Behavioral models are crucial to enable fast and accurate design space explo- ration. Therefore, in what follows, we first describe how models are built. ‘The channel SAR ADC is modeled bottom-up by us- ing the same parameters as in Fig. 2, and changing the ideal sampler and quantizer blocks with a more accurate SAR ADC model based on feasible implementations of the main building blocks in a 90-nm 1-V digital CMOS process. The reference SAR architecture, sketched in Fig. 5, is based on a fully dynamic topology and consists of a passive S/H cir- cuit, a regenerative comparator, and a SAR digital controller that drives a binary-scaled capacitive array acting as digital- to-analog converter (DAC), placed in a feedback loop with the comparator. The input signal is sampled only at the be- ‘ginning of the conversion cycle and then held for a number Of cycles equal to the resolution n of the ADC. An addi tional sample clock period T, is allowed for proper settling of the S/H. Therefore, the minimum number of channels for given resolution n will be Min = +1. The reference SAR ADC implementation relies on a fully dynamic compara: (or topology, sketched in Fig.6 (see also [9] and [20]). A dynamic comparator allows (i) minimizing the static power consumption and (ii) scaling the dynamic power consump-SAPONARA etal: ARCHITECTURAL EXPLORATION AND DESIGN OF TIME-INTERLEAVEDSAR ARRAYS tion with the clock frequency. Moreover, calibration tech- hiques are used to compensate technology spreading and mismatch, As far as speed is concerned, the dynamic cir- ‘cuit takes approximately 0.5ns to execute the comparison; considering thatthe time needed to reset the circuit and DAC settling is lower than 0.5 ns the whole time response is faster than 1 ns. As discussed in [21], exploiting dynamic circuits as in our work, instead of conventional opamp-based de- signs, also gives a contribution to the reduction of variabil- ity and manufacturability issues in DSM CMOS technol- ogy nodes. Finally, the SAR logic in Fig. Sis implemented, through asynchronous digital circuits to reduce power con- sumption and reduce the SAR algorithm computation time. With reference to the above described ADC SAR archi- tecture, the comparator and S/H thermal noise are modeled as random Gaussian generators with a given variance, ADC thresholds are finally perturbed to represent the static non- linearities (INL and DNL) of a real quantizer. Monte Carlo simulations are carried out based on the following assump- tions on mismatch statistics: + Channel offer 0; has a zero mean uniform probability density function (pdf inthe interval (LSB/4; LSB/4) since the use of the calibration circuitry we already adopted in [9] can provide offset correction in the > above range: + Channel gain gy has a Gaussian distribution with mean Ga; ‘Relative clock skew rin each channel has a zero mean Gaussian pa The channel S/H bandwidth by is a Gaussian variable with mean B. The mean bandwidth of the first oF- der low-pass filter approximation is computed by im- posing that a maximum LSB/4 sampling error is al lowed within the sampling time Ts. Tsy is equal 0 the time available for each SAR conversion step and can be expressed as Tsy = T,--Mj(n+ 1), and hence ‘fa = f(a 1)/M. The average bandwidth willbe: mae tt 2nd Bad ® ‘ebeing an additional design margin over the theoretical rminimum value. Comparator noise is a function of its power consumption. Noise variance has been estimated from a 6-bit SAR design, sized for a noise standard deviation c = 1.4mV~LSB/9 to, be conservative. For other resolutions, a “hard” scaling rule ‘would suggest that the owLSB ratio should be kept con- stant, Since this would lead to a 4 time increase in power consumption for each additional bit, we finally opt for a “soft” scaling rule, allowing only a doubling in the power consumption per bit. Therefore, the energy per comparison, is scaled with resolution based on the law in Eq. (4) which leads to the noise scaling relation in Eq. (5) Ecamp(t) = 2" Econp @ co) Based on Eq, (5), noise is allowed to decrease by only a 1.4- factor for each bit, so as to contain power consumption while keeping thermal noise sufficiently below the quantiza- tion error, 4, TI-ADC Design Space Exploration Results, 4.1 TI-ADC Performance versus Mismatch Sources ‘To investigate the sensitivity of a TI system to the different mismatch sources, we first performed Monte Carlo simu- lations on a 6-bit TI-ADC operating at 1.1 GS/s with ideal channel samplers and quantizers. A number of 1,000 samn- ples per run was made possible thanks to the assumptions on statistical distributions made in Sect. 3.2. Since one SAR comparison cycle Ts; is reserved for input sampling, the array is made up of 7 elements. Hereafter we define the de- sign yield at x-ENOB as the percentage of samples provid- ing an ENOB larger than x. In Figs.7 and 8 design yields at '5,5-ENOB are represented as a function of the standard de- Viation of the different mismatch sources. Yield is quickly degraded by timing mismatches showing how clock skew is the most critical error already for 6 bits. However, as shown in Fig.8, a 95% yield can still be guaranteed by a relative skew standard deviation o, = 3-10". This value corre- sponds to a 2.7-ps absolute standard deviation, which is not problematic to be realized, by leveraging, for instance, tun- able delay buffers, as in [32]. On the other hand, bandwidth mismatch is expected not to be an issue in our design (see Fig. 8). In our passive implementation, constraints imposed by linearity already called for such a high bandwidth & that te effects of mismatch became practically irelevant to the final SNDR. In fact, asa reasonable margin for good linear- ity, the S/H is designed to provide an effective number of Year ae aaa Fate ost darth (58) Fig.755-ENOB yield as a function of normalized offset (ro/LSB) and tin (7y/@) standard deviations in abit TLADC.tr a as ate ig.8 —5.S-ENOB yield as «function of clock skew (7/73) at Nyquist and bandwith (7 /B) standard devistions in 6-bt TT ADC. bits that exceeds by at least 2 bits the nominal ADC reso- lution. As far as the signal dependent non-linear transistor resistance is the major source of distortion in a passive S/H circuit, the lower is the resistance value the higher the lin- carity will be. Therefore, low resistance values would call for bandwidths as high as 5 GHz in our design, to get the desired S/H linearity. As implied by (2), such high band- widths (ic. low time constants) would cause the impact of ‘bandwidth mismatch errors to be finally negligible for the overall ADC performance. 4.2. T-ADC ENOB versus Array Size and Nominal Reso- lution While Figs.7 and 8 refer to accuracy degradation for a 6-bit ‘7-channel TI ADC vs. different mismatch source variances, the combined effect ofall mismatches could be also evalu- ated as a function of the number of array elements and the target nominal resolution. To this aim a frst set of simula- tions was performed to find out the resolution offering the best trade-off between performance and cost, the latter ex- pressed in terms of circuit complexity and power consump- tion. As practical values for the mismatch source variances, ‘we chose those values that guaranteed a 98% yield (at the 5.5-ENOB level) for the 6-bit TI-ADC in our previous ex- plorations. All sigma are de-facto independent of the reso- lution of the converter, except forthe offset variance, which scales with the LSB because of the offset compensation net- ‘work that needs to be sized according to the ADC resolution. Experiments were performed in two cases: ideal quantizer, where the quantizer in each SAR ADC ‘channel gives no distortion and noise contributions (the per- formance degradations are only due to the contribution of channel mismatches); ~ real quantizer, where each SAR ADC channel has a noise source, as determined in Sect. 3.2, and maximum static non- linearites as reported in Fig. 9, The latter shows the INL and IEICE TRANS. ELECTRON, VOL.E92-C,NO.6JUNE 2009 Fig.9 Maximum INL and DNL of a SAR ADC with al quantizer as @ funeson ofits nominal resoaton Fig. 10. ENOB and SFDR as function of resolution (ry = 0.08 LSB, e910 = O88, 017, ‘Table Mean ENOB and quantiles a 10% and 90% in a TISAR ADC inthe rea quantizer ease Ug = 500M) z “ 37 AT «582 60262 368 45390 Sal S98 90% 36446526 S88 ST DNL values for a SAR ADC (Fig. 5) implemented at differ ent resolutions. Estimations in Fig. 9 are based on extrapo- lations from areal SAR ADC design (20). In such ease, per- formance degradations are due to both channel mismatches and quantizer nonidealities. Figure 10 shows the average ENOB and SEDR as a function of resolution from 4 to 9 bits for both the real and ideal quantizer cases. Table 2 reports, for the real quantizer case, the average ENOB with the 10% and 90% quantiles, conveying an indication of the ENOB distribution. Because of channel mismatches, the ENOB curve saturates both for real and ideal quantizer cases. As @ matter of fact, using more than 8 parallel elements (to implement a 7 bit ADC) tum into a waste of power and area for the tested values of rmismatches, since trying to compensate these errors via dig- ital or analog calibrations might also end with augmenting power consumption and complexity. Results are even worse'SAPONARA etal: ARCHITECTURAL EXPLORATION AND DESION OF TIME:NTERLEAVED SAR ARRAYS Fig. 11 Average ENOB as fonetion of input signal frequency in a bit, channel ADC with rea quantizers (= 0.08 LSB, cjg = 08%, err, = 027%, 7579 = 7). in the real quantizer case, where additional 0.2-bit ENOB degradations are observed with respect tothe ideal case, al- ‘most independent of n. Similar conclusions can be drawn from the SFDR plot. Both ENOB and SFDR are simulated and computed at Nyguist conditions, with an input signal frequency of 500 MEV ‘To gather more insight into typical ADC dynamic per- formances, Fig. 11 shows the average ENOB as a function ofthe input signal frequeney for a 6-bit (7 channels) ADC based on real quantizers. In nominal conditions, the ADC effective resolution bandwidth (ERBW) is basically limited by the S/H bandwidth, which can be a high as 5 GHz, based on the design criteria exposed in Sects.3.2 and 4.1. In the presence of bandwidth and timing mismatches, following the behavior summarized in Sect.2, the ERBW tends to de- crease. However, bandwidth and timing error deviations in cour experiments are such thatthe ERBW is stil well beyond the Nyquist frequency in practically all cases (e.g. ERBW > 560 MHz. with probability 0.8 under the assumptions in Figs. 10 and 11), which allows us to still use the formula in Sect. 1.2 to compute the FoM 4.3. Effects of Parallelism on TI-ADC Accuracy, Area and Power Consumption Another objective of our analysis is the TI ADC accu- racy, power consumption and area characterization, when the number of array elements is increased for the same nom- {nal resolution. Increasing the number of channels above ‘Mr felaxes the speed requirements of each SAR ADC and increases the sampling time available to the S/H thus redue- ing the effects of bandwidth mismatch. Simulation parame- ters have been set considering an ADC SAR channel based, (on a real quantizer. As shown in Fig. 12, implementing a 6-bit converter by interleaving 7, 8 or 9 elements has a neg- ligible impact on performance since the variations in ENOB are less than 0.05 LSB. Although the S/H could take advan- tage of the additional time for settling, the beneficial effects, ‘of bandwidth mismatch error reduction are not clearly ob- Fig. 12 ENOB as a function ofthe numberof parle elements for the same nominal solution, served because of the high S/H bandwidth, Increasing parallelism for a fixed resolution leads to an area penalty roughly proportional to the number of added ‘channels while its effect on the total power consumption is not relevant. In fact, power consumption can be expressed as in Eq. (6) as a function of the SAR energy per conversion Econ and the array size M : n ae Feo fe being fy the frequency of each SAR conversion step which, given a fixed bit resolution m and a fixed sampling frequency fis proportional o (n+ 1)/M. Equation (6) leads toa good estimation ofthe energy scaling under the assump- tions, physically reasonable in our case given experimental results on the 90nm 1 V CMOS SAR ADC implementation, that: Pig = MP cy = M- NE confer o (i) the SAR ADC channels are the dominant source of power consumption in the whole TI ADC; i) cach SAR channel is based on dynamic circuitry where the power is dominated by the comparator and by the digital controller performing the search algorithm (the ‘S/H consumes less than 10% of the comparator power in our 90-nm prototype). Asa result of the analysis, when the parallelism is increased (TM) the speed requirements of each channel are decreased accordingly (L fs), being the power consumption in (6) only a function of the resolution and the sampling rate of the TLADC. Moreover, to simplify our energy estimations, Bem in (6) is assumed as composed by an analog contribution, which roughly doubles each time one bit is added (see also Sect. 3.2) and a digital contribution, which is almost inde- pendent of the ADC resolution (in the considered range 4~ 8bits). 5. TIADC Implementation In addition to ENOB and SFDR, analyzed in detail in Figs.7, 8, 10, 11 and 12, low power consumption has a key role in determining the best ADC architecture for our ap- plications. ‘To this aim, the total power consumption and the figure of merit (FoM) have been evaluated as a function ‘of the nominal resolution and are represented in Fig. 13. In Figs. 10 and 13 the array size M is equal to n+1. Given the results of Figs. 10 and 13 an 8-element 7-bit TI SAR ADC has been selected asa good compromise for our target UWB8 =? Fig. 13 Power consumption and FoM a a function of T|ADC nominal resolution, application. Although our selection relied on Monte Carlo simulations performed on behavioral models, we note that the models are built bottom-up from measurement results of a prototype SAR ADC channel in 1-V 90-nm CMOS tech- nology [20]. Based on the reference SAR implementation, the selected design offers a 5.81 average ENOB and 43.6- 4B average SFDR. The power consumption, dominated by ‘dynamic power, amounts to 8-mW with a FOM of roughly 14013/Conversion-step and 0.41 mm! area occupation. A 7- clement 6-bit TI SAR ADC design is also competitive in ‘our performance range. In spite of a 0.42-bit ENOB degra- dation (5.39 mean ENOB, 43-4B SFDR) with respect to the 8-element 7-bit TI SAR ADC, it would cost less power (4.6mW) and less area (0.17 mm), while achieving an im- provement in the FoM (110f/conversion-step) higher than 20%. After further tuning our modeling framework based ‘on experimental results from our prototype, we observed a slightly lower speed rate (1 GS/s instead on 1.1 GS/s) with respect of [30], and a FoM increase of roughly 10% for both 7- and 8- element TI SAR ADCs. Since the time spent for each SAR iteration is roughly I ns, few can reach 1GHz and the target f, of I GS/s can still be reached using M = Min = n+ 1. AS discussed in Sect. 4.3, increasing par- alletisin would lead to an area increase not counterbalanced by a power consumption saving, ‘Comparing the achieved results to the state ofthe art in Table 1, itemerges how the proposed TI SAR ADCS bring a more effective trade-off among the multiple cost functions. With respect to [11]-[13].[15H{17), our designs achieve better FoM with similar or better ENOB and sampling fre- quency. With respect to [4] our designs offer lower ENOB and sampling frequency (mainly due to a different target ap- plication case), but power consumption and FoM up to one order of magnitude lower. 6. Conclusions ‘The paper proposed a system-level design approach of high- speed and low-power TL ADCs for ultra wideband com- munications. Mixed-signal design space exploration of a TI SAR architecture is performed top-down via Monte Carlo simulations, by exploiting behavioral models built Phoose. shay all a: TICE TRANS, ELECTRON, VOLLE2-C, NO.6 JUNE 2009 bottom-up after characterizing the SAR ADC blocks. Such characterization is based on measurements of a proto- type ADC channel chip in 90nm IV CMOS technol- ogy. Although parallel SAR architectures remain promis- ing for high data rates and medium resolutions (5-7 bits, up to 1GSs), it was shown that their efficiency advan- tage over other approaches can be relevanily overcome by mismatch errors. Careful system-level planning is there- fore a must when designing these systems. To this aim different speediresolution scenarios were investigated and the impact of architectural/circuital choices on performance, yield, power consumption was assessed starting from the early design phases. Based on exploration results, two TL SAR ADC configurations (a 6-bit 5.4-ENOB with FOM of 110f/conversion-step and a 7-bit 5.8-ENOB with FOM of 140f)/conversion step) were proposed, effectively trading performance for power consumption and area. Compared to state-of-art TL ADCs with similar accuracy and sampling rate constraints the proposed designs are able to offer better FoMs. Mae Tie 6 BAAN TT (1)/M. Cummings and, Cookies, “Tara: Softwire-defned radio. “IEEE ICCD 2007, p. 103-10, 2007 ra. wideban: Multimedia unploage Yel, n09,pp2-27, Sept 203 (YRS. Shera. @tal "Numeral pression requirement onthe multi tad wlravidetand system for practical consumer electronic de ‘ees IEEE Trams, Consum, Electron, vol SI, 386-392, 2015 (8) 5. Louwsna, A. van Tul M. Verte and B. Nava, A 1356S), 10b, 175 mW cine-intrcaved AD canes in 013m CMOS TEEE J. Soli State Cit, v3, nod 778-786, 2008 GYN.Linsalaa,a Automate syne of os etectve FFTAPET cores fr VESIOFDMsytens"IEICE Tats. Elecwon, voLED1C, 0 87-496, Apa 208 (61 K. Atami, "An algorithm to improve the performance of M chanel ime iteresved AD conver” IEICE Tras, Fudan. tls, voLE9O-A, no 12 pp. 2846-2852, De. 207 (7) Z.Cao,. Ya, and ¥.13,°A 32m 1.2565 & Shep ADC in (134m CMOS," Proc. IEEE ISSCC2008, p 42-543, 2008, (8) X.Jiang, . Wang, nd M.F Chang, “A 2G8) 6b ADC in 0.18 {CMOS)"IEEE ISSCC 2003, p,322-497, 2008, (©) P Nurs ¢a)°A 10 6m 085 powcrscalble 1 SIs 4 ADCin (184m CMOS with 58s ERBW?” IEEE DACO, pp 875-878, 2008. (00) YC tang 1H. Bae, and SH. Pa, “An 88.05)5 61 CMOS 5 imeliericavd lash Analog toga Cone wit a (Phas nek lve” IEICE Trans, Eesti, 1 EOC, 6, PP 1136-1164,2007. Fane, Ginsburg abd A. Chirhaan, “Dus ne-intereaved suces sive apoxination rept ADCs for an uta- wideband recive” TEE Sol-Sate Cui, ol 2, 02 pp. 247-257, 207 D.Draselnayt, "A 6008s 10m ADC ary in ig 90am (CMOS,"IEEE ISSCC Dig. Tech. Papen, Feb. 2004 S.Dondi(al)"A 6: .2Glzinteresed SAR ADC in 9 ‘CMOS TEBE PRIME 2006, pp 301-304, 2006. KC Dyer al) "An analog background cairn ecnique for ‘ine iterlevedegalogo-ighal convenes” IEEE J, Soli State Circuits, 01.33, n.12, pp1912-1919, B Ginsburg and A. Chandrataan, “Highly inerteaved 32500455 ADC with redundant channels in 6S nm CMOS,” IEEE ISSCC200, Senet wee | Please. chon Refereness IEEE Spectr, no. AdT ers'SAPONARA etal: ARCHITECTURAL EXPLORATION AND DESION OF TIME INTERLEAVEDSAR ARRAYS (161 B. Ginsburg and A. Chandrakasan, "S00-MSs Sit ADC in 6S-nmm ‘CMOS with split capcitorseray DAC? IEEE. Solid-State Cres, vol, not, pp. 739-747, 2007. UML ¥. Ob and’ B Mormann, “A low-power 6-it ineinteresved SAR ADC wsing OFDM pilot tone calibration” IEEE CICC 2007, p193-196, 2007 (08) S.¥. Ng, B. Jalal, P. Zhang, J. Wilson, and M. Ismail, “A Tow voltage CMOS 5-bit 600Mliz 30mW SAR ADC for UWE. wie- " IEEE Midwest Symposium on Circuit and Systems Sergio Saponara got the Laurea degree, ‘eum laude, and the Ph.D. in Electronic En neering fom the University of Psa i 1999 and 2008 respectively. In 2002 he was with IMEC, Lewen (B), as Marie Curie Research Fellow Since 2001 he collaborates with Consorco Pisa Ricerche in Pisa, He ie senior esearcer at Uni versity of Pisa inthe feld of electronic circuits and systems for telecom, multimedis, space and ‘pp. 187=190, 200s, Automotive applications, He holds the chair of [19] F. Erato, A. Agnes, B. Bonizzoni, and F, Malober, “Design of clectonie systems for auomotive and atoms an ultra low power tine interleaved SAR converte” IEEE PRIME ton atthe Faculy of Engineering, He co-authored more thn 90 scenic 2008, pp.245-248, 2008. publications and patents, (29) 4. Craninckx and G. Van der Pas, “A 65 Sjconversion-step, O= '50MS/s0-0.7 mW Dbitcharge-sharing SAR ADC in 90 nm digit ‘CMOS," IEEE ISSCC 2007, pp.246-247, 207, 21) A. Matsuzawa, “Design challenges of analog-t-dgital converters in nanosale CMOS," IEICE Trans. leceones, volE90-C, n04, p.779-185, April 2007 'A. Nazemi,aL"A 10.3GSJs Obit (5.1 ENOB at Nyquist) ime inerleavedpipelined ADC using open loop amplifiers and digital calibration in 90m CMOS," IEEE Int. Symposium on VLSI Cie cis 2008, pp. 119, 2008, (23) K Les, aL) °A nose-couped tine interleaved AE ADC with 42MHz BW, -984B THD, and 7948 SNDR," IEEE 1SSCC2008, Pierluigh Nuzzo graduated cur laude) in lecuonic Engineering from the University of Pisa, Ialy, and the Sant Anna School of Ad ‘anced Suds of Ps, From 2006 © 2008, he was a esearcer inthe Wireless Reseach group ‘of IMEC, Leuven, Belgium. He is now grad uae student in electrical engineering snd com: puter sciences atthe University of California, Berkeley. His research interests include design pees, 208 tstomnfon of mci! st, ow power (24) © Nog, “he ingest of combine cans! mismatch ees in Ih amlog, a mince het dese Scimvicned ASCr” TSE a. ntam, Mets wos ma, CMOS holo, embeded soem sign mato. He eed psa 2, fn place nthe Sprionalegry ands over abo ae (25) Pu.Q@al)A cig background cabin wcniue frtie- 2006 DACISSCC Het design competion ineseavedanalog-o-dgital converters” IEEE J. Solid-State Ci- cats, vo33,no.12, pp. 1904-1911, 1998 {26)) 7-H. Tsai, @ al) "Bandwidth mismatch and its conection in ie 7 tricaved stog-te-digial converters" IEEE Trans. Ctcuts Sys Cutt Nani got the Laurea dere in Elec To 33, no 10, pp. 1133-1137, Ot 2006. toni Engineering, stm cum ade, fom the (27) Z.Li, K Honda nd. Kavaito, “A new calibration method for Unis of Ps in 207, an the Diploma in sampling clock sew in ime itceaved ADC.” IEEE tn Inst Abd ‘gineering fro the San Ana Schoo of Ad ___ Measurement Techeology Conference, ptt May 2008." Ci) anced Stiis, Pia, in 2008. Dating 2007 (2s) Robey aL Algritns or dig conection of ADC 20 he was with IMECINES, Begiom, working linearis” IEICE Trans. Fundamentals, voLES®-A, 90.2. ppSOt> fp on Jw power data omer," Cuneily he 508, Feb. 2003 ie wit NXP Semiconductors Resch, Eind- hoven (NL) where he works on highspeed data (29) De Benin, P Naz, and A. Sangioann- Vice “Mixed signal design spice exploration togh slog platen IEEE DAC 200, p58 2008 (20) Naan. Nas 8. Sapna, Lancs, nd. Van dor Pas, “Mixedsignal design spe exploration of tineseewes A/D comer fr ule tad spplcons.” IEEE DATE 2008 1390-1393, 208 (31) MClark(et al) "Ultr- wide band (UWB) multiband OFDM physical afer with He poin ansmiteresver modeling” May 2008, ‘rv naw cononpenyncltergetayO in] (G2) Caan, Danan, A Saban, Sib, ‘Bena ra) ‘Dyeami thal cock saw compassion sig tenable ly ble IEEE Tne. Vary Large Soe nee (WLSD Sy vol 16, 0.6 9959-68, he 208 Geert Van der Plas is Principal Scientist in the Wireless Research group of IMECINES. He obtained the MSc. and PhD. degrees frm the Katholieke Universitit Leaven (KUL), Bel- ium, in 1992 and 2001, respecvely. From 1992 to 2001, be was a Researcher at ESAT. MICAS Laboratory of the KUL, where he ‘worked inthe fed of mixed-signal design, mod cling and design automation. Since 2003, he hasbeen with the design technology division of IMECINES, Belgium, where he has been werk ing on enerayeficint data converters and low-power scalable radios. He tas been the author and coauthor of over 75 scene paper‘Luca Fanucct got the Laurea andthe PAD. degrees in Electronic Engineering from Uni verity of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with ESA/ESTEC, Noord (NL), a5 esearch fellow. From 1996 ‘o 2004 he was senior researcher ofthe CNR. Jn Pisa. He is Professor of Microelectronics at the University of Pisa. His escrch interests in- slde VIS architectures for integrated circuits and systems. Prot. Fanuccl co-authored more than 180 scientific publications and he holds ‘more than 10 patents. He was program chair of IEEE Euromicro DSD 2008 and IEEE DATE Designers Forum, IEICE TRANS, ELECTRON, VOLLES2-C, NO.6 JUNE 2000