GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology

(ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

Reducing the Test Data Volume by Enhanced

Compression Code
1Devi

Sowndarya K.K. 2Kalamani.C 3Dr.K.Paramasivan

1,2,3
Department of Electronics and Communication Engineering
1,2
Dr.Mahalingam College of Engineering and Technology, Pollachi-642002 3Karpagam College of
Engineering, Coimbatore-641032
Abstract
Because of the increased design complexity and advanced fabrication technologies, number of tests and corresponding test data
volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System on- aChip (SOC). Test data volume reduction is an important issue for the SOC designs. Several compression coding schemes had been
proposed in the past. Run Length Coding was one of the most familiar coding methodologies for test data compression. Golomb
coding was used in existing compression side. The compression ratio of golomb code was found to be lesser than the combined
Alternative Variable Run-length code (AVR) and nine code compression (9C) methods. The proposed combined AVR and 9C
codes are used for reducing the test data volume. The experiment is conducted for proposed methods using ISCAS89 benchmark
circuits. The experimental results shows that, the proposed method is highly efficient when compared with the existing methods.
Keyword- SOC, Integrated coding, FSM, Test Data Compression, efficiency
__________________________________________________________________________________________________

I. INTRODUCTION
The complexity of VLSI continues to grow; more number of transistors is integrated on a single chip and test data volume has
drastically increased. The testing cost and testing power are two major issues in the current generation integrated chip testing.
Testing cost is related to test data volume. The cost includes a number of parameters, but the major one is the cost of Automatic
Test Equipment proposed by Pranab.K. Nag et al. Such it is difficult to transmit huge test data from ATE to system-on-a-chip
(SOC). The commercial ATEs have limited memory, bandwidths and I/O channel capacity. Testing cannot precede any faster
than the amount of time required to transfer the data:
Test time >= (amount of test data on tester)/ (number of tester channels)*(tester clock rate)
As we can see from the above equation that the test time is directly proportional to the test data hence we can reduce this
test data to reduce testing time proposed by Pranab.K. Nag et al. The testing time of SOC directly impacts the test cost. It is
determined by several factors, including the test data volume, the test required to transfer test data to the cores and the maximum
scan chain length. While test data volume reduction techniques can be applied to soft and hard cores, scan chains cannot modified
in hard (IP) cores. New techniques are therefore needed to reduce the test data volume, decrease testing time, and overcome ATE
memory limitations for SOCs containing IP cores.
Build-in self-test (BIST) proposed by S.Lei et al has emerged as an alternative to ATE-based external testing. It allows precomputed test sets to be embedded in the test sequences generated by on-chip hardware, supports test reuse and at speed testing.
Test data compression offers a promising solution to the problem of reducing the test data volume, special when the cores are not
BIST ready.
The test volume reduction consists of compressing the original test data, storing the compressed data in ATE, and then
decompressing them for restoring the original test volume. Three basic methods for reducing test data compression: proposed by
N.A.Tauba and Abramovici.M et al Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based
schemes. An alternative approach for reducing test data volume for SOCs is based on the use of data compression techniques such
as: proposed by N.A.Tauba Run length based, Dictionary based, Statistical codes and Constructive codes. In this paper we will
concentrate on run length based codes. The proposed work has been compared with Golomb code was proposed by Priyanka
Kalode et al, AVR was proposed by B.Ye, FDR was proposed by A.Chandra et al, EFDR was proposed by H.Aiman et al and Nine
code compressions was proposed by Usha S. Mehta et al. All these are variable to variable run length code. Golomb code, AVR
and nine code compressions are discussed in details so that there functionality is clear as the proposed work is based on these
codes.
The organization of the rest of the paper is as follows: Section II contains the discussions of Golomb and AVR codes. Section
III contains the discussion of Enhanced compression code (ECC). Section IV contains the Decompression Architecture. Section V
shows some of the Parameter Analysis. Finally section VI shows the Conclusion and Future Work.

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II. RUN LENGTH BASED CODES

Run-length coding is a form of data compression in which runs of data are stored as a single data value and count, rather than as
the original run. One particular variable-to-fixed coding scheme, the symbols consist of runs of consecutive 0s or 1s. Various
coding schemes have been discussed in section 1. Three of which are discussed below.
A. Golomb code
Golomb coding is lossless data compression algorithm. The Golomb code code was proposed by Priyanka Kalode et al that encode
runs of 0s with variable-length code words. The code words are divided into groups of equal size M (M is power of 2). Golomb
coding is implemented using following three steps:
1) Fix parameter M to an integer value.
2) For N, run length to be encoded find
Quotient, q= int [N/M]
Remainder, r= N modulo M.
3) Codeword generation:
Code format=<Quotient code><remainder code>
where,
Quotient code: Quotient is represented in unary code. In this we get unary code by representing q strings of 0s followed
by 1.
Remainder code: Remainder is represented in truncated binary code.
If M is power of 2 then code remainder as binary format using log2M bits. If m is not a power of 2, set b= . If r<2b-M
code r as plain binary using b-1 bits.
Group
A1

A2

A3

Run
Group
Tail
Codeword
length
prefix
0
0
00
000
1
01
001
2
10
010
3
11
011
4
01
00
0100
5
01
0101
6
10
0110
7
11
0111
8
001
00
00100
9
01
00101
10
10
00110
11
11
00111
.
.
.
.
Table 1: Golomb coding for M=4.

EXAMPLE:
TD: 00000011111111111100001000100000001111100001 No. of
bits:44, M=4
TE: 1010 000 000 000 000 000 000 000 000 000 000 000 000 100 011
1011 000 000 000 000 1000
Encoded bits=67.

B. Alternative variable length code

The alternative variable run-length code is also a variable to variable length code, consisting of two parts the group prefix and
tail was proposed by B.Ye. The prefix identifies the group in which the present run-length lies and the tails tells about the number
of ones or zeros (run length) within the group. The difference between other variable run-length codes and this code was that there
were two group prefixes in each group. The second prefix was the inverted data of first prefix in the same group. Each prefix was
associated with half of the data from the group. The test data can be classified into runs of zeros ending with a one and runs of
ones ending with a zero.
Group
A1

A2

Run
length
1
2
3
4
5
6
7
8

Group prefix

Tail

01

0
1
0
1
00
01
10
11

10
001

Code
word
010
011
100
101
00100
00101
00110
00111

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9
110
00
10
01
11
10
12
11
13
0001
000
14
001
......
......
20
111
21
1110
000
22
001
.
..
Table 2: AVR code compression.

A3

11000
11001
11010
11011
0001000
0001001
......
0001111
1110000
1110001
..

EXAMPLE:
TD : 00000011111111111100001000100000001111100001
No. of bits: 44
TE : 001011101010010000110101101
No. of bits : 27

III. ENHANCED COMPRESSION CODE

The drawback of the Golomb code is that it is beneficial only for the runs of zeros. This was evident from the experimental results.
Hence it was needed to encode runs of ones also. Although AVR was efficient enough in encoding ones but move from one group
to another it increments two bits in the code word. The codes are used depending on the run length. Now AVR and Nine code
compression is merged. The code provides minimum number of bits to a particular run length is used.
A. Nine code compression
Nine-coded compression technique was proposed by Usha S. Mehta et al considers the input test data block size of fixed length.
Each input test vector is partitioned into groups of bits with particular size called as block; say K and the block size is user defined.
The block size is selected as even, so that each of these blocks can easily be divided into equal halves such that the halves may be
all 0s, 1s or a set of mismatched bits, that is, a mixed group of 0s, 1s and X-bits.
Cases
1
2

Input block
0000 0000
1111 1111

Symbol
00
11

Code word
0
10

3
4

0000 1111
1111 0000

01
10

11000
11001

5
6
7
8

1111 uuuu
uuuu 1111
0000 uuuu
uuuu 0000

1u
u1
0u
u0

11010
11011
11100
11101

uuuu uuuu

uu

1111

Table 3: Nine code compression.

EXAMPLE:
TD: 001011101010010000110101101. No. of bits = 27
TE: 1111111111111111. No. of bits = 16

Therefore the compression has improved by 63.3%.

IV. DECOMPRESSION ARCHITECTURE

A. Decoder of AVR
The on-chip decoder decompresses the encoded test set TE and produces the primary test set TD. The decoder architecture is
similar to the on-chip decode architecture of Golomb code and AVR code. The testing time was reduced because test pattern
decompression could be carried out at higher clock frequencies. The lmax is the longest run of zeros or 1s in TD, and
k=log2(lmax+4)-2. The decoder is made up of a k+1- bit counter, a log2 (k+1) bit counter, a T flip flop and an exclusive or
gate. It has following signal.
The select line tells us which code was used for encoding. Bypass signal reflects the bypass mode.
Bit_in is the input of FSM and an enable signal en was used to control the input encoded data when the decoder was ready.
Signal shift was used to control the prefix and tail of the codeword to shift into the (k+1)-bit counter.
Signal dec1 was used for decrement, and rs1 was used to indicate the reset state of the counter.

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The second counter of log2 (k+1) bit was used to count the length of the prefix and tail in order to identify the group. The
signals inc and dec2 were used to increment and decrement the counter, respectively.
The FSMs output signal out controlled the toggle of the T flip-flop, and indicated that it had finished decoding runs of 0s or
1s before decoding runs of 1s or 0s according to the binary parameter . Signal v indicated when the output was valid and it
was used to control the scan clock signal scan_clk.
The operation of decoder was expressed as follows:
Step 1: In the initial state, the T flip-flop was reset to 0. Signal en become high and ready to receive data from bit_in.
Step 2: The FSM fed the (k+1)-bit counter with the prefix. The end of the prefix was identified by the separator 0 or 1 according
to code word type. The signal en, shift and inc were kept high until 0 or 1 was received. If the prefix was inverted in the (k+1)
bit counter. For example, if the prefix was 1110, then the data in the (k+1)-bit counter would be 0001.
Step 3: The FSM output, 0s and 1s decrement the (k+1)-bit counter and made the signal dec1 high. It continued it until rs1 is
high. The v signal shows whether the output was high or not. The tail part was again shifted to (k+1)-bit counter, but it was
under the log2 (k+1)-bit counter. It controlled the length of the control word.

Fig. 1: Decoder Architecture.

B. Decoder of Combined AVR and 9c

It consists of two Finite-State Machine (FSM) blocks, one synchronization block, one counter, a MUX, and the control signals.
The decoder operates on two clocks the external clock ATE_CLK and the internal clock SOC_CLK. The FSM1 is of 9C and
FSM2 is of AVR. The FSM1 receives the compressed data, DATA_IN from the ATE at ATE_CLK frequency. Once the FSM1
detects the code word, decoding begins at the system clock frequency (SOC_CLK) and the DEC_EN is set to 1. When FSM1
decodes the data, it does not receive any data from the ATE. The ACK_H is set to 1, as soon as the FSM1 decoded the code word
and it is ready to receive the next code word. The FSM2 receives the decoded data from FSM1 at the frequency of the system clock
was proposed by Shurti Chadha et al and Usha S.Mehta et al.

Fig. 2: Decoder of combined AVR and 9C.

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V. PARAMETER ANALYSIS
Power dissipation is an important problem for the circuit under test. A huge amount of power is dissipated when the circuit elements
switched from logic 1 to 0 and vice versa. Next, we analyzed the testing time when a single scan chain was fed by the AVR decoder.
Test data compression decreased testing time and allowed the use of a low-cost ATE, running at a low frequency, to the core
without imposing any penalties on the total testing time. The efficiency is used to compare the different codes with each other,
where
Efficiency=

(Total no.bits inTDTotal no.bits in TE )

(Total no.bits inTD)
TD TE

TD

100

100

Where TD is the original test data and TE is the data archived after compression.

Fig. 3: Schematic Diagram of combined AVR and 9C.

Parameters

Nine
code

Combined
AVR and 9C

Area (m)sq

Alternative
variable
runlength code
6866

350

7437

Time (ps)

142

171

381

Gate Count
(m) sq
Power (nw)

6866.334

350.208

7437.132

50165
4688
53191
Table 4: Decompression Results.

Fig. 4: Simulation results for compared codes

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Circuit

Original number
of bits

FDR % compressed

EFDR
compressed

Golomb
code
compressed

Comb AVR and 9C

% compressed

s5378
s9234

23754
39273

48.02
43.59

51.92
45.89

-3.23
36.80

65.7
74.08

s15850
s38417

76986
164736

66.22
43.26

67.99
60.56

63.49
86.01

86.06
96.95

Table 5: Compression results for compared codes.

VI. CONCLUSION AND FUTURE WORK

Proposed data compression techniques are implemented using MATLAB 13.0 language, Xilinx 14.2, schematic diagram is taken
using Cadence, the experiment is conducted using large ISCAS89 benchmark circuits and the results show that there is a
significant improvement in the compression ratio. So this technique combined with other techniques gives better compression. The
ISCAS89 sequential benchmark circuits are used here. So only specified bits are considered. The future work is carried out for
test data compression scheme based on Compatible data block coding.

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