IJSRD - International Journal for Scientific Research & Development| Vol.

4, Issue 02, 2016 | ISSN (online): 2321-0613

PF Corrected Converter Based PQ Fed Multiple Output Switched Mode
Power Supply
S.Balaji1 K.S.Yamuna2
Department of Electrical and Electronics Engineering
1,2
Sona College of Technology(Autonomous) Salem – 636005,Tamil Nadu, INDIA
1,2

Abstract— Multiple output Switched Mode Power
Supplies(SMPSs) for personal computers (PCs) normally
depict extremely bad power quality indices at the utility
interface such as total harmonic distortion of the input
current being more than 80%, and output voltage regulation
being very poor. Power quality is an issue that is becoming
increasingly important to electricity consumer at all level of
usage. Power quality is disturbed mainly for two reasons
one is due to Harmonics generated and other is reactive
power. In order to maintain power quality certain techniques
and equipment should be added. In this paper, a nonisolated
power factor corrected (PFC) converter is being proposed to
be used at the front end to improve the power quality of an
SMPS for a PC. The front end converter is able to reduce the
100 Hz ripple in its output that is being fed to the second
stage isolated converter Analysis has been made and
simulation result has been verified.
Key words: Power factor corrected Zeta converter, unity
power factor, power quality, SMPS, multiple output
I. INTRODUCTION
In the present era, personal computers (PCs) have become a
part of our day to day activities from business to education
to infotainment. Switched Mode Power Supply (SMPS) is
an integral part of the computer that converts ac to
multiple numbers of suitable dc voltages to impart power to
different parts of the PC. It contains a diode bridge rectifier
(DBR) with a capacitor filter followed by an isolated dc-dc
converter to achieve multiple dc output voltages of different
ratings. The uncontrolled charging and discharging of the
capacitor result in a highly distorted, high crest factor,
periodically dense input current at the single phase ac mains;
this violates the limits of international power quality (PQ)
Further, the neutral current in the distribution system
increases if these PCs are used in large numbers which
creates serious problems like overloading the neutral
conductor, noise, de-rating of the transformer, voltage
distortion etc..
To end these problems, improved PQSMPSs that
are capable of drawing a sinusoidal input current at unity
power factor (UPF) and yielding stiffly regulated output
voltages, are extensively being researched. Employing
various power factor corrected (PFC) single-stage and two
stage converters effect a perceivable PQ improvement in
these SMPSs. PQ improvement is visible in the form of low
total harmonic distortion (THD) in the ac mains current and
power factor being close to unity at the point of common
coupling (PCC). This is achieved even under varying loads
and supply voltage conditions.
The selection of operating mode of the front end
converter may be in Discontinuous Conduction Mode
(DCM) if the cost is a major consideration; if not,
Continuous Conduction Mode (CCM) is adopted that
reduces device stresses, despite the fact that CCM uses two

voltage and one current sensors which naturally makes it
costlier. Therefore, a DCM operation of the front end PFC
converter is preferred in PCs where only one voltage sensor
is needed for sensing and control.
II. BLOCK DIAGRAM EXPLANATION

Fig. 2.1: Block Diagram
Fig. 2.1 shows the system block of a PFC Zeta
converter based multi-output SMPS topology. At the input,
a DBR with filter is connected to a nonisolated Zeta
converter. A Zeta PFC converter is still unexplored for the
development of computer SMPSs that are capable of
drawing a purely sinusoidal current with unity PF, offering
low rippled output which is the prime requirement of PCs.
voltage PI controller is used here to regulate the output
voltage. Three different operating modes of the Zeta
converter have been analyzed and compared to select the
best operating mode for a computer power supply
application.

Fig. 3.1:
III. PROPOSED PFC ZETA CONVERTER BASED SMPS
CONFIGURATION
In Fig 3.1shows the system configuration of a PFC Zeta
converter based multi-output SMPS topology. At the input,
a DBR with filter is connected to a no isolated Zeta

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17

PF Corrected Converter Based PQ Fed Multiple Output Switched Mode Power Supply
(IJSRD/Vol. 4/Issue 02/2016/006)

converter. This PFC converter regulates the output dc
voltage and draws a sinusoidal current from the ac mains
at unity PF. Three different DCM conditions (i.e. input
inductor DCM, intermediate capacitor DCM and output
inductor DCM) are considered here to choose the best
operating condition of the front end PFC converter. In the
DCM operation, the current becomes zero either in the input
inductor or output inductor, or the voltage across the
intermediate capacitor becomes zero for some duration in
one switching cycle.
The output dc voltage is regulated using a
Proportional-Integral (PI) voltage controller. The regulated
output dc voltage is connected to an isolated converter for
achieving multiple dc voltages at the output. The isolated
converter consists of two equal valued input
capacitors, two switches, one high frequency transformer
(HFT) and filters. Further, to reduce the component stresses,
the isolated converter is designed in CCM. Another voltage
PI controller is used here to regulate the output voltage.
IV. OPERATING PRINCIPLE OF THE PROPOSED
SYSTEM
The operation of the proposed SMPS is studied to
analyze its behavior in one switching cycle. Three different
conditions (input inductor in DCM, intermediate capacitor
in DCM, output inductor in DCM) have been considered for
the PFC Zeta converter to select the best operating
condition.
IV. DESIGN OF THE PROPOSED PFC ZETA CONVERTER
BASED SMPS
The design of PFC Zeta converter based SMPS is carried
out in this section. The design is based on the change in the
inductor current during the switch on and off period.
The diodes and switches are considered ideal. The switching
frequency considered is high as compared to the
line frequency; so, average magnitudes (of currents and
voltages) within a PWM period are considered for analysis.

If St<Vco, then S=on, else S=off
where, S represents the switching signals for the
PFC converter device. If the output voltage varies, the
control output voltage Vco changes to vary the duty cycle.
Hence, the width of PWM pulses changes accordingly to
maintain the dc output voltage as a constant.
B. Control of Isolated Converter
To control the multiple dc output voltages of the isolated
converter, average current control scheme is used. Only one
winding’s output voltage which is having the highest power
rating is controlled. The other windings’ output voltages are
controlled by the duty cycle of the converter as a common
core is used for all secondary windings. The responses of the
other windings are slow as compared to the output whose
voltage is sensed. For control, output voltage Vdc1 is sensed
and compared with the corresponding reference voltage to
produce voltage error which is the input to the PI controller.
The output of this PI controller is compared with a sawtooth wave to generate the switching pulses for both the
switches S1 and S2. Both the switches are switched on and
off alternately in each half cycle of one PWM period with
sufficient dead time to avoid shoot-through. The width of
the pulses varies according to the voltage error. Thus, the
control of isolated converter is able to take care of the
impact of other output voltage variations (due to load
changes in these outputs) by modifying the duty ratio. If any
winding undergoes a load change, the duty ratio changes
according to the impact felt on the sensed output to maintain
voltage regulation on all the outputs.
V. PERFORMANCE EVALUATION
The performance of the proposed Zeta converter based
SMPS is studied through simulation results to select the best
mode of operation. The design specifications for the power
supply are given in Table II. The power supply is modeled
in MATLAB/Simulink using discrete sampling mode. The
performance of the power supply is analyzed under three
operating conditions of DCM.
Table-2
Design Specifications Of The Zeta Converter Based Smps

Table. 1:Selected Values For The Pfc Converter For The
Power Supply
A. Control of PFC converter
The control of the front end PFC converter generates pulses
according to the output voltage error, which is the voltage
difference between the desired voltage and sensed voltage.
The voltage error signal (Ve) at nth instant is,
Ve(n) = Vdcref(n)-Vdc(n)
Ve is fed to the proportional–integral (PI) controller to
generate a controlled output voltage (Vco).
Vco(n)=Vco(n-1)+kp{Ve(n)-Ve(n-1)}+kiVe(n) where kp
and ki are the proportional and integral gains of the PI
controller.
The output of the PI controller is compared with a high
frequency saw-tooth signal (St) to generate the PWM pulses.

When Lz1 is operating in DCM: shows the
waveforms of vin, iin, iLz1, iLz2, vC1, vS, iS when
the input inductor is operating in DCM. The current through
the output inductor iLz2 and voltage of the intermediate
capacitor VC1 remain in continuous conduction while the
current in input inductor is in DCM. The peak voltage and
current stresses of the PFC switch are observed to be 630V
and 28A respectively in this condition. The input current
THD is 4.11% at full load as shown in Waveforms of PFC
converter when Lz1 is operating in DCM (a) Waveforms of
vin, iin, iLz1, iLz2, VC1, VS, IS at 220V, (b) Input current
and its harmonic spectrum.

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18

PF Corrected Converter Based PQ Fed Multiple Output Switched Mode Power Supply
(IJSRD/Vol. 4/Issue 02/2016/006)

REFERENCES

Fig. 4:

Fig. 5:
VI. CONCLUSION
A DCM operated front end PFC converter cascaded with a
multiple output isolated converter has been used for the
design of an SMPS for PCs. It has been designed, modeled,
simulated and developed for input power quality
improvement and output voltage regulation. All the dc
output voltages are regulated by controlling only one output
voltage. Three different modes of operation of the front end
converter have been carried out in simulation to select the
best possible operation especially based on device stresses.
Finally, the best suited mode of operation for the front end
converter has been implemented in an
experimental
prototype.
Test
results obtained from the prototype
conform to the ones obtained via simulations. From the
recorded test results, it is evident that the proposed power
supply is able to mitigate power quality problems that are
present in the conventional SMPS systems. Based on these
results, it is concluded that the proposed SMPS
configuration in PCs is expected to yield improved THD of
ac mains current with almost unity PF under wide range of
input voltages and loads.

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