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DOI 10.1007/s10836-011-5242-7
Received: 23 December 2010 / Accepted: 8 August 2011 / Published online: 9 September 2011
# Springer Science+Business Media, LLC 2011
Abstract Finite element modeling (FEM) has been undertaken to characterize the effect of copper (Cu) elastoplastic behavior on the induction of stress in 3D
crystalline silicon (Si) systems incorporating Cu throughsilicon vias (TSVs). Using a linear isotropic hardening
model, simulations of thermal annealing cycles in Cu
TSVs indicate that, for sufficient anneal temperatures,
plastic yield within the Cu leads to substantial residual
stress in the neighboring Si following cool-down. Simulated Si stress profiles of annealed isolated TSVs agreed
with experimental Raman microscopy measurements of
post-anneal stress profiles in Si near isolated 525 m
cylindrical TSVs on a 300 mm Si wafer. Simulations were
expanded to investigate the impact of Cu plasticity (yield
stress and tangent modulus) on the residual stress profile
in Si near isolated TSVs and linear TSV arrays. The results
show that the magnitude and extent of the TSV-induced
stress field in Si is a non-monotonic function of Cu yield
stress. Moreover, the tensile or compressive nature of
TSV-induced stress within and outside linear TSV arrays is
also a strong function of the Cu yield stress. The simulated
impact of Cu tangent modulus on TSV-induced stress in Si
is less substantial. The implications of these results for
1 Introduction
The development of 3D interconnection methods for future
generations of integrated circuits is important for meeting
further device scaling demands, as interconnect delay is fast
becoming a performance-limiting factor [6, 8]. In addition,
3D die stacking can significantly improve the areal
efficiency and functionality of future chips [2]. The use of
copper through-silicon vias (Cu TSVs) is a highly promising avenue for 3D integration, but the differences in
thermo-mechanical properties between copper (Cu) and
silicon (Si) can lead to substantial TSV-induced stress
profiles in the surrounding Si. The coupling between these
stress fields and the carrier mobility in Si devices has raised
concerns about the impact of TSVs on the performance of
nearby devices [1, 3, 7, 9, 10, 13, 14]. For comprehensive
electrical analysis of Si-based devices in 3D integrated
circuits it is necessary to take into the account the effects of
local stress in the active regions induced by TSVs.
54
2 Background
2.1 TSV Modeling
Simulations of cylindrical Cu TSV-based systems were
carried out using the Structural Mechanics module of
COMSOL Multiphysics software. The TSV diameter was
5 m and the TSV depth was 25 m. For both isolated Cu
TSVs and linear arrays (12, 14, and 18), quartersymmetric 3D models were used, exploiting the symmetry
in the systems (Fig. 1). In all models the TSVs were
surrounded by anisotropic (crystalline <100>) Si with a
1.0 m SiO2 cap layer. The top of the Cu TSV was flush
with the top surface of the SiO2 cap layer. This geometry
paralleled fabricated samples of isolated TSV structures on
which experimental stress measurements were made. In this
study, the oxide liner (~100 nm thick) and metal barrier
layers (each <10 nm thick) were excluded due to
computational restrictions arising from multi-scale meshing. The extremely thin barrier layers do not seem to have
significant impact on residual stress, as cross sections show
no delamination. However, the impact of the oxide liner
could be significant and will be addressed in future studies.
For modeling of linear arrays the linear TSV pitch was
10 m and the array axis was parallel to the <110>crystal
orientation of the surrounding Si. Figure 2 shows schematics of the models used for the various TSV systems,
with the meshing at the measurement plane, 50 nm beneath
the Si/SiO2 interface. This position was chosen as a balance
between the depth of channels in nearby transistors and the
depth at which the Raman signal is collected from
fabricated samples. The mesh is densest near the edges of
the TSVs, where the stress is expected to change most
rapidly, and it is kept dense along the Raman scan direction
(<110>, along the x-axis) to optimize comparison with
experimental data and minimize mesh-based artifacts in the
simulation. In these dense sections, the mesh elements are
smaller than the spatial resolution of the measurement
equipment (~1 m) so as to investigate the detailed
behavior in the areas over which the Raman tool is
collecting signal.
55
Fig. 2 (color online) Model for Cu TSV systems; (insets) mesh size at measurement plane 50 nm below the Si/SiO2 interface (scale bars are 5 m)
56
Table 1 Material properties used in isolated and linear TSV array simulations
Density (g/cm3)
CTE (ppm/C)
Direction- dependent
2.330
2.3
75
0.17
2.200
0.5
117
0.3
8.960
16.7
Material
Poissons ratio
Silicon (anisotropic)
SiO2 (isotropic)
Direction- dependent
Copper (elasto-plastic)
0.1
Biaxial Approximation
Eigenvalue 1
Eigenvalue 2
Eigenvalue 3
-0.1
0
10
15
20
25
30
Position (m)
57
To investigate the role played by Cu plasticity in TSVinduced residual stress in Si near the device layer for
isolated Cu TSVs and linear arrays of 2, 4, and 8 TSVs,
simulations were run using a matrix of values for the linear
isotropic hardening parameters ys and h. ys was varied
from 50 to 350 MPa in steps of 50 MPa, and h was taken to
be 250, 500, 1,000, and 2,500 MPa. An example of these
simulation results is shown in Fig. 5 for the modeled stress
profile across a 14 TSV array for values of the yield stress,
ys, and tangent modulus, h, of 150 MPa and 250 MPa,
respectively. Exterior to the array the stress profile
qualitatively matches that shown in Fig. 4. Moving away
from the outer TSV, a transition from compressive to tensile
stress is evident, followed by a gradual relaxation. In
contrast, within the linear array the simulation shows
significant Si tensile stress superposition between TSVs.
The maximum Si tensile stress midway between the inner
two TSVs is 74% larger that the corresponding Si tensile
stress extremum outside the array. In concordance with the
simulation data in Fig. 4, the simulated profile in Fig. 5
shows a compressive stress in the Si very close (< 1 m) to
each Cu TSV in the array.
58
Fig. 6 (color online) Impact of varying Cu tangent modulus (h) on tensile stress extrema outside TSVs for simulated stress profiles; for larger
values of ys (>300 MPa for isolated and >200 MPa for arrays), no extrema were seen outside of the TSV arrays
59
Fig. 7 (color online) Impact of varying yield stress (ys) of Cu on extrema in simulated stress profiles (h=500 MPa for all data)
5 Discussion
The simulation results presented above yield important
insights into the behavior and possibly management of TSVinduced stress in Si. First, the non-monotonic behavior of the
60
Fig. 8 (color online) Impact of varying yield stress (ys) on position of simulated stress extremum outside of an isolated TSV and linear TSV
arrays (h=500 MPa for all data)
6 Conclusion
FEM simulations have been presented using anisotropic
Si and treating Cu as an elasto-plastic aggregate with
linear isotropic strain hardening behavior. It has been
shown that these simulations are sufficient to recreate the
measured stress profile in Si surrounding an isolated Cu
TSV. By exploring the impact of the plastic properties of
Cu in the TSVs, it was further shown that the Cu yield
stress in particular can have a large influence on the
residual stress profile of Si near Cu TSVs after thermal
processing. This was the case for simulations of isolated
TSVs and linear TSV arrays containing 2, 4, and
8 elements. Influencing Cu plasticity, potentially through
some form of work hardening, could be beneficial in
minimizing the effects of TSV-induced stresses on
surrounding Si devices and shrinking the keep-out zones
near these TSVs. As additional stresses can be introduced when these TSV-based systems are further processed (thinning, stacking, bonding, etc.), mitigating the
stresses and maximizing the usable space at this stage
would be an important step in making high-performance,
high-density 3D systems a reality.
Acknowledgments B.B. would like to thank Jihan Capulong for
many useful discussions regarding the simulation software and model
development. This work was funded by SEMATECH under Contract
402333-NY.
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Research Initiative Award in 2005, IBM Faculty Awards in 2008 and
2010, and coauthored the Best Paper Award winner from the IEEE
Canadian Conference on Electrical and Computer Engineering
(CCECE) Conference in 2005. He is also an Editor of the Journal of
Computer Science and Technology.
Robert Geer is Professor of Nanoscience and Vice President for
Academic Affairs at the College of Nanoscale Science and
Engineering at the University at Albany, SUNY. His group focuses
on research in nanoelectronics and nanomaterials. He leads the