CMOS, Mixed Signal and Radio Frequency VLSI Design, NMEICT, T210KT-2017

Analog Design: Full Marks-200

Q1. For all circuits in Fig. Q1, assume all transistors to be in saturation.
(a) For the single stage amplifiers given in fig. Q1(a) to (c), find the expression for low frequency small
signal gain (Vout/Vin) using small signal analysis.
[3x5]
(b) For the circuits given in fig. Q1(d) to (f), find the expression for small signal impedance (VX/IX), as
depicted in the circuit diagrams.
Express your answer in terms of MOSFET low frequency small signal parameters. [4x2.5]

(a)

(b)

(d)

(e)

(f)

(g)

(c)

Fig Q1

Q2.

Fig. Q2

In fig. Q2 , RG1||RG2 = 50K, Rs = 10K, CL = 1pF, Iref = 0.1mA. VA1 = VA2 =50V. VDD = 2V. ,
(W/L)1 = 40 , (W/L)2 =20, (W/L)3-6 = 30, L1-6 = 1m , Vtn = |Vtp| = 0.4V .
For M1-6, Cgs = 0.003xW pF and Cgd = 0.001xW pF, Cdb ~0, Csb ~0 (where W is the transistor width in
m), find :
(i)
(ii)
(iii)
(iv)
(v)

Minimum value of Vb applicable for saturation region operation of the amplifier.

Small signal voltage gain from Vin to Vx.
Small signal voltage gain from Vin to Vout.
High frequency poles at Vo, VG1, VD1.
Maximum allowed output voltage swing and hence the allowed input voltage swing for the
case when Vb = 1 V
[5x5]

Q3. For the differential amplifier given in fig. Q3, nCox(W/L)1,2 = 1mA/V2. = 0. Vtn = 0.4V. Is =
0.1mA. RD = 3k.
For Vin1 =0.9V and Vin2 = 1.2V, calculate IDS1 and IDS2. [Hint: assume transistors are in saturation region
of operation]. Also calculate gm1 and gm2. Draw the small signal equivalent circuit. For Vin1 = 0.9+
0.001sin(t) V and Vin2 = Vin1 = 1.2- 0.001sin(t) V, find the expressions for Vout1, Vout2 and Vs. From
the last result, comment about differential mode gain and differential to common mode gain.
[25]

Fig. Q3
Q4. For the differential amplifier in fig. Q4, Kn = Kp = 0.1mA/V2 where Kn,p = n,pCox(W/L).
n= | np| = 0.02 V-1. Vtn= |Vtp| = 0.4V. IS = 0.2mA. VDD = 3V, VSS= 0V. Assume that the devices in the
two branches are well matched.
(i)
(ii)
(iii)

Find the input common mode range. [7.5]

Find the maximum allowed output voltage swing for an applied differential input with
common mode voltage = 1V. [7.5]
For common mode voltage 1V, find the small signal differential input to single ended
output voltage gain and the maximum allowed input voltage swing. [10]

Fig. 4

Q5

Fig. Q5
For the feedback amplifier given in fig. Q5,
Kn,p = n,pCox(W/L) = 4mA/V2. , ID1-4 = 0.2mA, VDD = 2V. R1= 2k, R2 = 3k. There is no DC current
flowing through R2. n= | np| = 0.01 V-1. Vtn= |Vtp| = 0.4V. Cgs = 0.1pF, Cgd = 0.05pF. Csb ~0, Cdb~0.
(i)
(ii)
(iii)
(iv)
(v)
(vi)

Identify the feedback topology. [2.5]

Find the open-loop gain of the amplifier considering the loading effect of the feedback
network on the amplifier. [5]
Find the feedback factor. [2.5]
Find the open loop output impedance of the amplifier. [5]
Using results in (ii), (iii) and (iv), find the closed loop gain and the closed loop output
impedance of the amplifier. [5]
Find the high frequency poles for the loop gain and hence the phase margin. [5]

Q.6 Determine the transistor sizing along with bias conditions for the 2-stage OPAMP shown in the
figure, to achieve the following specifications: [25]
Av >4000V/V. VDD = 2V, VSS = 0, GB = 100MHz, CL = 1pF, slew-rate >10V/s, Vout range = 0.4 to
1.5V , ICMR = 0.5 to 1.4V, phase margin = 60o. Assumer CL and Cc to be much larger than MOS
parasitic capacitances.

Fig. Q6

Fig. Q7
Q.7 For the common-mode feedback scheme depicted in fig. Q7, find the expression for open loop gain
for the feedback loop in terms of transistor small-signal parameters. Identify the dominant poles and find
the expression for phase margin. [12.5 x 2 ]

Fig. Q8
Q.8
(a) For the differential pair shown in fig. 7, find the expression for input referred noise-voltage in terms
of small signal device parameters. Based on the noise expression, determine the sizing strategy for
minimizing the input referred noise of the circuit. Find the expression for 1/f noise corner frequency.
[12.5]
(b) How does the expression for input referred noise change for (i) diode connected load and (ii) currentsource load (fully differential).
[12.5]