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  • Clock - Domain - Crossing, Verilog Blocking Vs Non Blocking & FSM in Verilog

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    Clock_domain_crossing,Verilog Blocking vs Non Blocking & FSM in Verilog

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    14 views4 pages

    Clock - Domain - Crossing, Verilog Blocking Vs Non Blocking & FSM in Verilog

    Uploaded by

    VIKRAM
    cook ogf the function

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    12/28/2016

    clock_domain_crossing,verilogblockingvsnonblocking&FSMinVerilog

    ClockDomainCrossing...
    Thefollowingsectionexplainsclockdomaininterfacing
    Oneofthebiggestchallengesofsystemonchip(SOC)designsisthatdifferentblocksoperateon
    independentclocks.Integratingtheseblocksviatheprocessorbus,memoryports,peripheralbusses,and
    otherinterfacescanbetroublesomebecauseunpredictablebehaviorcanresultwhentheasynchronous
    interfacesarenotproperlysynchronized
    Averycommonandrobustmethodforsynchronizingmultipledatasignalsisahandshaketechniqueas
    shownindiagrambelowThisispopularbecausethehandshaketechniquecaneasilymanagechangesin
    clockfrequencies,whileminimizinglatencyatthecrossing.However,handshakelogicissignificantlymore
    complexthanstandardsynchronizationstructures.

    FSM1(Transmitter)assertsthereq(request)signal,askingthereceivertoacceptthedataonthedatabus.
    FSM2(Receiver)generallyaslowmoduleassertstheack(acknowledge)signal,signifyingthatithas
    acceptedthedata.
    ithasloopholes:whensystemReceiversamplesthesystemsTransmitterreqlineandTransmittersamples
    systemReceiverackline,theyhavedoneitwithrespecttotheirinternalclock,sotherewillbesetupand
    holdtimeviolation.Toavoidthiswegofordoubleortriplestagesynchronizers,whichincreasetheMTBF
    andthusareimmunetometastabilitytoagoodextent.Thefigurebelowshowshowthisisdone.

    http://www.asic.co.in/Index_files/digital_files/clock_domain_crossin.htm

    1/4

    12/28/2016

    clock_domain_crossing,verilogblockingvsnonblocking&FSMinVerilog

    BlockingvsNonBlocking...
    selftriggeringblocks
    moduleosc2(clk)
    outputclk
    regclk
    initial#10clk=0
    always@(clk)#10clk<=~clk
    endmodule
    Afterthefirst@(clk)trigger,theRHSexpressionofthenonblockingassignmentisevaluatedandtheLHS
    valuescheduledintothenonblockingassignupdateseventqueue.
    Beforethenonblockingassignupdateseventqueueis"activated,"the@(clk)triggerstatementis
    encounteredandthealwaysblockagainbecomessensitivetochangesontheclksignal.Whenthe
    nonblockingLHSvalueisupdatedlaterinthesametimestep,the@(clk)isagaintriggered.
    moduleosc1(clk)
    outputclk
    regclk
    initial#10clk=0
    always@(clk)#10clk=~clk
    endmodule
    BlockingassignmentsevaluatetheirRHSexpressionandupdatetheirLHSvaluewithoutinterruption.The
    blockingassignmentmustcompletebeforethe@(clk)edgetriggereventcanbescheduled.Bythetimethe
    triggereventhasbeenscheduled,theblockingclkassignmenthascompletedtherefore,thereisnotrigger
    eventfromwithinthealwaysblocktotriggerthe@(clk)trigger.
    Badmodeling:(usingblockingforseq.logic)
    always@(posedgeclk)begin
    http://www.asic.co.in/Index_files/digital_files/clock_domain_crossin.htm

    2/4

    12/28/2016

    clock_domain_crossing,verilogblockingvsnonblocking&FSMinVerilog

    q1=d
    q2=q1
    q3=q2

    end

    RaceCondition

    always@(posedgeclk)q1=d
    always@(posedgeclk)q2=q1
    always@(posedgeclk)q3=q2

    always@(posedgeclk)q2=q1
    always@(posedgeclk)q3=q2
    always@(posedgeclk)q1=d

    always@(posedgeclk)begin

    q3=q2

    q2=q1
    q1=d
    end

    Badstylebutstillworks

    Goodmodeling:

    Power
    MOSFETs
    Rich product
    lineup of
    MOSFETs
    Oered by
    ROHM
    Semiconductor.

    always@(posedgeclk)begin

    q1<=d

    q2<=q1
    q3<=q2

    end

    always@(posedgeclk)begin

    q3<=q2

    q2<=q1
    q1<=d

    end

    NomatterofsequenceforNonblocking

    always@(posedgeclk)q1<=d

    always@(posedgeclk)q2<=q1
    always@(posedgeclk)q3<=q2

    always@(posedgeclk)q2<=q1
    always@(posedgeclk)q3<=q2
    always@(posedgeclk)q1<=d

    GoodCombinationallogic:(Blocking)

    always@(aorborcord)begin

    tmp1=a&b

    tmp2=c&d

    y=tmp1|tmp2

    end

    BadCombinationallogic:(Nonblocking)

    always@(aorborcord)beginwillsimulateincorrectly

    tmp1<=a&bneedtmp1,tmp2insensitivity
    http://www.asic.co.in/Index_files/digital_files/clock_domain_crossin.htm

    3/4

    12/28/2016

    clock_domain_crossing,verilogblockingvsnonblocking&FSMinVerilog

    tmp1<=a&bneedtmp1,tmp2insensitivity

    tmp2<=c&d

    y<=tmp1|tmp2

    end

    Mixeddesign:

    UseNonblockingassignment.

    Incaseonmultiplenonblockingassignmentslastonewillwin.

    rohm.com

    VerilogFSM

    Home

    Power
    MOSFETs
    Rich product
    lineup of
    MOSFETs
    Oered by
    ROHM
    Semiconductor.
    http://www.asic.co.in/Index_files/digital_files/clock_domain_crossin.htm

    4/4

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