2.3.

1 Rangkaian Kombinasi
2.3.1.1 Tabel Kebenaran Rangkaian Kombinasi
Tabel 2.1 Rangkaian Kombinasi
Input
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Outpu
t
Y
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1

2.3.1.2 Gambar Rangkaian

Gambar 2.3 Rangkaian Kombinasi 3 Gerbang Logika

2.3.1.3 Listing Program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BabIIkombinasi is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Y : out STD_LOGIC);
end BabIIkombinasi;
architecture Behavioral of BabIIkombinasi is
begin
Y <= ( A and B ) or ( C nand D );
end Behavioral;

2.3.1.4 Timing Diagram

Gambar 2.4 Timing Diagram Rangkaian Kombinasi

2.3.1.5 File Report

BabIIkombinasi Project Status (10/21/2015 - 21:46:00)

Project File:

BABIIkombinasi.xis
Parser Errors:
e

No Errors

Module
Name:

BabIIkombinasi

Implementation State:

Programming
File Generated

Target
Device:

xc3s500e-4fg320

Errors:

No Errors

Product
Version:

ISE 13.2

Warnings:

No Warnings

Design Goal: Balanced

Routing Results:

All Signals
Completely
Routed

Design
Strategy:

Timing
Constraints:

Xilinx Default
(unlocked)

Environment
System Settings
:

Final Timing
Score:

0 (Timing
Report)

Device Utilization Summary

Logic Utilization

[-]

Use Availabl Utilizatio

Note(s)
d
e
n

Number of 4 input LUTs

9,312

1%

Number of occupied Slices

4,656

1%

Number of Slices containing only

related logic

100%

Number of Slices containing

unrelated logic

0%

Total Number of 4 input LUTs

9,312

1%

Number of bonded IOBs

232

2%

Average Fanout of Non-Clock Nets

1.00

Performance Summary

[-]

Final Timing
Score:

0 (Setup: 0, Hold: 0)

Pinout
Data:

Pinout Report

Routing Results:

All Signals Completely

Routed

Clock
Data:

Clock Report

Timing
Constraints:
Detailed Reports

[-]

Report Name

Status Generated

Error Warning
Infos
s
s

Synthesis Report

Curren Thu Oct 22

t
10:38:17 2015

Translation Report

Curren Thu Oct 22

t
10:38:26 2015

Map Report

Curren Thu Nov 26

t
13:52:20 2015

2 Infos (0
new)

Place and Route

Report

Curren Thu Nov 26

t
13:52:33 2015

1 Info (0 new)

Post-PAR Static
Timing Report

Curren Thu Nov 26

t
13:52:39 2015

5 Infos (0
new)

Bitgen Report

Curren Thu Nov 26

t
13:52:53 2015

Power Report

Secondary Reports
Report Name

Status

Generated

ISIM Simulator Log

Current

Thu Nov 26 14:00:10 2015

WebTalk Report

Current

Thu Nov 26 13:52:54 2015

WebTalk Log File

Current

Thu Nov 26 13:52:55 2015

[-]

Date Generated: 11/26/2015 - 14:05:33

2.3.2 Multiplekser
2.3.2.1 Tabel Kebenaran Multiplekser
Tabel 2.2 Tabel Kebenaran Multiplekser
Input
S0
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

A
0
1
0
0
0
0
0
0

2.3.2.2 Gambar Rangkaian

B
0
0
0
1
0
0
0
0

C
0
0
0
0
0
1
0
0

D
0
0
0
0
0
0
0
1

Output
Y
0
1
0
1
0
1
0
1

Gambar 2.5 Rangkaian Multiplexer

2.3.2.3 Listing Program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplekser is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end multiplekser;
architecture Behavioral of multiplekser is

begin
Y <= ( A and B ( not S0) and ( not S1) ) or ( B and s1 and ( not S0 )) or ( C and S0
and ( not S1)) or ( D and S0 and S1 );
end Behavioral;

2.3.2.4 Timing Diagram

Gambar 2.6 Timing Diagram Multiplexer

2.3.2.5 File Report

multiplekser Project Status (10/24/2015 - 13:57:42)
Project File:

babmultiplekserII.xis
Parser Errors:
e

No Errors

Module
Name:

Multiplekser

Implementation State:

Placed and
Routed

Target
Device:

xc3s500e-4fg320

Errors:

No Errors

Product
Version:

ISE 13.2

Warnings:

No Warnings

Routing Results:

All Signals
Completely
Routed

Design Goal: Balanced

Design
Strategy:

Timing
Constraints:

Xilinx Default
(unlocked)

Environment: System Settings

Final Timing
Score:

0 (Timing
Report)

Device Utilization Summary

[-]

Use Availabl Utilizatio

Note(s)
d
e
n

Logic Utilization
Number of 4 input LUTs

9,312

1%

Number of occupied Slices

4,656

1%

Number of Slices containing only

related logic

100%

Number of Slices containing

unrelated logic

0%

Total Number of 4 input LUTs

9,312

1%

Number of bonded IOBs

232

3%

Average Fanout of Non-Clock Nets

1.14

Performance Summary

[-]

Final Timing
Score:

0 (Setup: 0, Hold: 0)

Pinout
Data:

Pinout Report

Routing Results:

All Signals Completely

Routed

Clock
Data:

Clock Report

Timing
Constraints:
Detailed Reports

[-]

Report Name

Status

Generated

Error Warning
Infos
s
s

Synthesis Report

Current

Sat Oct 24
16:15:30 2015

Translation Report Current

Sat Oct 24
16:16:27 2015

Map Report

Current

Sat Oct 24
16:16:33 2015

2 Infos (0
new)

Place and Route

Current

Sat Oct 24

1 Info (0 new)

Report

16:16:47 2015

Power Report
Post-PAR Static
Timing Report

Current

Sat Oct 24
16:16:53 2015

5 Infos (0
new)

Bitgen Report

Out of
Date

Sat Oct 24
13:57:40 2015

Secondary Reports

[-]

Report Name

Status

Generated

ISIM Simulator Log

Current

Fri Nov 20 15:42:04 2015

WebTalk Report

Out of Date

Sat Oct 24 13:57:40 2015

WebTalk Log File

Out of Date

Sat Oct 24 13:57:42 2015

Date Generated: 11/26/2015 - 14:06:27

2.3.3 Demultiplekser
2.3.3.1 Tabel Kebenaran Demultiplexer
Tabel 2.3 Tabel Kebenaran Demultiplexer

S0
0
0
0
0
1
1
1
1

Input
S1
0
0
1
1
0
0
1
1

Output
Z
0
1
0
1
0
1
0
1

2.3.3.2 Gambar Rangkaian

A
0
1
0
0
0
0
0
0

B
0
0
0
1
0
0
0
0

C
0
0
0
0
0
1
0
0

D
0
0
0
0
0
0
0
1

Gambar 2.7 Rangkaian Demultiplexer

2.3.3.3 Listing Diagram
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demultiplexer is
Port ( S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Z : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC;
C : out STD_LOGIC;
D : out STD_LOGIC);
end demultiplexer;
architecture Behavioral of demultiplexer is

begin
A <= Z and ( not S0 ) and ( not S1 );
B <= Z and S1 and ( not S0 );
C <= Z and S) and ( not S1 );
D <= Z and S0 and S1;
end Behavioral;

2.3.3.4 Timing Diagram

Gambar 2.8 Timing Diagram Demultiplexer

2.3.3.5 File Report

DemultiplexerBABII Project Status (10/24/2015 - 14:39:29)
Project File:

DemultiplexerBABII.xis
Parser Errors:
e

No Errors

Module
Name:

DemultiplexerBABII

Implementation State:

Placed and
Routed

Target
Device:

xc3s500e-4fg320

Errors:

No Errors

Product
Version:

ISE 13.2

Warnings:

No Warnings

Design Goal: Balanced

All Signals
Routing Results: Completely
Routed

Design
Strategy:

Timing
Constraints:

Xilinx Default
(unlocked)

Environment System Settings

:

Final Timing

0 (Timing
Report)

Score:

Device Utilization Summary

[-]

Use Availabl Utilizatio

Note(s)
d
e
n

Logic Utilization
Number of 4 input LUTs

9,312

1%

Number of occupied Slices

4,656

1%

Number of Slices containing only

related logic

100%

Number of Slices containing

unrelated logic

0%

Total Number of 4 input LUTs

9,312

1%

Number of bonded IOBs

232

3%

Average Fanout of Non-Clock Nets

2.29

Performance Summary

[-]

Final Timing
Score:

0 (Setup: 0, Hold: 0)

Pinout
Data:

Pinout Report

Routing Results:

All Signals Completely

Routed

Clock
Data:

Clock Report

Timing
Constraints:
Detailed Reports

[-]

Report Name

Status Generated

Error Warning
Infos
s
s

Synthesis Report

Curren Sat Oct 24

t
16:11:09 2015

Translation Report

Curren Sat Oct 24

t
16:11:39 2015

Map Report

Curren Sat Oct 24

t
16:11:45 2015

2 Infos (0
new)

Place and Route

Report

Curren Sat Oct 24

t
16:12:02 2015

1 Info (0 new)

Curren Sat Oct 24

t
16:12:07 2015

5 Infos (0
new)

Power Report
Post-PAR Static
Timing Report
Bitgen Report
Secondary Reports

[-]

Report Name

Status

Generated

ISIM Simulator Log

Current

Fri Nov 20 16:03:47 2015

Date Generated: 11/26/2015 - 14:07:05

2.3.4.Dekoder 3 to 8
2.3.4.1 Tabel Kebenaran Dekoder 3 to 8
Tabel 2.4 Tabel Kebenaran Dekoder 3 to 8
Input
A

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

Q
0
1
0
0
0
0
0
0

Q1
0
1
0
0
0
0
0

Q
2
0
0
1
0
0
0
0

Output
Q
Q
3
4
0
0
0
0
0
0
1
0
0
1
0
0
0
0

Q5

Q6

Q7

0
0
0
0
0
1
0

0
0
0
0
0
0
1

0
0
0
0
0
0
0

2.3.4.2 Gambar Rangkaian

Gambar 2.9 Rangkaian Dekoder 3 to 8

2.3.4.3 Listing Program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dekoder3to8 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;

Q3 : out STD_LOGIC;
Q4 : out STD_LOGIC;
Q5 : out STD_LOGIC;
Q6 : out STD_LOGIC;
Q7 : out STD_LOGIC);
end dekoder3to8;
architecture Behavioral of dekoder3to8 is
begin
Q0 <= ( not A ) and ( not B ) and ( not C );
Q1 <= ( not A ) and ( not B ) and C ;
Q2 <= ( not A ) and B and ( not C );
Q3 <= ( not A ) and B and C;
Q4 <= A and ( not B ) and ( not C );
Q5 <= A and ( not B ) and C;
Q6 <= A and B and 9 not C );
Q7 <= A and B and C;
end Behavioral;

2.3.4.4 Timing Diagram

Gambar 2.10 Timing Diagram Dekoder 3 to 8

2.3.4.5 File Report

Dekoder3to8 Project Status
Project File:

Dekoder3to8.xise

Parser Errors:

No Errors

Module
Name:

Dekoder3to8

Implementation State:

Placed and
Routed

Target
Device:

xc3s500e-4fg320

Errors:

No Errors

Product
Version:

ISE 13.2

Warnings:

No Warnings

Design Goal:

Balanced

Routing Results:

All Signals
Completely
Routed

Design
Strategy:

Xilinx Default
(unlocked)

Timing
Constraints:

Environment: System Settings

Final Timing

0 (Timing
Report)

Score:

Device Utilization Summary

[-]

Use Availabl Utilizatio

Note(s)
d
e
n

Logic Utilization
Number of 4 input LUTs

9,312

1%

Number of occupied Slices

4,656

1%

Number of Slices containing only

related logic

100%

Number of Slices containing

unrelated logic

0%

Total Number of 4 input LUTs

9,312

1%

11

232

4%

Number of bonded IOBs

Average Fanout of Non-Clock Nets

2.91

Performance Summary

[-]

Final Timing
Score:

0 (Setup: 0, Hold: 0)

Pinout
Data:

Pinout Report

Routing Results:

All Signals Completely

Routed

Clock
Data:

Clock Report

Timing
Constraints:
Detailed Reports

[-]

Report Name

Status Generated

Error Warning
Infos
s
s

Synthesis Report

Curren Sat Oct 24

t
15:22:21 2015

Translation Report

Curren Sat Oct 24

t
15:22:29 2015

Map Report

Curren Sat Oct 24

t
15:22:35 2015

2 Infos (2
new)

Place and Route

Report

Curren Sat Oct 24

t
15:22:48 2015

1 Info (1 new)

Curren Sat Oct 24

t
15:22:53 2015

5 Infos (5
new)

Power Report
Post-PAR Static
Timing Report
Bitgen Report
Secondary Reports
Report Name

Status

Generated

ISIM Simulator Log

Current

Fri Nov 20 16:03:31 2015

Date Generated: 11/26/2015 - 14:07:51

[-]