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PDIP14
N SUFFIX
CASE 646
14
1
Features
SOIC14
D SUFFIX
CASE 751A
14
1
TSSOP14
DTB SUFFIX
CASE 948G
14
PIN CONNECTIONS
Out 1
14
13
Inputs 1
3
VCC
*
)
4
5
Inputs 2
6
Out 2
*
1
)
Inputs 4
12
11
)
2
*
)
*
Out 4
VEE, GND
10
Inputs 3
9
8
Out 3
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Symbol
Value
VCC
VCC, VEE
32
16
VIDR
32
Vdc
VICR
0.3 to 32
Vdc
tSC
Continuous
Unit
Vdc
TJ
150
RJA
118
156
190
C/W
Tstg
65 to +150
Vesd
Case 646
Case 751A
Case 948G
V
2000
200
TA
C
25 to +85
0 to +70
40 to +105
40 to +125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Split Power Supplies.
2. For supply voltages less than 32 V, the absolute maximum input voltage is equal to the supply voltage.
3. All RJA measurements made on evaluation board with 1 oz. copper traces of minimum pad size. All device outputs were active.
4. NCV2902 is qualified for automitive use.
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2
Symbol
VIO
Min
Typ
LM324A
Max
Min
Typ
LM324
Max
Min
Typ
LM2902
Max
Min
Typ
LM2902V/NCV2902
Max
Min
Typ
Max
Unit
mV
TA = 25C
2.0
5.0
2.0
3.0
2.0
7.0
2.0
7.0
2.0
7.0
TA = Thigh (Note 5)
7.0
5.0
9.0
10
13
TA = Tlow (Note 5)
7.0
5.0
9.0
10
10
VIO/T
7.0
7.0
30
7.0
7.0
7.0
V/C
IIO
3.0
30
100
5.0
30
75
5.0
50
150
5.0
50
200
5.0
50
200
nA
Average Temperature
Coefficient of Input
Offset Current
IIO/T
10
10
300
10
10
10
pA/C
IIB
90
150
300
45
100
200
90
250
500
90
250
500
90
250
500
nA
Average Temperature
Coefficient of Input
Offset Voltage
TA = Thigh to Tlow
(Notes 5 and 7)
TA = Thigh to Tlow
(Notes 5 and 7)
Input Bias Current
TA = Thigh to Tlow
(Note 5)
Input Common Mode
Voltage Range
(Note 6)
VICR
VCC = 30 V
TA = +25C
28.3
28.3
28.3
24.3
24.3
TA = Thigh to Tlow
(Note 5)
28
28
28
24
24
VCC
VCC
VCC
VCC
VCC
Differential Input
Voltage Range
VIDR
AVOL
V
V/mV
RL = 2.0 k,
VCC = 15 V,
for Large VO Swing
50
100
25
100
25
100
25
100
25
100
TA = Thigh to Tlow
(Note 5)
25
15
15
15
15
CS
120
120
120
120
120
dB
Common Mode
Rejection,
RS 10 k
CMR
70
85
65
70
65
70
50
70
50
70
dB
Power Supply
Rejection
PSR
65
100
65
100
65
100
50
100
50
100
dB
Channel Separation
10 kHz f 20 kHz,
Input Referenced
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3
Symbol
Min
Typ
LM324A
Max
Min
Typ
LM324
Max
Min
Typ
LM2902
Max
Min
Typ
LM2902V/NCV2902
Max
Min
Typ
Max
VOH
VCC = 5.0 V, RL =
2.0 k, TA = 25C
3.3
3.5
3.3
3.5
3.3
3.5
3.3
3.5
3.3
3.5
VCC = 30 V
RL = 2.0 k
26
26
26
22
22
VCC = 30 V
RL = 10 k
27
28
27
28
27
28
23
24
23
24
5.0
20
5.0
20
5.0
20
5.0
100
5.0
100
Output Voltage
Low Limit,
VCC = 5.0 V,
RL = 10 k,
TA = Thigh to Tlow
(Note 8)
VOL
IO +
Unit
mV
mA
TA = 25C
20
40
20
40
20
40
20
40
20
40
TA = Thigh to Tlow
(Note 8)
10
20
10
20
10
20
10
20
10
20
10
20
10
20
10
20
10
20
10
20
TA = Thigh to Tlow
(Note 8)
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
(VID = 1.0 V,
VO = 200 mV,
TA = 25C)
12
50
12
50
12
50
A
40
60
40
60
40
60
40
60
40
60
mA
IO
ISC
ICC
mA
mA
VCC = 30 V
VO = 0 V, RL =
3.0
1.4
3.0
3.0
3.0
3.0
VCC = 5.0 V,
VO = 0 V, RL =
1.2
0.7
1.2
1.2
1.2
1.2
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4
Output
Bias Circuitry
Common to Four
Amplifiers
VCC
Q15
Q16
Q22
Q14
Q13
40 k
Q19
5.0 pF
Q12
Q24
25
Q23
+
Q20
Q18
Inputs
Q11
Q9
Q21
Q17
Q6
Q2
Q25
Q7
Q5
Q1
Q8
Q3
Q4
2.4 k
Q10
Q26
2.0 k
VEE/GND
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5
1.0 V/DIV
VCC = 15 Vdc
RL = 2.0 k
TA = 25C
5.0 s/DIV
VCC
1.5 V to VCC(max)
1.5 V to VEE(max)
4
VEE
Single Supply
Split Supplies
VEE/GND
Figure 3.
70
70
Phase Margin
60
50
50
40
40
30
30
Gain Margin
20
20
10
0
10
1.0
10
100
1000
LOAD CAPACITANCE (pF)
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6
0
10000
PHASE MARGIN ()
60
120
A VOL, LARGESIGNAL
OPEN LOOP VOLTAGE GAIN (dB)
18
16
14
12
10
Negative
8.0
Positive
6.0
4.0
2.0
0
80
60
40
20
0
20
2.0
4.0
6.0
8.0
10
12
14
16
18
20
1.0
10
100
1.0 k
10 k
1.0 M
100 k
f, FREQUENCY (Hz)
14
550
RL = 2.0 k
VCC = 15 V
VEE = GND
Gain = 100
RI = 1.0 k
RF = 100 k
12
10
8.0
VCC = 15 V
VEE = GND
TA = 25C
100
6.0
4.0
2.0
500
Input
450
Output
400
350
300
250
VCC = 30 V
VEE = GND
TA = 25C
CL = 50 pF
200
0
1.0
10
100
f, FREQUENCY (kHz)
1000
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
t, TIME (s)
TA = 25C
RL = R
2.1
2.4
1.8
1.5
1.2
0.9
0.6
0.3
0
5.0
10
15
20
25
VCC, POWER SUPPLY VOLTAGE (V)
30
90
80
70
35
2.0
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7
18
20
VCC
R2
10 k
1/4
MC1403
2.5 V
Vref =
a R1
Hysteresis
1/4
LM324
+
eo
VO
Vref
Vin
LM324
1/4
1
CR
1/4
VinH =
VinL
100 k
C
C
R
1/4
LM324
+
100 k
1/4
1/4
LM324
+
Vref
Bandpass
Output
R3
Vref
R1
Vref =
1
V
2 CC
C1 = 10C
For:fo=1.0 kHz
For:Q= 10
For:TBP= 1
For:TN= 1
Notch Output
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R1 = QR
R1
R2 =
TBP
C1
1/4
LM324
+
Vref
1
fo =2 RC
R3 = TN R2
LM324
+
Vref
Vref
VinH
R1
(VOH VOL)
R1 + R2
R2
VOL
R1
(VOH Vref) + Vref
R1 + R2
H=
eo = C (1 + a + b) (e2 e1)
R2
VO
R1
(V V ) + Vref
VinL =
R1 + R2 OL ref
LM324
+
C1
VOH
Vin
R1
b R1
e2
R1
R2
LM324
R1
1
fo = 2 RC
R2
1
CR
1/4
VO
1
V
2 CC
VCC
1/4
LM324
+
VO
LM324
+
VO = 2.5 V 1 +
e1
Vref
R
C
R1
R2
R3
= 160 k
= 0.001 F
= 1.6 M
= 1.6 M
= 1.6 M
1
V
2 CC
Triangle Wave
Output
+
R2
300 k
R3
1/4
LM324
VCC
+
1/4
75 k
LM324
R1
100 k
Vref
C
Square
Wave
Output
R1
R1 + RC
4 CRf R1
Vin
Vref
R2 R1
R2 + R1
VO
LM324
+
R2
if R3 =
CO
1/4
Rf
f =
R3
CO = 10 C
1
Vref = 2 VCC
Given:fo=center frequency
A(fo)=gain at center frequency
Choose value fo, C
Then:
R3 =
Q
fo C
R1 =
R3
2 A(fo)
R2 =
R1 R3
4Q2 R1 R3
Qo fo
BW
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9
< 0.1
Package
LM224D
SOIC14
LM224DG
SOIC14
(PbFree)
LM224DR2
SOIC14
LM224DR2G
SOIC14
(PbFree)
LM224DTB
25C to +85C
TSSOP14*
LM224DTBG
TSSOP14*
LM224DTBR2
TSSOP14*
LM224DTBR2G
TSSOP14*
LM224N
PDIP14
LM224NG
PDIP14
(PbFree)
LM324D
SOIC14
LM324DG
SOIC14
(PbFree)
LM324DR2
SOIC14
LM324DR2G
SOIC14
(PbFree)
LM324DTB
TSSOP14*
LM324DTBG
TSSOP14*
LM324DTBR2
TSSOP14*
LM324DTBR2G
TSSOP14*
LM324N
PDIP14
LM324NG
PDIP14
(PbFree)
LM324AD
0C to +70C
Shipping
55 Units/Rail
96 Units/Tube
25 Units/Rail
55 Units/Rail
96 Units/Tube
25 Units/Rail
SOIC14
LM324ADG
SOIC14
(PbFree)
LM324ADR2
SOIC14
LM324ADR2G
SOIC14
(PbFree)
LM324ADTB
TSSOP14*
LM324ADTBG
TSSOP14*
LM324ADTBR2
TSSOP14*
LM324ADTBR2G
TSSOP14*
LM324AN
PDIP14
LM324ANG
PDIP14
(PbFree)
55 Units/Rail
96 Units/Tube
25 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
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10
Package
LM2902D
SOIC14
LM2902DG
SOIC14
(PbFree)
LM2902DR2
SOIC14
LM2902DR2G
SOIC14
(PbFree)
LM2902DTB
40C to +105C
TSSOP14*
LM2902DTBG
TSSOP14*
LM2902DTBR2
TSSOP14*
LM2902DTBR2G
TSSOP14*
LM2902N
PDIP14
LM2902NG
PDIP14
(PbFree)
LM2902VD
SOIC14
LM2902VDG
SOIC14
(PbFree)
LM2902VDR2
SOIC14
LM2902VDR2G
SOIC14
(PbFree)
LM2902VDTB
TSSOP14*
LM2902VDTBG
TSSOP14*
LM2902VDTBR2
40C to +125C
LM2902VDTBR2G
TSSOP14*
TSSOP14*
LM2902VN
PDIP14
LM2902VNG
PDIP14
(PbFree)
NCV2902DR2
SOIC14
NCV2902DR2G
SOIC14
(PbFree)
NCV2902DTBR2G
Shipping
55 Units/Rail
96 Units/Tube
25 Units/Rail
55 Units/Rail
96 Units/Tube
25 Units/Rail
TSSOP14*
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
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11
14
LM324AN
AWLYYWWG
14
LMx24N
AWLYYWWG
14
LM2902N
AWLYYWWG
LM2902VN
AWLYYWWG
SOIC14
D SUFFIX
CASE 751A
14
14
LM324ADG
AWLYWW
14
14
LMx24DG
AWLYWW
LM2902DG
AWLYWW
LM2902VDG
AWLYWW
TSSOP14
DTB SUFFIX
CASE 948G
14
14
14
14
x24
324A
2902
ALYWG
G
ALYWG
G
ALYWG
G
1
2902
V
ALYWG
G
1
x
= 2 or 3
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= PbFree Package
(Note: Microdot may be in either location)
*This marking diagram also applies to NCV2902.
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12
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
F
T
SEATING
PLANE
D 14 PL
0.13 (0.005)
M
M
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13
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
10 _
0.38
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
A
14
P 7 PL
0.25 (0.010)
T
D 14 PL
0.25 (0.010)
T B
DIM
A
B
C
D
F
G
J
K
M
P
R
K
M
R X 45 _
SEATING
PLANE
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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14
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
N
2X
14
L/2
0.25 (0.010)
M
B
U
L
PIN 1
IDENT.
N
F
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
DETAIL E
K
A
V
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION NN
W
C
0.10 (0.004)
T SEATING
PLANE
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
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15
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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16
LM324/D