MINI2440启动代码的编写

Mini2440 ------
Mini2440
ARM
MINI2440 MINI2440
S3C2440 NOR FLASH NAND FLASH FLASH

NOR FLASH nGCS0 NOR FLASH nGCS0
0x00000000 NAND FLASH S3C2440 4K BootSRAM nGCS0
0x00000000 0
0
NOR FLASH RAM
NOR FLASH NOR FLASH NAND FLASH
NAND FLASH
S3C2440 SRAM 4KBSteppingstone
NAND FLASH S3C2440 NAND FLASH 4K Steppingstone
4K SRAM nGCS0 0x00000000
NAND FLASH NAND FLASH 4K
NAND FLASH SDRAM
NAND FLASH SDRAM
Mini2440 FLASH 2M Nor FLASH 128M Nand FLASH
NAND FLASH NOR
FLASH NOR FLASH S2
S3C2440
ARM

1
fengwei@jiangnan.edu.cn QQ:184930560
Mini2440 ------
1.
ARM PC
ARM 7
IRQ IRQ
FIQ FIQ 7
8*4 4
PC
1
1
0x00
Reset
0x04
HandlerUndef
0x08
HandlerSWI
0x0c
HandlerPabort
0x10
HandlerDabort
0x14
0x18
HandlerIRQ
IRQ
0x1c
HandlerFIQ
FIQ
CODE32
AREA
// ARM
startup,CODE,READONLY //AREA startup CODE

//READONLY -
ENTRY
B ResetInit
B HandlerUndef
//
//
//
2
Mini2440 ------
B
B
B
B
B
B
HandlerSWI
HandlerPabort
HandlerDabort
.
HandlerIRQ
HandlerFIQ
//
//
//
//
//
//
ARM 0 PC 0
ResetInit
ARM PC
2 5
1.1
ARM
CPU CPSR R14

SPSR CPSR PC 0x00000004
HandlerUndef
B
HandlerUndef
1.2
ARM 7
CPSR CPSR
CPSR
SWI SWI SWI
3
Mini2440 ------
SWI SWI CPSR

SWI R14 SPSR CPSR IRQ PC
0x00000008
IRQFIQ
IRQ FIQ
IRQ FIQ SWI
(1)
int Main(void)
{
//
IRQEnable(); // IRQ
//
}
2
2
// / IRQFIQ
__swi(0x00) void SwiHandle1(int Handle);
#define IRQDisable()
SwiHandle1(0)
#define IRQEnable()
SwiHandle1(1)
#define FIQDisable()
SwiHandle1(2)
#define FIQEnable()
SwiHandle1(3)
3
3
HandlerSWI
CMP
R0,#4
//R0 44
LDRLO PC,[PC,R0,LSL #2]

// 4 SwiFunction
MOVS PC,LR
// 4
SwiFunction
DCD
DCD
DCD
DCD
IRQDisable
MRS
ORR
MSR
IRQDisable
IRQEnable
FIQDisable
FIQEnable
//
// 0
// 1
// 2
// 3
// IRQ
R0,CPSR
R0,R0,#IRQMSK
SPSR_c,R0
4
Mini2440 ------
MOVS
IRQEnable
MRS
BIC
MSR
MOVS
FIQDisable
MRS
ORR
MSR
MOVS
FIQEnable
MRS
BIC
MSR
MOVS
PC,LR
// IRQ
R0,CPSR
R0,R0,#IRQMSK
SPSR_c,R0
PC,LR
// FIQ
R0,CPSR
R0,R0,#FIQMSK
SPSR_c,R0
PC,LR
// FIQ
R0,CPSR
R0,R0,#FIQMSK
SPSR_c,R0
PC,LR
2 __swi ADS
__swi() ()
24

ATPCS 4 R0~R3
4
2__swi(0x00) void SwiHandle1(int Handle) 0x00
SwiHandle1 R0
4 IRQ IRQ FIQ

IFQ 1
IRQEnable( );
3PC 0x00000008
HandlerSWIHandlerSWI
R0 R0 4 4
SwiFunctionSwiFunction
R0 1 IRQEnable IRQ
5
Mini2440 ------
1.3
ARM9 5 5 /
PC-4+4 CPSR
R14 SPSR CPSR PC
0x0000000C
MMU
HandlerPabort
B
HandlerPabort
1.4
ARM Thumb
CPSR R14
SPSR CPSR PC 0x00000010
MMU
HandlerDabort
B
HandlerDabort
1.5 IRQ
ARM CPU
CPSR I
IRQ IRQ ARM IRQ R14 CPSR
6
Mini2440 ------
IRQ SPSR CPSR IRQ IRQ

PC 0x00000018 IRQ
IRQ IRQ
IRQ
LR
IRQ
C
void __irq IRQHandle(void)
{
void
(*p)(void);
//
int
irq_no;
//
uint32 intpnd;
//
intpnd=rINTPND;
//
//
for(irq_no=0;irq_no<32;irq_no++)
{
intpnd=intpnd>>1;
if(intpnd==0)
break;
}
//
p=(void(*)(void))VICVectAddr[irq_no];
p( );
//
}
IMPORT
IRQHandle
IRQ __irq
EINT0 EINT1
7
Mini2440 ------
Void IRQ_Eint0(void)
{
//
}
Void IRQ_Eint1(void)
{
//
}
IRQ
VICVectAddr[0] = (uint32) IRQ_Eint0;
VICVectAddr[1] = (uint32) IRQ_Eint1;
ARM 32 IRQ
S3C2440 8-23 IRQ
IRQ
IRQ IRQ IRQ
IRQ IRQ IRQ
IRQ
1.6 FIQ
ARM IRQ FIQARM

FIQ FIQ 8 FIQ
FIQ
FIQ
CPSR F
FIQ FIQ FIQ
FIQ ARM CPSR FIQ R14 SPSR

CPSR FIQ FIQ IRQ PC 0x0000001C
FIQ
FIQ
8
Mini2440 ------
HandlerFIQ
STMFD
BL
LDMFD
SUBS
SP!, {R0-R3, LR}

FIQ_Exception
SP!, {R0-R3, LR}
//
// FIQ
//
PC, LR, #4
//
FIQ_Exception C FIQ
void FIQ_Exception(void)
{
while(1);
}
//
HandlerFIQ
IMPORT
FIQ_Exception
FIQ FIQ
FIQ
FIQ FIQ
SWI CPSR FIQ
2.
ARM 7
6
CPSR
5 CPSR
CPSR
2
FIQ
IRQ
9
Mini2440 ------
R0~R7
StacksInit
//
MOV R0,LR
;// LR
;//
MSR CPSR_c,#(SVCMODE|IRQMSK|FIQMSK)//
LDR SP,=StackSvc
;//
MSR CPSR_c,#(UNDMODE|IRQMSK|FIQMSK)//
LDR SP,=StackUnd
;//
MSR CPSR_c,#(ABTMODE|IRQMSK|FIQMSK)//
LDR SP,=StackAbt
;//
MSR CPSR_c,#(IRQMODE|IRQMSK|FIQMSK)// IRQ
LDR SP,=StackIrq
;//
MSR CPSR_c,#(FIQMODE|IRQMSK|FIQMSK)// FIQ
LDR SP,=StackFiq
;//
MSR CPSR_c,#(SYSMODE|IRQMSK|FIQMSK)//
LDR SP,=StackUse
MOV
PC,R0
;//
CPSR
SP
SP
(1)
USRMODE
FIQMODE
IRQMODE
EQU
EQU
EQU
0x10 ;//
0x11 ;//
0x12 ;//
10
Mini2440 ------
SVCMODE
ABTMODE
UNDMODE
SYSMODE
IRQMSK
FIQMSK
NOINT
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0x13 ;//
0x17 ;//
0x1B ;//
0x1F ;//
0x80 ;//CPSR
0x40 ;//CPSR
0xc0;//
StackUse
StackSvc
StackUnd
StackAbt
StackIrq
StackFiq
EQU
EQU
EQU
EQU
EQU
EQU
(_STACKBASEADDR-0x3800) ;// 0x33ff4800

(_STACKBASEADDR-0x2400) ;// 0x33ff5c00
(_STACKBASEADDR-0x0)
;// 0x33ff8000
_STACKBASEADDR 0x33ff8000
IRQ IRQ
IRQ
(2)
BL
MOV
PC,LR
LR
PC LR LR
LR PC
11
Mini2440 ------
MOV
PC,LR
3.

PLL

1
1
watchdog timer WDT
MCU RST MCU
WDT WDT
MCU MCU MCU
WDT ARM
WDT
WDT
WDT
LDR R0,=WTCON
LDR R1,=0x0
STR R1,[R0]
2
2
12
Mini2440 ------
//
LDR R0,=INTMSK
LDR R1,=0xFFFFFFFF
STR R1,[R0]
//
LDR R0,=INTSUBMSK
LDR R1,=0x3FF
STR R1,[R0]
3 PLL
3
PLL
S3C2440 MPLL UPLLMPLL
FCLKHCLKPCLK CPU FCLKUPLL USB
S3C2440A
PLL
// PLL
LDR R0,=LOCKTIME
LDR R1,=0xFFFFFFFF
STR R1,[R0]
LDR R0,=CLKDIVN
MOV R1,#7
STR R1,[R0]
;//PLL
;//
;//PLL
;//
;// UPLLCON MPLLCON UPLLCON

LDR R0,=UPLLCON
;//USB
LDR R1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)
NOP
;//USB 7
NOP
NOP
NOP
NOP
NOP
NOP
LDR R0,=MPLLCON
;//
LDR R1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)
STR R1,[R0]
LOCKTIME
13
Mini2440 ------
PLL PLL PLL

FCLK LOCKTIME PLL PLL PLL
S3C2440A U_LTIMEM_LTIME 300us
12M (1/12M)*N>300N N>3600 U_LTIMEM_LTIME
3600LOCKTIME [15:0] M_LTIME[31:16] U_LTIME
CLKDIVN PCLKHCLKFCLK
S3C2440A CLOCK
UPLLCON UPLL UPLL [19:12]
U_MDIV[9:4] U_PDIV [1:0]
S
U_SDIV UPLL =m*FIN /(p*2 )

m=U_MDIV+8p=U_PDIV+2s=U_SDIVFIN 12MHZ ARM920T
5 (/) 5
7 NOP
MPLLCONMPLL MPLL [19:12]
M_MDIV[9:4] M_PDIV [1:0]
M_SDIV MPLL =2*m*FIN/(p*2 S )
m=U_MDIV+8p=U_PDIV+2s=U_SDIVFIN 12MHZ
UPLL MPLL
UPLL HDIVN
0 CPU
S3C2440
AsyncBusMode
MRC
ORR
MCR
MOV
p15,0,r0,c1,c0,0
r0,r0,#0xc0000000
p15,0,r0,c1,c0,0
PC,LR
//
//P15
MRC ARM
MRC{} 1 1 2 2
12
14
Mini2440 ------
ARM 12
MCR ARM
P15 MCR MRC
ARM cachesMMU
4
4
S3C2440A 0-0x3FFFFFFF 1G 8 BANK
BANK 128M
8 BANK BANK0
16 32 BANK 8 16 32
8 BANK 6 BANK ROMSRAM 2 ROM
SRAMSDRAM
8 BANK BANK0~BANK6 BANK7
BANK6BANK7
MINI2440 NAND FLASH NAND FLASH
SDRAM SDRAM
SDRAM
LDR
LDR
LDMIA
STMIA
LDMIA
STMIA
LTORG
R0,=BUSINIT
R1,=BWSCON
R0!, {R2-R8}
R1!, {R2-R8}
R0!, {R2-R7}
R1!, {R2-R7}
BUSINIT
DCD B7_BWCON<<28)|(B6_BWCON<<24)|(B5_BWCON<<20)|(B4_BWCON<<16)
|(B3_BWCON<<12)|(B2_BWCON<<8)|(B1_BWCON<<4) ; BWSCON
DCD (0<<13)|(0<<11)|(7<<8)|(0<<6)|(0<<4)|(0<<2)|(0<<0)
; BANKCON0
DCD (0<<13)|(0<<11)|(7<<8)|(0<<6)|(0<<4)|(0<<2)|(0<<0)
; BANKCON1
15
Mini2440 ------
DCD (0<<13)|(0<<11)|(7<<8)|(0<<6)|(0<<4)|(0<<2)|(0<<0)
; BANKCON2
DCD (0<<13)|(0<<11)|(7<<8)|(0<<6)|(0<<4)|(0<<2)|(0<<0)
; BANKCON3
DCD (0<<13)|(0<<11)|(7<<8)|(0<<6)|(0<<4)|(0<<2)|(0<<0)
; BANKCON4
DCD (0<<13)|(0<<11)|(7<<8)|(0<<6)|(0<<4)|(0<<2)|(0<<0)
; BANKCON5
DCD (3<<15)|(2<<2)|(1<<0)
; BANKCON6 (SDRAM)
DCD (3<<15)|(2<<2)|(1<<0)
; BANKCON7 (NC)
DCD (1<<23)|(0<<22)|(2<<20)|(2<<18)|(2<<16)|(1653)
; REFRESH (SDRAM)
DCD (1<<5)|(1<<4)|(2<<0)
; BANKSIZE (128MB)
DCD (3<<4)
; MRSRB6
DCD (3<<4)
; MRSRB7
R0
4K LDR NAND
FLASH NAND FLASH 4K SRAM

LDR

4K
ADR R0,BUSINIT
R1 2440
LDR
13
BWSCON
BWSCON BANK0~7
SDRAM BANK 4
BANK0 4 BWSCON [2:1]BANK0

OM[1:0] BWSCON[2:1]
BWSCON [4]
BANK7 MINI2440 BANK6 64M16 SDRAM
128M32 BANK
16
Mini2440 ------
B1_BWCON
B2_BWCON
B3_BWCON
B4_BWCON
B5_BWCON
B6_BWCON
B7_BWCON
EQU
EQU
EQU
EQU
EQU
EQU
EQU
DW8
DW16
DW32
WAIT
UBLB
EQU
EQU
EQU
EQU
EQU
(DW32)
(DW16)
(DW16)
(DW16)
(DW16)
(DW32)
(DW32)
//0010
//0001
//0001
//0001
//0001
//0010
//0010
(0x0)
(0x1)
(0x2)
(0x1<<2)
(0x1<<3)
BANK0~BANK7
BANK0~BANK5 SDRAM 0x00000700
BANK6~BANK7 SDRAM BANK
0x00018005
BANK BANK6~7
S3C2440 SDRAM
LTORG
END
BUSINIT
DCDDCD
DCD
&
4.
.c .s ARM ELF .o
ARM ELF (.axf)
fromelf ROM RAM
.bin ROM FLASH
ROM RAM
17
Mini2440 ------
0 RORW
ZI 0
RO
RW RW RO ZI ZI
RW RORW
ROM FLASH RO
RO ROM/FLASH
RAM RW RAM ZI
ZI
ZI ZI ZI RAM
RO RAM
RW RW RAM RAM ZI
Mini2440 NAND FLASH NAND FLASH NAND

FLASH Mini2440
Mini2440
18
Mini2440 ------
0x3FFFFFFF
SD RA M
RW
NAND FLASH
RO
4K
Z I
Z I
RW
RW
RO
RO
RO Base
RW Base
0x30000000
4K
Steppingstone
1 Mini2440
Mini2440 NAND FLASH NAND FLASH

BANKNAND FLASH 4K SC2440 4K
SRAMSteppingstone SRAM 0x00000000
NAND FLASH 4K NAND FLASH
Mini2440 SDRAM 0x30000000
NAND FLASH 0x30000000 SDRAM
RO RW ZI
3 RO RW
ZI
0
BL
CopyProgramFromNand
CopyProgramFromNand C
19
Mini2440 ------
MidWare nand.c
NAND FLASH ID
2RORWZI
IMPORT
IMPORT
IMPORT
IMPORT
IMPORT
IMPORT
|Image$$RO$$Base|
// RO
|Image$$RO$$Limit| // RO RW
|Image$$RW$$Base| // RW
|Image$$RW$$Limit| // RW ZI
|Image$$ZI$$Base|
// ZI
|Image$$ZI$$Limit| //ZI
IMPORT
|Image$$RO$$Base| RO |Image$$RO$$Limit| RO
RO BaseRW Base ADS Debug Se

ttings---Linker---ARM Linker---Output RO Base RO
RO
RO Base 0x30000000 MIN
I2440 SDRAM |Image$$RO$$Base| 0x30000000|Image$$RO$$Limit|
RO
RW RO |Image$$RO$$Limit| RW
RW Base RW RW
RW RO RO
|Image$$RO$$Limit||Image$$RW$$Base|
RW RAM RW Base |Image$$RW$$Base|ZI
RW |Image$$ZI$$Base||Image$$RW$$Limit|
RORWZI
LDR PC,=RunInit
// SDRAM
RunInit
20
Mini2440 ------
// RW RAM ZI
LDR R0,=|Image$$RO$$Limit| // RO +1R0 RW
LDR R1,=|Image$$RW$$Base| // RW R1
LDR R3,=|Image$$ZI$$Base|
// ZI R3
CMP R0,R1
// RW RW
BEQ %F2
// RW 2
// RW R0R1 4
CMP
R1,R3
// R1 R3 RW
LDRCC R2,[R0],#4 // R0 4 R2
STRCC R2,[R1],#4
// R2 4 R1
BCC
%B1
// 1
// ZI
LDR
R1,=|Image$$ZI$$Limit| // ZI R1
MOV
R2,#0
//0R2
//R3 4
CMP
R3,R1
//
STRCC R2,[R3],#4
// R3 4
BCC
%B3
// 3
LDR PC,=RunInit
SDRAM SDRAM
SDRAM LDR RunInit PC RunInit
ADS RO Base 0x30000000 LDR PC,=RunInit
SDRAM
LDR
R0,=|Image$$RO$$Limit| RO
R0 RW RO
RW R0
LDR
R1,=|Image$$RW$$Base| RW R1 LDR
R3,=|Image$$ZI$$Base| ZI R3
CMP
R0,R1 RW RW
CPSR
RW
BEQ
%F2BEQEQ

%F22
0~99
21
Mini2440 ------
%{F|B}{A|T}
F:
B:
A:
T:
RunInit RW
ZI Mini2440 RW
1 23
RAM
RO RW
2
2
C
1.
B
Main
Main
__main Main main
2.
B
__main
__main __Scatterload
RW/RO ZI
__main
_rt_entry main
__main _user_ininial_stackheap
22
Mini2440 ------
ResetInit
PL L
E ntr y

IR Q
F IQ
0x00000000 B
0x00000004 B
0x00000008 B
0x0000000 C B
0x00000010 B
0x00000014 B
0x00000018 B
ResetInit
HandlerUndef
HandlerSWI
HandlerPabort
HandlerDabort
.
HandlerIRQ
0x0000001 C B HandlerFIQ
IR Q
F IQ
void Main ( )
{
While
(1)
{
}
}
2 Mini2440
MINI 2440 NAND FLASH

NAND FLASH 4K CPU NAND FLASH 4K
Steppingstone RAM 0 Entry
23
Mini2440 ------
C main Entry 0
32 8
PC 0x00000000 B
ResetInitResetInit
PC 0x00000000
PC
0x00000004
SWI PC 0x00000008
1.
8
4
2.
PLL
3.
8 6
IRQ
ARM
Mini2440 NAND FLASH

24
Mini2440 ------
scatter
1ARM ..
2ARM ..
3ARM ..
25
Mini2440 ------
Mini2440 StartUp.s
;/**********************************************************************
;**MINI2440
;**
;***********************************************************************/
GET startuphead.inc;// C
;//
StackUse
EQU
StackSvc
EQU
StackUnd
EQU
(_STACKBASEADDR-0x2400) ;// 0x33ff5c00
StackAbt
EQU
StackIrq
EQU
StackFiq
EQU
(_STACKBASEADDR-0x0)
;// 0x33ff8000
; /*************************************************************************/
; //
; /*************************************************************************/
USRMODE
EQU
0x10 ;//
FIQMODE
EQU
0x11 ;//
IRQMODE
EQU
0x12 ;//
SVCMODE
EQU
0x13 ;//
ABTMODE
EQU
0x17 ;//
UNDMODE
EQU
0x1B ;//
SYSMODE
EQU
0x1F ;//
IRQMSK
FIQMSK
NOINT
EQU
EQU
EQU
0x80 ;//CPSR
0x40 ;//CPSR
0xc0 ;//
;/*******************************************************************
;**
;********************************************************************/
IMPORT |Image$$RO$$Base| ;//RO
IMPORT |Image$$RO$$Limit| ;//RO
IMPORT |Image$$RW$$Base| ;//RW
IMPORT |Image$$RW$$Limit| ;//RW
IMPORT |Image$$ZI$$Base| ;//ZI
IMPORT |Image$$ZI$$Limit| ;//ZI
IMPORT Main
;//
IMPORT CopyProgramFromNand ;// NAND FLASH SDRAM
IMPORT IRQHandle
EXPORT
IRQDisable
26
Mini2440 ------
EXPORT IRQEnable
EXPORT FIQDisable
EXPORT FIQEnable
EXPORT AsyncBusMode
EXPORT FastBusMode
;/******************************************************************
;**
;******************************************************************/
;// 32 ARM
CODE32
AREA startup,CODE,READONLY
;//AREA startup CODE

READONLY
ENTRY
;//
;//
Vectors
;//
B ResetInit
;//
B HandlerUndef
;//
B HandlerSWI
;//
B HandlerPabort
;//
B HandlerDabort
;//
B .
;//
B IRQHandle
;//
B HandlerFIQ
;//
;/********************************************************
;**
;*********************************************************/
HandlerUndef
B HandlerUndef
;/********************************************************
;**
;*********************************************************/
HandlerSWI
CMP
R0,#4
;//R0 4 4
LDRLO PC,[PC,R0,LSL #2] ;// 4 SwiFunction

MOVS PC,LR
;// 4
SwiFunction
DCD
DCD
DCD
DCD
IRQDisable
IRQEnable
FIQDisable
FIQEnable
;//
;// 0
;// 1
;// 2
;// 3
27
Mini2440 ------
IRQDisable
;// IRQ
MRS
R0,CPSR
ORR
R0,R0,#IRQMSK
MSR
SPSR_c,R0
MOVS PC,LR
IRQEnable
;// IRQ
MRS
R0,CPSR
BIC
R0,R0,#IRQMSK
MSR
SPSR_c,R0
MOVS PC,LR
FIQDisable
;// FIQ
MRS
R0,CPSR
ORR
R0,R0,#FIQMSK
MSR
SPSR_c,R0
MOVS PC,LR
FIQEnable
;// FIQ
MRS
R0,CPSR
BIC
R0,R0,#FIQMSK
MSR
SPSR_c,R0
MOVS PC,LR
;/********************************************************
;**
;**
;*********************************************************/
HandlerPabort
B HandlerPabort
;/********************************************************
;**
;**
;*********************************************************/
HandlerDabort
B HandlerDabort
;/********************************************************
;**
;**
;*********************************************************/
HandlerFIQ
B HandlerFIQ
;/*************************************************************
;**
;** 0
;**************************************************************/
ResetInit
28
Mini2440 ------
;//1.
LDR R0,=WTCON
LDR R1,=0x0
STR R1,[R0]
;//2.
LDR R0,=INTMSK
LDR R1,=0xFFFFFFFF
STR R1,[R0]
;//
LDR R0,=INTSUBMSK
LDR R1,=0x7FFF
STR R1,[R0]
;//3. PLL
LDR R0,=LOCKTIME
LDR R1,=0xFFFFFF
STR R1,[R0]
LDR R0,=CLKDIVN
MOV R1,#5
STR R1,[R0]
;//PLL
;//
;//PLL
;//
;// UPLLCON MPLLCON UPLLCON

LDR R0,=UPLLCON
;//USB
LDR R1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)
STR R1,[R0]
NOP
;//USB 7
NOP
NOP
NOP
NOP
NOP
NOP
LDR R0,=MPLLCON
;//
LDR R1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)
STR R1,[R0]
;//4.
ADR
R0,BUSINIT
LDR
R1,=BWSCON
;//ADR
29
Mini2440 ------
LDMIA
STMIA
LDMIA
STMIA
R0!, {R2-R8}
R1!, {R2-R8}
R0!, {R2-R7}
R1!, {R2-R7}
;//5.
BL StacksInit
;// NAND FLASH SDRAM
BL CopyProgramFromNand
LDR PC,=RunInit
RunInit
LDR
LDR
LDR
R0,=|Image$$RO$$Limit|
R1,=|Image$$RW$$Base|
R3,=|Image$$ZI$$Base|
CMP
BEQ
R0,R1
%F2
1
CMP
LDRCC
STRCC
BCC
R1,R3
R2,[R0],#4
R2,[R1],#4
%B1
LDR
MOV
R1,=|Image$$ZI$$Limit|
R2,#0
CMP
STRCC
BCC
R3,R1
R2,[R3],#4
%B3
;// CPU
BL
AsyncBusMode
B
Main
;/************************************************************
;**
;**
;**
;**
;************************************************************/
StacksInit
MOV R0,LR ;// LR
30
Mini2440 ------
;//
MSR CPSR_c,#(SVCMODE|IRQMSK|FIQMSK)
LDR
SP,=StackSvc
;//
MSR CPSR_c,#(UNDMODE|IRQMSK|FIQMSK)
LDR
SP,=StackUnd
;//
MSR CPSR_c,#(ABTMODE|IRQMSK|FIQMSK)
LDR
SP,=StackAbt
;//
MSR CPSR_c,#(IRQMODE|IRQMSK|FIQMSK)
LDR
SP,=StackIrq
;//
MSR CPSR_c,#(FIQMODE|IRQMSK|FIQMSK)
LDR
SP,=StackFiq
;//,
MSR CPSR_c,#(SYSMODE|IRQMSK|FIQMSK)
LDR SP,=StackUse
MOV
PC,R0 ;//
;/********************************************************
;** CPU
;**MPLLCON M_PDIV 1
;*********************************************************/
AsyncBusMode
MRC p15,0,r0,c1,c0,0
ORR r0,r0,#0xc0000000
MCR p15,0,r0,c1,c0,0
MOV PC,LR
;/********************************************************
;** CPU
;*********************************************************/
FastBusMode
MRC p15,0,r0,c1,c0,0
BIC r0,r0,#0xc0000000
MCR p15,0,r0,c1,c0,0
MOV PC,LR
;/********************************************************
;**
31
Mini2440 ------
;** BANK
;**
;*********************************************************/
LTORG
BUSINIT
DCD (B7_BWCON<<28)|(B6_BWCON<<24)|(B5_BWCON<<20)|(B4_BWCON<<16)
|(B3_BWCON<<12)|(B2_BWCON<<8)|(B1_BWCON<<4)
; BWSCON
DCD (0x3<<13)|(0x3<<11)|(0x7<<8)|(0x3<<6)|(0x3<<4)|(0x1<<2)|(0<<0) ; BANKCON0
DCD (1<<13)|(1<<11)|(6<<8)|(1<<6)|(1<<4)|(0<<2)|(0<<0)
; BANKCON1
DCD (1<<13)|(1<<11)|(6<<8)|(1<<6)|(1<<4)|(0<<2)|(0<<0)
; BANKCON2
DCD (1<<13)|(1<<11)|(6<<8)|(1<<6)|(1<<4)|(0<<2)|(0<<0)
; BANKCON3
DCD (1<<13)|(1<<11)|(6<<8)|(1<<6)|(1<<4)|(0<<2)|(0<<0)
; BANKCON4
DCD (1<<13)|(1<<11)|(6<<8)|(1<<6)|(1<<4)|(0<<2)|(0<<0)
; BANKCON5
DCD (3<<15)|(2<<2)|(1<<0)
; BANKCON6 (SDRAM)
DCD (3<<15)|(2<<2)|(1<<0)
; BANKCON7 (SRAM )
DCD (1<<23)|(0<<22)|(2<<20)|(2<<18)|(2<<16)|(1012) ; REFRESH (SDRAM)
period=15.6us, HCLK=60Mhz, (2048+1-15.6*60)
DCD (1<<5)|(1<<4)|(2<<0)
; BANKSIZE (128MB)
DCD (3<<4)
; MRSRB6
DCD (3<<4)
END
32
Mini2440 ------
startuphead.inc
startuphead.inc
M_MDIV
M_PDIV
M_SDIV
EQU
EQU
EQU
U_MDIV
U_PDIV
U_SDIV
EQU
EQU
EQU
WTCON
INTMSK
INTSUBMSK
LOCKTIME
CLKDIVN
MPLLCON
BWSCON
UPLLCON
DW8
DW16
DW32
WAIT
UBLB
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
B1_BWCON
B2_BWCON
B3_BWCON
B4_BWCON
B5_BWCON
B6_BWCON
B7_BWCON
EQU
EQU
EQU
EQU
EQU
EQU
EQU
92
1
1
56
2
2
0x53000000
0x4A000008
0x4A00001C
0x4C000000
0x4C000014
0x4C000004
0x48000000
0x4C000008
(0x0)
(0x1)
(0x2)
(0x1<<2)
(0x1<<3)
(DW16)
(DW16)
(DW16)
(DW32)
(DW16)
(DW32)
(DW32)
; PCMCIA(PD6710), 16-bit
; Ethernet(CS8900), 16-bit
; A400/A410 Ext, 16-bit
; N.C.
END
33

MINI2440启动代码的编写

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MINI2440启动代码的编写

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Mini2440 ------

S3C2440 NOR FLASH NAND FLASH FLASH

startup,CODE,READONLY //AREA startup CODE

CPU CPSR R14

SWI SWI CPSR

LDRLO PC,[PC,R0,LSL #2]

4 IRQ IRQ FIQ

IRQ SPSR CPSR IRQ IRQ

ARM IRQ FIQARM

FIQ ARM CPSR FIQ R14 SPSR

SP!, {R0-R3, LR}

(_STACKBASEADDR-0x3800) ;// 0x33ff4800

;// UPLLCON MPLLCON UPLLCON

PLL PLL PLL

U_SDIV UPLL =m*FIN /(p*2 )

MINI2440 NAND FLASH NAND FLASH

FLASH NAND FLASH 4K SRAM

BANK0 4 BWSCON [2:1]BANK0

Mini2440 NAND FLASH NAND FLASH NAND

Mini2440 NAND FLASH NAND FLASH

RO BaseRW Base ADS Debug Se

MINI 2440 NAND FLASH

Mini2440 NAND FLASH

;//AREA startup CODE

LDRLO PC,[PC,R0,LSL #2] ;// 4 SwiFunction

;// UPLLCON MPLLCON UPLLCON

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U_SDIV UPLL =mFIN /(p2 )