ANANTH SHETTY K R

Email: ananthsetty05@gmail.com
Mobile No: 8105010222

Objective
To become a more challenging full custom layout design engineer proficient in effective floor plan and optimized
layout designs in future technologies.

Core Competencies

Worked on Custom layout design of 180nm, 90nm & 28nm technologies

Knowledge of complete ASIC flow, Full custom flow and sub-flows

Knowledge of Layout development and Verification (DRC,LVS& Parasitic Extraction)

Played an important role in designing the layouts for standard cells and analog blocks such as OPAMP

Played an important role in designing the layout for SRAM Memory Compiler using 28nm

Good understanding of LVS errors, shorts, opens, real and false errors

Knowledge of analog layout concepts like Matching, symmetry

Knowledge of EDA tools such as Cadence, Mentor Graphics and Synopsys

Good exposure to technology by undergoing additional training in VLSI

Good understanding of fundamentals of Transistors and CMOS device operation

Good knowledge of Digital Design Concepts

Working Knowledge of Linux

Good knowledge on parasitics and their effects on performance

Education Profile

M.Tech - Industrial Electronics from SJCE, Mysore, Affiliated to VTU, 2015, with 8.48 CGPA (77.3%)

B.E Electronics and Communication Engineering (under VTU) from KLEIT, Hubli, 2012, with aggregate
of 70.12%

Senior Secondary Class 12 (PUC II), Fatima Composite PU College, Hubli, 2008, with aggregate of 78%

Class 10 (SSLC), Saint Andrews English Medium High School, Hubli, 2006, with aggregate of 82.24%

Experience
Trainee at RV-VLSI Design Center:
As a trainee in RV-VLSI Design Center, I physically verified layouts for various standard cells in 180nm, 90nm
and 28nm technology nodes of TSMC and Jazz semiconductor foundries respectively. Worked on 28nm 32x32
SRAM Memory Layout compiler where I was designing layouts of leaf cells.

Projects
1) 90nm 9track Standard Cell Library Design
Designing Standard Cells Library for Combinational Circuits such as:
INVERTER: INVx1, NOR: NOR2x1, NAND: NAND2X1, HALF ADDER: HADDx2, MUX: MUX21x2

Sequential Circuits such as: D- Flip Flop: DFFX1, DFFX2

Tools Used:
IC studio: Mentor Graphics
Pyxis: Schematic and Layout editor
Calibre RVE: DRC & LVS check
Deliverable/Challenges Faced:
1. Fitting the complete layout within the PR-Boundary including n-tap and p-tap maintaining all DRC rules
2. Making the layout as optimized as possible by Source & Drain sharing
3. Reducing the parasitic by making use of metal over poly
4. Placing as many contacts for connecting the metals for the reduction of parasitic
5. Placing metal pins on grid by maintaining proper distance among them to satisfy compatibility of the design

2) Two Stage Differential Amplifier Layout Design in 180nm Technology

Tools Used:
IC studio: Mentor Graphics.
Pyxis: Schematic and Layout editor.
Calibre RVE: DRC & LVS check.
Deliverable/Challenges Faced:
1. Making common centroid
2. Device matching
3. Maintaining of metal width such that in order to come across cross talk
4. To overcome Latch-up & Electro Migration problem
5. DRC is error free but to make error free LVS filter is needed because dummies are to be neglected

3) Design of Leaf Cell for SRAM Memory in 28nm Technology

Designing Standard Cells Library for Combinational Circuits such as:
INVERTER: INVx1, INVx2, NAND: NAND2x1, NAND2x2, NAND2x4, NOR: NOR3x1, NOR3x2, NOR3x4,
AND: AND2x1, AND3x1, OR: OR3x1, OR3x2, OR3x4
Tools Used:
IC studio: Mentor Graphics
Pyxis: Schematic and Layout editor
Calibre RVE: DRC & LVS check
Deliverable/Challenges Faced:
1. Placing contacts and polys on grid
2. There are no pin placement rules
3. Reducing the parasitic by making use of metal over poly