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3 Description
2 Applications
AV Receivers
Portable Audio Docks
Blu-Ray Players
Home Theater
MP3 Players or Recorders
Personal Digital Assistants (PDAs)
Device Information(1)
PART NUMBER
PACKAGE
SN74LS00DB
SSOP (14)
6.20 mm 5.30 mm
SN7400D,
SN74LS00D,
SN74S00D
SOIC (14)
8.65 mm 3.91 mm
SN74LS00NSR
PDIP (14)
19.30 6.35 mm
SNJ5400J,
SNJ54LS00J,
SNJ54S00J
CDIP (14)
19.56 mm 6.67 mm
SNJ5400W,
SNJ54LS00W,
SNJ54S00W
CFP (14)
9.21 mm 5.97 mm
SN54LS00FK,
SN54S00FK
LCCC (20)
8.89 mm 8.89 mm
SN7400NS,
SN74LS00NS,
SN74S00NS
SO (14)
10.30 mm 5.30 mm
SN7400PS,
SN74LS00PS
SO (8)
6.20 mm 5.30 mm
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
5
5
5
5
6
6
6
6
12
12
12
12
12
12
12
4 Revision History
Changes from Revision B (October 2003) to Revision C
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changed Ordering Information table to Device Comparison Table; see Package Option Addendum at the end of the
data sheet ............................................................................................................................................................................... 1
Changed Package thermal impedance, RJA, values in Thermal Information table From: 86C/W To: 90.9C/W (D),
From: 96C/W To: 102.8C/W (DB), From: 80C/W To: 54.8C/W (N), and From: 76C/W To: 89.7C/W (NS)................... 5
1A
14
VCC
1B
13
4A
1Y
12
4B
2A
11
4Y
2B
10
3A
2Y
3B
GND
3Y
SN74xx00 PS Package
18-Pin SO
Top View
1A
VCC
1B
2B
1Y
2A
GND
2Y
Not to scale
12
4A
VCC
11
GND
2Y
10
3B
2A
3A
2B
3Y
1A
NC
VCC
4B
20
19
2A
16
4Y
NC
15
NC
2B
14
3B
2Y
13
1Y
NC
3A
4B
17
12
13
3Y
NC
11
1B
4A
NC
4Y
18
10
14
GND
1Y
1A
SN5400 W Package
14-Pin CFP
Top View
1B
Not to scale
SN54xx00 FK Package
20-Pin LCCC
Top View
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
SO
(SN74xx00)
CFP
(SN5400)
LCCC
1A
Gate 1 input
1B
Gate 1 input
1Y
Gate 1 output
2A
Gate 2 input
2B
Gate 2 input
2Y
Gate 2 output
3A
10
13
Gate 3 input
3B
10
14
Gate 3 input
3Y
12
Gate 3 output
4A
13
12
18
Gate 4 input
NAME
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DESCRIPTION
SO
(SN74xx00)
CFP
(SN5400)
LCCC
4B
12
13
19
Gate 4 input
4Y
11
14
16
Gate 4 output
GND
11
10
Ground
No connect
Power supply
NAME
NC
1, 5, 7,
11, 15, 17
VCC
14
20
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input voltage
5.5
SNx4LS00
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
7
65
150
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to network ground terminal.
Electrostatic
discharge
(1)
UNIT
500
2000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as 2000 V may actually have higher performance. Tested
on SN74LS00N package.
VCC
Supply voltage
VIH
VIL
IOH
IOL
MIN
NOM
MAX
SN54xx00
4.5
5.5
SN74xx00
4.75
5.25
2
0.8
SN54LS00
0.7
0.4
SNx4S00
SNx400
16
SN5LS400
SN7LS400
SNx4S00
TA
V
V
UNIT
V
mA
mA
20
SN54xx00
55
125
SN74xx00
70
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
14 PINS
14 PINS
14 PINS
14 PINS
90.9
102.8
54.8
89.7
C/W
51.9
53.3
42.1
48.1
C/W
48
53.4
34.8
50.1
C/W
UNIT
RJB
JT
18.6
16.5
26.9
16.7
C/W
JB
47.8
52.9
34.7
49.8
C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.5
VIK
VOH
VOL
II
mA
IIH
40
IIL
1.6
mA
IOS
VCC = MAX
ICCH
ICCL
2.4
3.4
0.2
V
0.4
SN5400
20
55
SN7400
18
55
mA
mA
12
22
mA
TYP
MAX
UNIT
1.5
TEST CONDITIONS
VIK
VOH
MIN
2.5
3.4
IOL = 4 mA
0.25
0.4
IOL = 8 mA (SN74LS00)
0.35
0.5
VOL
II
0.1
mA
IIH
20
IIL
IOS
VCC = MAX
ICCH
ICCL
0.4
mA
100
mA
0.8
1.6
mA
2.4
4.4
mA
20
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.2
VIK
VOH
VOL
II
IIH
50
IIL
mA
2.5
3.4
V
0.5
V
mA
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TEST CONDITIONS
MIN
TYP
40
MAX
UNIT
IOS
VCC = MAX
100
mA
ICCH
10
16
mA
ICCL
20
36
mA
FROM (INPUT)
TO (OUTPUT)
A or B
tPHL
TEST CONDITIONS
MIN
RL = 400 and CL = 15 pF
TYP
MAX
11
22
15
TYP
MAX
15
10
15
UNIT
ns
FROM (INPUT)
TO (OUTPUT)
TEST CONDITIONS
A or B
RL = 2 k and CL = 15 pF
MIN
UNIT
ns
FROM (INPUT)
A or B
tPHL
TO (OUTPUT)
Y
A or B
TYP
MAX
RL = 280 and CL = 15 pF
TEST CONDITIONS
MIN
4.5
RL = 280 and CL = 50 pF
4.5
RL = 280 and CL = 15 pF
RL = 280 and CL = 50 pF
UNIT
ns
TPHL (ns)
12
10
8
6
4
2
1
2
Device
3
D001
VCC
RL
(see Note B)
From Output
Under Test
CL
(see Note A)
High-Level
Pulse
1.5 V
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.5 V
1 k
Test
Point
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
S1
(see Note B)
CL
(see Note A)
RL
CL
(see Note A)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.5 V
0V
tw
Low-Level
Pulse
1.5 V
tsu
Data
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
In-Phase
Output
(see Note D)
tPHL
VOH
1.5 V
0V
1.5 V
1.5 V
1.5 V
0V
tPZL
Waveform 1
(see Notes C
and D)
tPLZ
VOL
tPZH
tPLH
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2
(see Notes C
and D)
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
1.5 V
3V
Output
Control
(low-level
enabling)
0V
tPLH
3V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
th
VOL + 0.5 V
tPHZ
VOH
1.5 V
VOH 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
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8 Detailed Description
8.1 Overview
The SNx4xx00 devices are quadruple, 2-input NAND gates which perform the Boolean function Y = A B or Y =
A + B in positive logic.
8.4
OUTPUT
Y1
A2
B2
C2
Y2
www.ti.com
TPLH(ns)
20
15
10
0
1
2
Device
3
D001
10
11 Layout
11.1 Layout Guidelines
When using multiple bit logic, devices inputs must never float.
Devices with multiple-emitter inputs (SN74 and SN74S series) need special care. Because no voltage greater
than 5.5 V must be applied to the inputs (if exceeded, the base-emitter junction at the inputs breaks down), the
inputs of these devices must be connected to the supply voltage, VCC, through series resistor, RS (see Figure 5).
This resistor must be dimensioned such that the current flowing into the gate or gates, which results from
overvoltage, does not exceed 1 mA. However, because the high-level input current of the circuits connected to
the gate flows through this resistor, the resistor must be dimensioned so that the voltage drop across it still
allows the required high level. Equation 1 and Equation 2 are for dimensioning resistor, RS, and several inputs
can be connected to a high level through a single resistor if the following conditions are met.
V * 5.5 V
R S(min) + CCP
1 mA
(1)
VCC(min) * 2.4 V
R S(max) +
n I IH
where
(2)
&
Output
Input
11
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PRODUCT FOLDER
TECHNICAL
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COMMUNITY
SN5400
Click here
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SN54LS00
Click here
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SN54S00
Click here
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SN7400
Click here
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SN74LS00
Click here
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SN74S00
Click here
Click here
Click here
Click here
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12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12
13
www.ti.com
18-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
JM38510/00104BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
00104BCA
JM38510/00104BDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/
00104BDA
JM38510/07001BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
07001BCA
JM38510/07001BDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/
07001BDA
JM38510/30001B2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
JM38510/
30001B2A
JM38510/30001BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
30001BCA
JM38510/30001BDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/
30001BDA
JM38510/30001SCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/30001S
CA
JM38510/30001SDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/30001S
DA
M38510/00104BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
00104BCA
M38510/00104BDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/
00104BDA
M38510/07001BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
07001BCA
M38510/07001BDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/
07001BDA
M38510/30001B2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
JM38510/
30001B2A
M38510/30001BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
30001BCA
M38510/30001BDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/
30001BDA
M38510/30001SCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/30001S
CA
Addendum-Page 1
Samples
www.ti.com
18-Mar-2016
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
M38510/30001SDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
JM38510/30001S
DA
SN5400J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN5400J
SN54LS00J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN54LS00J
SN54S00J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN54S00J
SN7400D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7400
SN7400DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7400
SN7400N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN7400N
SN7400N3
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SN7400NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN7400N
SN74LS00D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74LS00DBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
0 to 70
SN74LS00DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74LS00DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74LS00DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74LS00DRE4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74LS00J
OBSOLETE
CDIP
14
TBD
Call TI
Call TI
0 to 70
SN74LS00N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS00N
SN74LS00NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS00N
SN74LS00NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS00
SN74LS00NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS00
Addendum-Page 2
Samples
www.ti.com
18-Mar-2016
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
SN74LS00PSR
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74LS00PSRG4
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS00
SN74S00D
NRND
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S00
SN74S00DE4
NRND
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S00
SN74S00N
NRND
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74S00N
SN74S00N3
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SN74S00NE4
NRND
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74S00N
SNJ5400J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SNJ5400J
SNJ5400W
ACTIVE
CFP
14
TBD
A42
-55 to 125
SNJ5400W
SNJ5400WA
OBSOLETE
CFP
WA
14
TBD
A42
-55 to 125
SNJ5400WA
SNJ54LS00FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
SNJ54LS00FK
SNJ54LS00J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SNJ54LS00J
SNJ54LS00W
ACTIVE
CFP
14
TBD
A42
-55 to 125
SNJ54LS00W
SNJ54S00FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
SNJ54S
00FK
SNJ54S00J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SNJ54S00J
SNJ54S00W
ACTIVE
CFP
14
TBD
A42
-55 to 125
SNJ54S00W
(1)
Addendum-Page 3
Samples
www.ti.com
18-Mar-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5400, SN54LS00, SN54LS00-SP, SN54S00, SN7400, SN74LS00, SN74S00 :
Addendum-Page 4
www.ti.com
18-Mar-2016
Addendum-Page 5
18-Mar-2016
Device
SN74LS00DBR
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DB
14
2000
330.0
16.4
8.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.6
2.5
12.0
16.0
Q1
SN74LS00DR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LS00NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LS00PSR
SO
PS
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
Pack Materials-Page 1
18-Mar-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LS00DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74LS00DR
SOIC
14
2500
367.0
367.0
38.0
SN74LS00NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LS00PSR
SO
PS
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
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