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Adders
1a.
Parallel Adder
1b.
1c.
1d.
1e.
BCD Adder
Multipliers
2a.
Signed Multiplier
2b.
2c.
2d.
2e.
Booth Multiplier
3.
4.
5.
6.
7.
8.
9.
Implementation of Alarm
embedded microcontroller
Clock
using
10.
PAGE
NO.
SIGNATURE
EX. NO.:
DATE :
DESIGN AND IMPLEMENTATION OF PARALLEL ADDER
AIM:To design a PARALLEL ADDER using Xilinx and simulate it using Model Sim
RTL SCHEMATIC:
PROGRAM:
module add(dataa,datab,clk,result);
input [7:0]dataa;
input [7:0]datab;
input clk;
output [8:0]result;
reg [8:0]result;
always @ (posedge clk)
begin
result=dataa+datab;
end
endmodule
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : add.ngr
Top Level Output File Name
: add
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 26
Cell Usage :
# BELS
: 25
#
GND
:1
#
LUT2
:8
#
MUXCY
:8
#
XORCY
:8
# FlipFlops/Latches
:9
#
FD
:9
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
: 25
#
IBUF
: 16
#
OBUF
:9
==================================================================
Device utilization summary:
--------------------------Selected Device : xa3s400pqg208-4
Number of Slices:
4 out of 3584 0%
Number of 4 input LUTs:
8 out of 7168 0%
Number of IOs:
26
Number of bonded IOBs:
26 out of 141 18%
IOB Flip Flops:
9
Number of GCLKs:
1 out of
8 12%
-------------------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|9 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
OUTPUT:
RESULT:Thus the 4 bit parallel adder has been designed and verified using Xilinx and
ModelSim
EX. NO.:
DATE :
DESIGN AND IMPLEMENTATION OF RIPPLE CARRY ADDER
AIM:To design 4-bit ripple carry adder using Xilinx and simulate it using Model Sim
PROGRAM:
module rca(a,b,cin,s,cout);
input [3:0] a;
input [3:0] b;
input cin;
output [3:0] s;
output cout;
reg [4:0]c;
reg [3:0]s;
reg cout;
integer i;
always@(a or b or cin)
begin
for(i=0;i<4;i=i+1)
begin
c[0]=cin;
s[i]=a[i]^b[i]^c[i];
c[i+1]=a[i]&b[i]|c[i]&b[i]|a[i]&c[i];
cout=c[4];
end
end
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
=======
*
Final Report
*
==================================================================
=======
Final Results
RTL Top Level Output File Name : rca.ngr
Top Level Output File Name
: rca
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 14
Cell Usage :
# BELS
:8
#
LUT3
:8
# IO Buffers
: 14
#
IBUF
:9
#
OBUF
:5
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : xa3s400pqg208-4
Number of Slices:
4 out of 3584 0%
Number of 4 input LUTs:
8 out of 7168 0%
Number of IOs:
14
Number of bonded IOBs:
14 out of 141 9%
--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
--------------------------==================================================================
=======
Timing Summary:
--------------Speed Grade: -4
OUTPUT:
RESULT:Thus the 4 bit ripple carry adder has been designed and verified using Xilinx and
Model sim.
EX. NO.:
DATE :
DESIGN & IMPLEMENTATION OF CARRY LOOK AHEAD ADDER
AIM:To design a 4-bit carry look ahead adder using Xilinx and simulate it using Model Sim
ALGORITHM:1. Using a look ahead carry generator we can easily construct a 4 bit parallel adder
with as look ahead carry scheme.
2. .Sum outputs requires the two exclusive OR gates
3. The output of the first EXOR gate generates Pi and the AND gate generate Gi such
that Pi=a^b and Gi=a&b;
4. The carry bit is generated using look ahead carry generator and it is applied as input
to the second EXOR gate Ci+1=Gi+Pi
5. The other inputs to EXOR gate is Pi
6. The sum outputs are obtained form the second XOR gate S =P^C
PROGRAM:
module cla(a,b,cin,s,c);
input [3:0]a,b;
input cin;
output [3:0]c,s;
wire [3:0] g,p;
assign g=a&b;
assign p=a^b;
assign c[0]=g[0]+(p[0]&cin);
assign c[1]=g[1]+(p[1]&c[0]);
assign c[2]=g[2]+(p[2]&g[1])+(p[1]&p[2]&c[0]);
assign c[3]=g[3]+(p[3]&g[2])+(p[3]&p[2]&g[1])+(p[3]&p[2]&p[1]&c[0]);
assign s=p^c;
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
==================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
: cla.ngr
: cla
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 17
Cell Usage :
# BELS
: 12
LUT2
:1
LUT3
:4
LUT4
:7
# IO Buffers
#
IBUF
OBUF
: 17
:9
:8
7 out of 7680
0%
12 out of 15360
17
17 out of
221
--------------------------TIMING REPORT
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
---------------
0%
7%
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 12.431ns
Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default path analysis
Total number of paths / destination ports: 66 / 8
------------------------------------------------------------------------Delay:
Source:
a<1> (PAD)
Destination:
c<3> (PAD)
Net
---------------------------------------- -----------IBUF:I->O
LUT4:I0->O
LUT4:I1->O
LUT4:I0->O
OBUF:I->O
5.644
c_3_OBUF (c<3>)
---------------------------------------Total
==================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.58 secs
Total memory usage is 273564 kilobytes
OUTPUT:
RESULT:Thus the 4 bit carry look ahead adder has been designed and verified using Xilinx
and Model Sim.
EX. NO.:
DATE
RTL SCHEMATIC:
PROGRAM:
module man(a,b,p,g,k);
input a,b;
output p,g,k;
assign p=a^b;
assign g=a&b;
assign k=~(a^b);
endmodule
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : man.ngr
Top Level Output File Name
: man
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:5
Cell Usage :
# BELS
:3
#
LUT2
:3
# IO Buffers
:5
#
IBUF
:2
#
OBUF
:3
==================================================================
Device utilization summary:
--------------------------Selected Device : 3s1000fg320-4
Number of Slices:
2 out of 7680 0%
Number of 4 input LUTs:
3 out of 15360 0%
Number of IOs:
5
Number of bonded IOBs:
5 out of 221 2%
--------------------------Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.063ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
Delay:
9.063ns (Levels of Logic = 3)
Source:
a (PAD)
Destination:
g (PAD)
Data Path: a to g
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
3 0.821 1.246 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.551 0.801 g1 (g_OBUF)
OBUF:I->O
5.644
g_OBUF (g)
---------------------------------------Total
9.063ns (7.016ns logic, 2.047ns route)
(77.4% logic, 22.6% route)
==================================================================
=======
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.95 secs
-->
Total memory usage is 257664 kilobytes
OUTPUT:
RESULT:
Thus the 8 bit Manchester carry chain adder is designed and verified using Xilinx
and Model sim.
EX. NO.:
DATE
To design 4-bit BCD adder using Xilinx and simulate it using Model Sim
SOFTWARE REQUIRED:-
1. Xilinx 6.0
2. Model sim
4. One logic circuit for checking sum value if sum is less than10, correction is
needed .If the sum is more than 9 six is to be added.
PROGRAM:
module bcd(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [4:0] s;
output cout;
reg [4:0] c,s;
reg cout;
integer i;
always@(a or b or cin)
begin
for(i=0;i<4;i=i+1)
begin
c[0]=cin;
s[i]=a[i]^b[i]^c[i];
c[i+1] =(a[i]&b[i])|(c[i]&b[i]& b[i])|(a[i]&c[i]);
cout=c[4];
s[4]=c[4];
end
if (s[3:0]>4'b1001|c[4]==1)
begin
s[4:0]=s[3:0]+4'b0110;
s[4]=cout;
end
end
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : bcd.ngr
Top Level Output File Name
: bcd
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 15
Cell Usage :
# BELS
: 11
#
LUT3
:8
#
LUT4
:3
# IO Buffers
: 15
#
IBUF
:9
#
OBUF
:6
==================================================================
Device utilization summary:
--------------------------Selected Device : 3s1000fg320-4
Number of Slices:
6 out of 7680 0%
Number of 4 input LUTs:
11 out of 15360 0%
Number of IOs:
15
Number of bonded IOBs:
15 out of 221 6%
--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
--------------------------==================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
OUTPUT:
RESULT:Thus the 4 bit BCD adder has been designed and verified using Xilinx and Model Sim.
EX. NO.:
DATE :
SIGNED MULTIPLLIER
AIM:
To design a 4-bit signed multiplier using Xilinx and simulate it using Model Sim.
SOFTWARE REQUIRED:1. Xilinx 6.0
2. Model sim
ALGORITHM:
If the entered numbers are positive then multiply the two numbers.
If the entered number is a negative number then take 2s complement of that number
and multiply.
The step three is followed if the two 4-bit numbers are negative.
The output is obtained such that the positive output value is stored in c and the
negative output value is stored in f.
PROGRAM:
module Sig(a,b,mul,clk);
input signed[7:0] a,b;
output signed[15:0] mul;
input clk;
reg signed [7:0]a_reg,b_reg;
wire signed [15:0]mul;
assign mul=a_reg*b_reg;
always @(posedge clk)
begin
a_reg<=a;
b_reg<=b;
end
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : Sig.ngr
Top Level Output File Name
: Sig
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 33
Cell Usage :
# FlipFlops/Latches
: 16
#
FD
: 16
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
: 32
#
IBUF
: 16
#
OBUF
: 16
# MULTs
:1
#
MULT18X18
:1
==================================================================
Device utilization summary:
--------------------------Selected Device : 3s1000fg320-4
Number of Slices:
0 out of 7680 0%
Number of IOs:
33
Number of bonded IOBs:
33 out of 221 14%
IOB Flip Flops:
16
Number of MULT18X18s:
1 out of 24 4%
Number of GCLKs:
1 out of
8 12%
--------------------------Clock Information:
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 16 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: 1.825ns
Maximum output required time after clock: 11.924ns
All values displayed in nanoseconds (ns)
==================================================================
OUTPUT:
RESULT:
Thus the 4-bit signed multiplier has been designed and verified successfully.
EX. NO.:
DATE :
WALLACE TREE MULTIPLIER
AIM:
To design a wallace tree multiplier using Xilinx and simulate it using Model Sim.
SOFTWARE REQUIRED:1. Xilinx 6.0
2. Model sim
HARDWARE REQUIRED:1. FPGA kit
ALGORITHM:
PROGRAM:
module wamul(x,y,p);
input [3:0] x;
input [3:0] y;
output [7:0] p;
wire [5:0] s;
wire [10:0] c;
assign p[0]=x[0]&y[0];
fa f1(x[0]&y[1],x[1]&y[0],1'b0,p[1],c[0]);
fa f2(x[2]&y[0],x[1]&y[1],x[0]&y[2],s[0],c[1]);
fa f3(x[3]&y[0],x[2]&y[1],x[1]&y[2],s[1],c[2]);
fa f4(x[3]&y[1],x[2]&y[2],1'b0,s[2],c[3]);
fa f5(s[0],c[0],1'b0,p[2],c[4]);
fa f6(s[1],c[1],x[0]&y[3],s[3],c[5]);
fa f7(s[2],c[2],x[1]&y[3],s[4],c[6]);
fa f8(x[1]&y[2],c[3],x[2]&y[3],s[5],c[7]);
fa f9(s[3],c[4],1'b0,p[3],c[8]);
fa f10(s[4],c[5],c[8],p[4],c[9]);
fa f11(s[5],c[6],c[9],p[5],c[10]);
fa f12(x[3]&y[3],c[7],c[10],p[6],p[7]);
endmodule
module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : wamul.ngr
Top Level Output File Name
: wamul
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 16
Cell Usage :
# BELS
: 29
#
LUT2
:8
#
LUT3
:4
#
LUT4
: 17
# IO Buffers
: 16
#
IBUF
:8
#
OBUF
:8
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : xa3s400pqg208-4
Number of Slices:
17 out of 3584 0%
Number of 4 input LUTs:
29 out of 7168 0%
Number of IOs:
16
Number of bonded IOBs:
16 out of 141 11%
--------------------------Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 19.761ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
==================================================================
=======
Timing constraint: Default path analysis
OUTPUT:
RESULT:
Thus the Wallace tree multiplier has been designed and verified successfully.
EX. NO.:
DATE :
2s COMPLEMENT MULTIPLIER
AIM:
To design a 2s complements multiplier using Xilinx and to verify it using Model
Sim.
ALGORITHM:
1. Enter the two 8 bit numbers a and b.
4. The full adder operation is performed. The output of the sum is kept constant
and each of the carry c is used for next successive bit combinations.
PROGRAM:
module com(a,b,out);
input [3:0]a,b;
output [3:0]out;
wire [3:0]w,x;
assign x=~a+1'b1;
shif g1(x,b,w);
assign out=~w+1'b1;
endmodule
module shif(x,y,z);
input [3:0]x,y;
output [7:0]z;
reg [7:0]t,z;
integer i;
always @ (x or y )
begin
z=8'b0;
for(i=0;i<4;i=i+1)
begin
t=8'b0;
if (y[i])
begin
t[i]=x[0];
t[i+1]=x[1];
t[i+2]=x[2];
t[i+3]=x[3];
end
z=z+t;
end
end
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : com.ngr
Top Level Output File Name
: com
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 12
Cell Usage :
# BELS
: 17
#
LUT2
:3
#
LUT3
:2
#
LUT4
: 12
# IO Buffers
: 12
#
IBUF
:8
#
OBUF
:4
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : 3s1000fg320-4
Number of Slices:
10 out of 7680 0%
Number of 4 input LUTs:
17 out of 15360 0%
Number of IOs:
12
Number of bonded IOBs:
12 out of 221 5%
--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
--------------------------==================================================================
=======
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 15.690ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
==================================================================
=======
Timing constraint: Default path analysis
Total number of paths / destination ports: 76 / 4
------------------------------------------------------------------------Delay:
15.690ns (Levels of Logic = 7)
Source:
b<1> (PAD)
Destination:
out<3> (PAD)
Data Path: b<1> to out<3>
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
6 0.821 1.342 b_1_IBUF (b_1_IBUF)
LUT3:I0->O
2 0.551 1.216 g1/z_mux00061 (g1/z_mux0006)
LUT4:I0->O
3 0.551 1.246 g1/Madd__old_z_4_Madd_lut<2> (w<2>)
LUT4:I0->O
1 0.551 0.869 g1/Madd__old_z_4_Madd_cy<2>1
(g1/Madd__old_z_4_Madd_cy<2>)
LUT4:I2->O
1 0.551 0.996 g1/Madd_z_lut<3>1 (w<3>)
LUT4:I1->O
1 0.551 0.801 Madd_out_xor<3>11 (out_3_OBUF)
OBUF:I->O
5.644
out_3_OBUF (out<3>)
---------------------------------------Total
15.690ns (9.220ns logic, 6.470ns route)
(58.8% logic, 41.2% route)
==================================================================
=======
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.24 secs
-->
Total memory usage is 274204 kilobytes
OUTPUT:
RESULT:
Thus the 2s compliment multiplier has been designed and verified successfully.
EX. NO.:
DATE :
SHIFT AND ADD MULTIPLIER
AIM:
To design a 4-bit shift and add multiplier using Xilinx and simulate it using Model
Sim.
ALGORITHM:
If one, then add the multiplicand with accumulator, then right shift the result bit by
one.
PROGRAM:
module shiftaccum(x,y,p);
input [3:0]x;
input [3:0]y;
reg [9:0] a;
output [9:0] p;
reg [9:0] p;
integer i;
always @(x or y or p )
begin
p[9:0]=10'b0;
for(i=0;i<4;i=i+1)
begin
if(y[i]==0)
begin
a[9:0]=4'b0;
p=p+(a[9:0]<<i);
end
else
begin
a[9:0]=x[3:0];
p=p+(a[9:0]<<i);
end
end
end
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : shiftaccum.ngr
Top Level Output File Name
: shiftaccum
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 18
Cell Usage :
# BELS
: 51
#
GND
:1
#
LUT2
:6
#
LUT3
:5
#
LUT4
: 16
#
MUXCY
:8
#
MUXF5
:5
#
XORCY
: 10
# IO Buffers
: 18
#
IBUF
:8
#
OBUF
: 10
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : 3s400pq208-5
Number of Slices:
16 out of 3584 0%
Number of 4 input LUTs:
27 out of 7168 0%
Number of IOs:
18
Number of bonded IOBs:
18 out of 141 12%
--------------------------Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 16.676ns
Timing Detail:
--------------
OUTPUT:
RESULT:
Thus the 4-bit shift and add multiplier has been designed and verified successfully.
EX. NO.:
DATE :
BOOTH MULTIPLIER
AIM:
To design a booths multiplier using Xilinx and to verify it in Model Sim.
ALGORITHM:
The partial products are obtained from the multiplier and multiplicand.
PROGRAM:
module multiplier(prod, busy, mc, mp, clk, start);
output [15:0] prod;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [7:0] sum, difference;
always @(posedge clk)
begin
if (start) begin
A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;
count <= 4'b0;
end
else begin
case ({Q[0], Q_1})
2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q};
endcase
count <= count + 1'b1;
end
end
alu adder (sum, A, M, 1'b0);
alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};
assign busy = (count < 8);
endmodule
//The following is an alu.
//It is an adder, but capable of subtraction:
//Recall that subtraction means adding the two's complement-//a - b = a + (-b) = a + (inverted b + 1)
//The 1 will be coming in as cin (carry-in)
module alu(out, a, b, cin);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : multiplier.ngr
Top Level Output File Name
: multiplier
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 35
Cell Usage :
# BELS
: 85
#
GND
:1
#
INV
:2
#
LUT2
: 18
#
LUT3
:8
#
LUT4
: 17
#
MUXCY
: 14
#
MUXF5
:8
#
VCC
:1
#
XORCY
: 16
# FlipFlops/Latches
: 28
#
FD
:7
#
FDE
:8
#
FDR
: 12
#
FDS
:1
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
: 34
#
IBUF
: 17
#
OBUF
: 17
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : xa3s400pqg208-4
Number of Slices:
28 out of 3584 0%
Number of Slice Flip Flops:
28 out of 7168 0%
Number of 4 input LUTs:
45 out of 7168 0%
Number of IOs:
35
Number of bonded IOBs:
35 out of 141 24%
Number of GCLKs:
1 out of
8 12%
--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
---------------------------
Speed Grade: -4
Minimum period: 6.605ns (Maximum Frequency: 151.400MHz)
Minimum input arrival time before clock: 5.236ns
Maximum output required time after clock: 8.593ns
Maximum combinational path delay: No path found
------------------------------------------------------------------------Delay:
6.605ns (Levels of Logic = 11)
Source:
M_0 (FF)
Destination:
A_6 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: M_0 to A_6
Gate Net
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 17 / 17
------------------------------------------------------------------------Offset:
8.593ns (Levels of Logic = 2)
Source:
count_3 (FF)
Destination:
busy (PAD)
Source Clock: clk rising
Data Path: count_3 to busy
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDR:C->Q
2 0.720 0.877 count_3 (count_3)
INV:I->O
1 0.551 0.801 busy1_INV_0 (busy_OBUF)
OBUF:I->O
5.644
busy_OBUF (busy)
---------------------------------------Total
8.593ns (6.915ns logic, 1.678ns route)
(80.5% logic, 19.5% route)
==================================================================
=======
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.61 secs
-->
Total memory usage is 217324 kilobytes
OUTPUT:
RESULT:
Thus the booths multiplier has been designed and verified successfully.
EX. NO.:
DATE :
8- BIT ALU
AIM:
To design a 8 bit ALU using Xilinx and simulate it using Model Sim.
ALGORITHM:
Declare the name of the entity and architecture by using VHDL source code.
Check the syntax and debug the errors if found, obtain the synthesis report.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALUDESIGN is
Port (inputa,inputb : in STD_LOGIC_vector(7 downto 0);
operation : in std_logic_vector(3 downto 0);
shiftvalue : in bit;
reset,clk : in std_logic;
output : out STD_LOGIC_vector(7 downto 0);
muloutput : out std_logic_vector(15 downto 0));
end ALUDESIGN;
architecture Behavioral of ALUDESIGN is
begin
process(reset,operation,clk)
variable temp,acc,reg_c,reg_b : std_logic_vector(7 downto 0):="00000000";
begin
if (reset = '1' ) then
acc :="00000000";
reg_b :="00000000";
elsif(reset = '0') then
acc := inputa;
reg_b := inputb;
if (operation = "0000") then
acc := acc + reg_b;
elsif (operation ="0001") then
acc := acc - reg_b;
elsif (operation ="0010") then --or
acc := acc or reg_b;
elsif (operation ="0011" ) then -- and
acc := acc and reg_b;
elsif (operation="0100") then -- Ex-or
acc :=((acc and(not reg_b))or(not(acc)and reg_b));
elsif (operation="0101") then --not
acc := not (acc);
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : ALUDESIGN.ngr
Top Level Output File Name
: ALUDESIGN
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 47
Cell Usage :
# BELS
: 111
#
GND
:1
#
LUT2
:1
#
LUT3
: 29
#
LUT4
: 54
#
MUXCY
:7
#
MUXF5
: 11
#
XORCY
:8
# FlipFlops/Latches
: 16
#
LDE_1
: 16
# Clock Buffers
:1
#
BUFG
:1
# IO Buffers
: 46
#
IBUF
: 22
#
OBUF
: 24
# MULTs
:1
#
MULT18X18SIO
:1
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : xa3s250epqg208-4
Number of Slices:
46 out of 2448 1%
Number of 4 input LUTs:
84 out of 4896 1%
Number of IOs:
47
Number of bonded IOBs:
46 out of 158 29%
IOB Flip Flops:
16
Number of MULT18X18SIOs:
1 out of 12 8%
Number of GCLKs:
1 out of 24 4%
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: 7.488ns
Maximum output required time after clock: 4.368ns
Maximum combinational path delay: 13.628ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
==================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'reset'
Total number of paths / destination ports: 264 / 32
------------------------------------------------------------------------Offset:
7.488ns (Levels of Logic = 2)
Source:
inputa<7> (PAD)
Destination:
muloutput_15 (LATCH)
Destination Clock: reset rising
Data Path: inputa<7> to muloutput_15
Gate Net
Total number of paths / destination ports: 16 / 16
------------------------------------------------------------------------Timing constraint: Default path analysis
Total number of paths / destination ports: 843 / 8
------------------------------------------------------------------------Delay:
13.628ns (Levels of Logic = 9)
Source:
operation<0> (PAD)
Destination:
output<3> (PAD)
Data Path: operation<0> to output<3>
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
23 1.218 1.281 operation_0_IBUF (operation_0_IBUF)
LUT3:I1->O
3 0.704 0.535 output_and000711 (N32)
LUT4:I3->O
1 0.704 0.000 output<1>2_G (N78)
MUXF5:I1->O
7 0.321 0.883 output<1>2 (N2)
LUT4:I0->O
1 0.704 0.424 output<3>36_SW0 (N43)
LUT4:I3->O
1 0.704 0.455 output<3>36 (output<3>36)
LUT4:I2->O
1 0.704 0.595 output<3>93_SW0 (N45)
LUT4:I0->O
1 0.704 0.420 output<3>93 (output_3_OBUF)
OBUF:I->O
3.272
output_3_OBUF (output<3>)
---------------------------------------Total
13.628ns (9.035ns logic, 4.593ns route)
(66.3% logic, 33.7% route)
==================================================================
=======
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.64 secs
-->
Total memory usage is 280860 kilobytes
OUTPUT:
RESULT:
Thus the 8-bit ALU has been designed and verified successfully.
EX. NO.:
DATE :
4-BIT SLICED ALU
AIM:
To design a 4-bit sliced processor using Xilinx and simulate it using ModelSim.
ALGORITHM:
Declare the name of the entity and architecture by using VHDL source code.
Check the syntax and debug the errors if found, obtain the synthesis report.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity s1 is
port(x,y:in std_logic_vector(7 downto 0);
clk: in std_logic;
start:in bit;
result:out std_logic_vector(7 downto 0);
mulout: out std_logic_vector(15 downto 0);
operation,functionload:in std_logic_vector(3 downto 0));
end s1 ;
architecture Behavioral of s1 is
signal carry1,carry2,borrow1,borrow2: std_logic;
signal accum1,accum2: std_logic_vector(3 downto 0);
signal Breg1,Breg2:std_logic_vector(3 downto 0);
signal m1,m2,i1,i2: std_logic_vector(7 downto 0);
signal opt: std_logic_vector(15 downto 0);
signal sum1,sum2:std_logic_vector(4 downto 0):="00000";
signal control1,control2:std_logic_vector(3 downto 0);
signal exe1,exe2,add,sub,b:bit :='0';
signal zout1:std_logic_vector(3 downto 0):="0000";
signal zout2:std_logic_vector(3 downto 0):="0000";
begin
p1:process(x,y,operation,functionload,start,clk)
begin
if(clk='1' and clk'event) then
if(start='1') then
exe1<='0';
if (operation="0000") then
control1<=functionload;
control2<=functionload;
elsif(operation="0001") then
accum1<=x(3 downto 0 );
Breg1<=y(3 downto 0);
accum2<=x(7 downto 4);
elsif(control1="1100") then
zout1<=Breg2(0) & Breg1(3 downto 1); --rotate right breg
elsif(control1="1101") then
sum1<=('0' & accum1) + ('0' & Breg1);
zout1<=sum1(3 downto 0);
carry1<=sum1(4);
add <='1';
elsif(control1="1110") then
if(accum1>=Breg1) then
zout1<=accum1 - Breg1;
borrow1<='0';
sub <='1';
elsif(accum1<Breg1) then
zout1<=accum1 - Breg1;
borrow1<='1';
sub <='1';
end if;
elsif(control1 = "1111") then
m1<=accum1*Breg1;
end if;
end if;
end if;
end process p2;
p3:process(accum2,Breg2,exe2,control2,borrow1,carry1,add,sub,clk)
variable k1,k2:std_logic_vector(15 downto 0);
begin
if(clk='1' and clk'event) then
if(exe2='1') then
if(control2="0000") then
zout2<=accum2 or Breg2;
elsif(control2="0001") then
zout2<=accum2 and Breg2;
elsif(control2="0010") then
zout2<=accum2 nor Breg2;
elsif(control2="0011") then
zout2<=accum2 nand Breg2;
elsif(control2="0100") then
zout2<=accum2 xor Breg2;
elsif(control2="0101") then
zout2<=not accum2 ;
elsif(control2="0110") then
zout2<=not Breg2;
elsif(control2="0111") then
zout2<='0' & accum2(3 downto 1);
elsif(control2="1000") then
zout2<='0' & Breg2(3 downto 1);
elsif(control2="1001") then
zout2<=accum2(2 downto 0) & accum1(3);
elsif(control2="1010") then
zout2<=Breg2(2 downto 0) & Breg1(3);
elsif(control2="1011") then
zout2<=accum2(2 downto 0) & accum1(3) ;
elsif(control2="1100") then
zout2<=Breg1(0) & Breg2(3 downto 1);
elsif(control2="1101" and add='1') then
sum2<=('0' & accum2) + ('0' & Breg2)+ carry1;
zout2<=sum2(3 downto 0);
carry2<=sum2(4);
elsif(control2="1110") then
if(accum2>=Breg2 and sub ='1') then
zout2<=accum2 - Breg2- borrow1;
borrow2<='0';
elsif(accum2<Breg2 and sub ='1') then
zout2<=Breg2 - accum2 - borrow1;
borrow2<='1';
end if;
elsif(control2 = "1111") then
m2 <=accum2 * Breg2;
i1<=accum1 * Breg2;
i2<=accum2 * Breg1;
k1:="0000"&i1(7 downto 0)&"0000";
k2:="0000"&i2(7 downto 0)&"0000";
opt<=(m2 & m1)+ k1+k2;
end if;
end if;
end if;
end process p3;
end Behavioral;
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : s1.ngr
Top Level Output File Name
: s1
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 50
Cell Usage :
# BELS
: 224
#
GND
:1
#
INV
:1
#
LUT1
:2
#
LUT2
: 10
#
LUT3
: 41
#
LUT3_D
:2
#
LUT3_L
:2
#
LUT4
: 91
#
LUT4_D
:8
#
LUT4_L
:7
#
MUXCY
: 16
#
MUXF5
: 20
#
MUXF6
:2
#
MUXF7
:1
#
VCC
:1
#
XORCY
: 19
# FlipFlops/Latches
: 82
#
FDE
: 82
# Shift Registers
:1
#
SRL16E
:1
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
: 49
#
IBUF
: 25
#
OBUF
: 24
# MULTs
:4
#
MULT18X18S
:4
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : 3s400pq208-5
Number of Slices:
91 out of 3584 2%
Number of Slice Flip Flops:
82 out of 7168 1%
------------------------------------------------------------------------Delay:
8.192ns (Levels of Logic = 9)
Source:
accum2_1 (FF)
Destination:
zout2_3 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: accum2_1 to zout2_3
Gate Net
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 250 / 67
------------------------------------------------------------------------Offset:
5.839ns (Levels of Logic = 3)
Source:
start (PAD)
Destination:
result_0 (FF)
Destination Clock: clk rising
Data Path: start to result_0
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
2 0.715 1.040 start_IBUF (start_IBUF)
LUT3:I0->O
4 0.479 1.074 accum1_not000111 (N29)
LUT3:I0->O
24 0.479 1.527 mulout_not00011 (mulout_not0001)
FDE:CE
0.524
result_0
---------------------------------------Total
5.839ns (2.197ns logic, 3.642ns route)
(37.6% logic, 62.4% route)
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 24 / 24
------------------------------------------------------------------------Offset:
6.216ns (Levels of Logic = 1)
Source:
mulout_15 (FF)
Destination:
mulout<15> (PAD)
Source Clock: clk rising
Data Path: mulout_15 to mulout<15>
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDE:C->Q
1 0.626 0.681 mulout_15 (mulout_15)
OBUF:I->O
4.909
mulout_15_OBUF (mulout<15>)
---------------------------------------Total
6.216ns (5.535ns logic, 0.681ns route)
(89.0% logic, 11.0% route)
Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 10.73 secs
-->
Total memory usage is 251368 kilobytes
OUTPUT:
RESULT:
Thus the 4-bit sliced processor has been designed and verified successfully.
EX. NO.:
DATE :
SYSTEM DESIGN USING PLL
AIM:
To design and implement a system using Phase Locked Loop (PLL) using Xilinx and
simulate it using Model Sim.
ALGORITHM:
Declare the name of the entity and architecture by using VHDL source code.
Check the syntax and debug the errors if found, obtain the synthesis report.
PROGRAM:
module phase(u1,u2,id_clk,reset);
input u1,id_clk,reset;
output u2;
parameter m=32;
parameter k=8;
parameter n=16;
parameter PHASE_DETECTOR_SELECT=1;
parameter m2=5;
parameter k2=3;
parameter n2=4;
wire reset,xor_out,jk_out,dn_up,k_clk,u2,u2_prime;
reg[(k2-1):0]kup,kdn;
reg carry_new,borrow,toggle_ff,carry_pulse,borrow_pulse,advanced,delayed;
reg id_out,id_out_2,id_out_4,id_out_8,id_out_16;
reg borrow_new,carry;
assign k_clk=id_clk;
jk jk1(q,j,k_clk);
assign xor_out=u1^u2_prime;
assign dn_up=PHASE_DETECTOR_SELECT?xor_out:jk_out;
//********KCOUNTER*****/////////
always@(negedge k_clk or negedge reset)
begin
if(!reset)
begin
kup<=0;
kdn<=0;
carry<=0;
borrow<=0;
end
else
begin
if(dn_up)kdn<=kdn+1;
else
begin
if(dn_up)kdn<=kdn+1;
carry<=kup[k2-1];
borrow<=kdn[k2-1];
end
end
end
///*****ID COUNTER***////////
always @(posedge id_clk)
begin
if(!carry)
begin
carry_new<=1;
carry_pulse<=0;
end
else if(carry_pulse)
begin
carry_pulse<=0;
carry_new<=0;
end
else if(carry && carry_new)
begin
carry_pulse<=1;
carry_new<=0;
end
else
begin
carry_pulse<=0;
carry_new<=0;
end
end
always@(posedge id_clk)
begin
if(!borrow)
begin
borrow_new<=1;
borrow_pulse<=0;
end
else if(borrow_pulse)
begin
borrow_pulse<=0;
borrow_new<=0;
end
else if(borrow && borrow_new)
begin
borrow_pulse<=1;
borrow_new<=0;
end
else
begin
borrow_pulse<=0;
borrow_new<=0;
end
end
always@(posedge id_clk or negedge reset)
begin
if(!reset)
begin
toggle_ff<=0;
delayed<=1;
advanced<=1;
end
else
begin
if(carry_pulse)
begin
advanced<=1;
toggle_ff<=!toggle_ff;
end
else if(borrow_pulse)
begin
delayed<=1;
toggle_ff<=!toggle_ff;
end
else if(toggle_ff==0)
begin
if(!advanced)toggle_ff<=!toggle_ff;
else if(advanced)
begin
toggle_ff<=toggle_ff;
advanced<=0;
end
end
else
begin
if(!delayed)toggle_ff<=!toggle_ff;
else if(delayed)
begin
toggle_ff<=toggle_ff;
delayed<=0;
end
end
end
end
always@(id_clk or toggle_ff)
begin
if(toggle_ff)id_out<=0;
else
begin
if(id_clk)id_out<=0;
else id_out<=1;
end
end
assign u2=id_out;
always@(negedge id_out or negedge reset)
begin
if(!reset)id_out_2<=0;
else
id_out_2<=!id_out_2;
end
always@(negedge id_out_2 or negedge reset)
begin
if(!reset)id_out_4<=0;
else id_out_4<=!id_out_4;
end
always@(negedge id_out_4 or negedge reset)
begin
if(!reset)id_out_8<=0;
else id_out_8<=!id_out_8;
end
always @(negedge id_out_8 or negedge reset)
begin
if(!reset)id_out_16<=0;
else id_out_16<=id_out_16;
end
assign u2_prime=id_out_8;
endmodule
//////////
module jk(q,j,k);
input j,k;
output q;
reg q;
always@(posedge j)
begin
if(k==1)
q<=!q;
else q<=1;
end
always@(posedge k)
begin
if(j==1)
q<=!q;
else
q<=0;
end
endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
==================================================================
*
Final Report
*
==================================================================
Final Results
RTL Top Level Output File Name : phase.ngr
Top Level Output File Name
: phase
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:4
Cell Usage :
# BELS
: 19
#
INV
:7
#
LUT2
:4
#
LUT3
:4
#
LUT4
:2
#
MUXF5
:1
#
VCC
:1
# FlipFlops/Latches
: 13
#
FDC_1
:3
#
FDCE
:4
#
FDCE_1
:1
#
FDPE
:2
#
FDR
:3
# Clock Buffers
:1
#
BUFG
:1
# IO Buffers
:4
#
IBUF
:3
#
OBUF
:1
==================================================================
=======
Device utilization summary:
--------------------------Selected Device : 3s400pq208-5
Number of Slices:
8 out of 3584 0%
Number of Slice Flip Flops:
13 out of 7168 0%
Number of 4 input LUTs:
17 out of 7168 0%
Number of IOs:
4
Number of bonded IOBs:
4 out of 141 2%
Number of GCLKs:
1 out of
8 12%
Timing Summary:
--------------Speed Grade: -5
Minimum period: 6.965ns (Maximum Frequency: 143.583MHz)
Minimum input arrival time before clock: 3.529ns
Maximum output required time after clock: 7.837ns
Maximum combinational path delay: 7.764ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
==================================================================
=======
Timing constraint: Default period analysis for Clock 'id_clk'
Clock period: 6.965ns (frequency: 143.583MHz)
Total number of paths / destination ports: 29 / 12
------------------------------------------------------------------------Delay:
3.482ns (Levels of Logic = 1)
Source:
borrow (FF)
Destination:
borrow_pulse (FF)
Source Clock: id_clk falling
Destination Clock: id_clk rising
Data Path: borrow to borrow_pulse
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDCE_1:C->Q
2 0.626 0.804 borrow (borrow)
LUT3:I2->O
1 0.479 0.681 borrow_pulse_or00001 (borrow_pulse_or0000)
FDR:R
0.892
borrow_pulse
---------------------------------------Total
3.482ns (1.997ns logic, 1.485ns route)
(57.3% logic, 42.7% route)
==================================================================
=======
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Delay:
7.764ns (Levels of Logic = 3)
Source:
id_clk (PAD)
Destination:
u2 (PAD)
Data Path: id_clk to u2
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
2 0.715 0.915 id_clk_IBUF (id_clk_IBUF1)
LUT2:I1->O
2 0.479 0.745 id_out1 (u2_OBUF)
OBUF:I->O
4.909
u2_OBUF (u2)
---------------------------------------Total
7.764ns (6.103ns logic, 1.661ns route)
(78.6% logic, 21.4% route)
==================================================================
=======
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.35 secs
-->
Total memory usage is 273884 kilobytes
OUTPUT:
RESULT:
Thus the system was designed using Phase Locked Loop (PLL) using the Modelsim
was verified.
EX. NO:
DATE :
LIQUID CRYSTAL DISPLAY
AIM:
To implement LCD using PIC 16F877 embedded microcontroller.
DESIGN TOOL:
PIC ISP
ALGORITHM:
PROGRAM:
//----------------------------------------------------//
//THIS PROGRAM FOR DISPLAY THE STRING VIA CHARACTER
//BASED LCD
//----------------------------------------------------//
#include<16F877.h>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
void busycheck();
unsigned int array[19]={"Vi Microsystems"};
unsigned char a,i,b;
void main()
{
output_low(PIN_B3);
output_high(PIN_B1);
busycheck();
output_d(0x38);
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x06);
/* function set */
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x01);
/* clear display */
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x0f);
/* cursor on */
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x80);
/* starting address */
output_high(PIN_B3);
output_low(PIN_B3);
for (i=0;i<15;i++)
{
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);
b=array[i];
output_d(b);
output_high(PIN_B3);
output_low(PIN_B3);
}
stop:
goto stop;
}
void busycheck()
{
output_d(0x02);
output_low(PIN_B1);
output_high(PIN_B1);
delay_ms(2);
busy:
output_high(PIN_B3);
output_low(PIN_B3);
a=input_d();
if ((a&0x80)==0x80)
goto busy;
output_d(0x0);
output_low(PIN_B1);
output_high(PIN_B1);
delay_us(10);
}
RESULT:
Thus the implementation of LCD has been done successfully using PIC
microcontroller 16F877.
EX. NO:
DATE :
LIGHT EMITTING DIODE
AIM:
To implement LED using PIC 16F877 embedded microcontroller.
DESIGN TOOL:
PIC ISP
ALGORITHM:
PROGRAM:
//This Program For LED interface
//Data Lines - PORTD
//Latch Line - PB4
#include<16f877.h>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
unsigned int led[]={0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80},i;
void main()
{
output_b(0xff);
while(1)
{
for(i=0;i<5;i++){
output_d(0xff);
output_low(PIN_B4);
output_high(PIN_B4);
delay_ms(500);
output_d(0x0);
output_low(PIN_B4);
output_high(PIN_B4);
delay_ms(500);
}
for(i=0;i<8;i++)
{
output_d(led[i]);
output_low(PIN_B4);
output_high(PIN_B4);
delay_ms(500);
}
}
}
RESULT:
Thus the implementation of LED has been done successfully using PIC
microcontroller 16F877.
EX. NO.:
DATE :
ELEVATOR CONTROLLER
AIM:
To implement an elevator controller using PIC 16F877 embedded microcontroller.
DESIGN TOOL:
PIC ISP
ALGORITHM:
The DC motor which is used to drive the elevator is served both by a limit
switch and optical encoder.
The controller is also used to control lights for the elevator following toggle
ON/OFF functions for each push button.
The indicator lights are automatically lit when the elevator arrives at a
chosen floor.
All light are ON on auto shut-off timer which conserves power is used.
PROGRAM:
#include<16f877.h>
#include<stdio.h>
#use delay(clock=20000000)
#use rs232(baud=19200,xmit=pin_c6,rcv=pin_c7)
if(G==0x02)
{
for(i=2;i>=1;i--)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0x03)
{
for(i=4;i>=1;i--)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X04)
{
for(i=6;i>=1;i--)
FLOOR
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
for(j=0;j<=0x03;j++);
{
OUTPUT_HIGH(PIN_B1);
delay_ms(300);
OUTPUT_LOW(PIN_B1);
delay_ms(300);
OUTPUT_HIGH(PIN_B1);
}
G=1;
}
void first_floor()
{
unsigned int i,j;
OUTPUT_LOW(PIN_B0);
if(G==1||G==00)
{
for(i=2;i<=3;i++)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X03)
{
for(i=4;i>=3;i--)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X04)
{
for(i=6;i>=3;i--)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
for(j=0;j<=0x03;j++);
{
OUTPUT_HIGH(PIN_B3);
delay_ms(300);
OUTPUT_LOW(PIN_B3);
delay_ms(300);
OUTPUT_HIGH(PIN_B3);
}
G=2;
}
void second_floor()
{
unsigned int I,j;
OUTPUT_LOW(PIN_b0);
if(G==0X01 || G == 00)
{
for(i=2;i<=5;i++)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X02)
{
for(i=4;i<=5;i++)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X04)
{
for(i=6;i>=5;i--)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
for(j=0;j<=0X03;j++)
{
OUTPUT_HIGH(PIN_B5);
delay_ms(300);
OUTPUT_LOW(PIN_B5);
delay_ms(300);
OUTPUT_HIGH(PIN_B5);
}
G=3;
}
void third_floor()
{
unsigned int i,j;
OUTPUT_LOW(PIN_B0);
if(G==0X01 || G==00)
{
for(i=1;i<=7;i++)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X02)
{
for(i=4;i<=7;i++)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
if(G==0X03)
{
for(i=6;i<=7;i++)
{
OUTPUT_B(a[i]);
delay_ms(500);
}
}
else
{
OUTPUT_B(0X80);
delay_ms(500);
}
for(j=0;j<=0X03;j++)
{
OUTPUT_HIGH(PIN_B7);
delay_ms(300);
OUTPUT_LOW(PIN_B7);
delay_ms(300);
OUTPUT_HIGH(PIN_B7);
}
G=4;}
RESULT:
Thus the implementation of Elevator controller has been done successfully using
PIC microcontroller 16F877.
EX. NO.:
DATE :
REAL TIME CLOCK
AIM:
To implement a real time clock using PIC 16F877 embedded microcontroller.
DESIGN TOOL:
PIC ISP
PROGRAM:
#include <16F877.H>
#include<string.h>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
#use I2C(MASTER,sda=PIN_C4,scl=PIN_C3)
unsigned int time[]={0x55,0x59,0x11};
unsigned int readtime[0x03];
unsigned char array2[];
unsigned char array3[19]="REAL TIME CLOCK";
unsigned long int hour,second,minute;
int i,j;
void busycheck()
{
unsigned char a;
output_d(0x02);
output_low(PIN_B1);
output_high(PIN_B1);
delay_ms(2);
busy:
output_high(PIN_B3);
output_low(PIN_B3);
a=input_d();
if ((a&0x80)==0x80)
goto busy;
output_d(0x0);
output_low(PIN_B1);
output_high(PIN_B1);
delay_us(10);
}
void set_rtc_time()
{
for (i=2;i<=4;i++)
{
i2c_start();
i2c_write(0xa0 | 0x00);
i2c_write(i);
i2c_write(time[(i-2)]);
i2c_stop();
}
}
void get_rtc_time()
{
for (i=2;i<=4;i++)
{
i2c_start();
i2c_write(0xa0);
i2c_write(i);
i2c_start();
i2c_write(0xa0 | 0x01);
readtime[(i-2)]=i2c_read(0);
i2c_stop();
}
}
void lcd_int()
{
output_low(PIN_B3);
output_high(PIN_B1);
busycheck();
output_d(0x38);
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x06);
/* function set */
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x01);
/* clear display */
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x0c);
/* cursor on */
output_high(PIN_B3);
output_low(PIN_B3);
l = strlen(array1);
for (i=0;i<l;i++)
{
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);
b=array1[i];
output_d(b);
output_high(PIN_B3);
output_low(PIN_B3);
}
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);
output_d(ch);
output_high(PIN_B3);
output_low(PIN_B3);
void alarm_set()
{
output_b(0xff);
if(hour==0x12)
if(minute==0x00)
{
if((second>=0x00)&&(second<=0x05))
{
output_high(PIN_B0);
delay_ms(10);
output_low(PIN_B0);
delay_ms(10);
}
}
}
void main()
{
unsigned int i;
lcd_int();
set_rtc_time();
while(1)
{
get_rtc_time();
hour = readtime[2];
minute= readtime[1];
second=readtime[0];
printf(" Time : %x : %x : %x \n\r",readtime[2],readtime[1],readtime[0]);
sprintf(array2,"%x : %x : %x",readtime[2],readtime[1],readtime[0]);
lcd_display(array3,0x82);
lcd_display(array2,0x98);
alarm_set();
delay_us(500);
}
}
RESULT:
Thus the implementation of real time clock has been done successfully using PIC
microcontroller 16F877.
EX. NO.:
DATE :
MODEL TRAIN CONTROLLER
AIM:
To design and implement a model train controller using PIC 16F877 embedded micro
controller.
DESIGN TOOLS:
HARDWARE REQUIRED:
PIC 16F877
ALGORITHM:
PROGRAM:
#include<16F877.H>
//#include<support.h>
#use delay(clock=20000000)
#use rs232(baud=19200,xmit=PIN_C6, rcv=PIN_C7)
#use i2c(MASTER,sda=PIN_C4,scl=PIN_C3)
unsigned char data,a,b,c;
unsigned char ls0[]={0x55,0x54,0x50,0x40,0x00,0x00,0x01,0x05,0x15,0x55};
//led0-led3 selector for forward direction.
unsigned char ls1[]={0x55,0x15,0x05,0x01,0x00,0x00,0x40,0x50,0x54,0x55};
//led0-led3 selector for reverse direction.
/*
0x55
0x54
0x50
0x40
0x00
*/
//unsigned char ls1[]={0x00,0x01,0x05,0x15,0x55};
/*
0x00
0x01
0x05
0x15
0x55
*/
unsigned char sel[]={0x00,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce,0x0c0};
/*
THESE LINES ARE CONNECTE TO U9.
PULSE PIN IS REI
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
*/
/*
0x02
0x04
0x08
*/
unsigned char i,i1,j,k=0*15,senout=0x00,senout1=0x00,senout2,senout3;
void crossingon();
void crossingoff();
void init();
void initbuf();
void sensor();
void sensor1();
void station1forward();
void station2forward();
void station1reverse();
void station2reverse();
void sw();
void sw1();
void reverse();
void forward();
void main()
{
init();
initbuf();
output_high(PIN_E0);
while(1)
{
start1:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start:
if(i<0x04)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k);
goto start1;
sw();
if((b!=0x0))
goto start;
if(i>=0x05)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k+1);
i2c_write(ls0[i-0x04]);
i2c_stop();
i2c_start();
i2c_write(sel[j+1]);
i2c_write(k);
i2c_write(ls0[i-0x04]);
i1++;
}
i2c_stop();
sw();
if((b!=0x0))
goto start;
sensor();
if(senout==0x00)
goto stop1;
senout++;
if(senout<0x05)
delay_ms(200);
else if(senout==0x05)
{
delay_ms(0x2000);
output_d(0x10);
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(1000);
output_d(0x08);
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(100);
}
if((senout>0x05)&&(senout<=0x09))
delay_ms(200);
stop1:
if(senout1==0x00)
goto stop2;
senout1++;
if(senout<0x05)
delay_ms(200);
else if (senout1==0x05)
{
delay_ms(0x2000);
output_d(0x04);
output_low(PIN_E2);
output_high(PIN_E2);
delay_ms(1000);
output_d(0x02);
output_high(PIN_E2);
output_low(PIN_E2);
delay_ms(100);
}
if((senout1>0x05)&&(senout1<=0x09))
delay_ms(200);
stop2:
if(i!=0x08)
delay_ms(200);
}
}
}
}
void init()
{
for(i=0;i<0x08;i++)
{
i2c_start();
i2c_write(sel[i]);
i2c_write(0x15);
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
}
}
void sensor()
{
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x04;
if(b!=0x04)
{
Output_d(0x0);
Output_low(PIN_E1);
Output_high(PIN_E1);
Crossingon();
}
b=a;
b=b&0x08;
If(b!=0x08)
//Crossing
Crossingoff();
b=a;
b=b&0x10;
If(b!=0x10)
Station2forward();
b=a;
b=b&0x01;
if(b!=0x01)
station1forward();
}
void Crossingon()
{
Output_d(0xF0);
Output_low(PIN_E2);
Output_high(PIN_E2);
Output_d(0xFF);
Output_low(PIN_B1);
Output_high(PIN_B1);
Output_low(PIN_E0);
}
void Crossingoff()
{
Output_d(0x00);
Output_low(PIN_E2);
Output_high(PIN_E2);
Output_d(0x00);
Output_low(PIN_B1);
Output_high(PIN_B1);
Output_high(PIN_E0);
}
void station1forward()
{
output_d(0x00);
output_low(PIN_E2);
output_high(PIN_E2);
output_d(0x20);
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x01;
if(b==0x01)
senout=0x01;
}
void station2forward()
{
output_d(0x08);
output_low(PIN_E2);
output_high(PIN_E2);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x10;
if(b==0x10)
senout1=0x01;
}
void sw()
{
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x40;
c=a;
c=c&0x80;
if((b==0x0)&&(c==0x80))
reverse();
}
void reverse()
{
init();
initbuf();
while(1)
{
start3:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start4:
if(i<0x04)
{
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x06);
i2c_write(ls1[i]);
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x05);
i2c_write(ls1[i1]);
i1++;
}
if(j==0x08)
goto start3;
sw1();
if((b!=0x0))
goto start4;
if(i>=0x05)
{
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x05);
i2c_write(ls1[i-0x04]);
i2c_stop();
i2c_start();
i2c_write(sel1[j+1]);
i2c_write(0x06);
i2c_write(ls1[i1-0x04]);
i1++;
}
sw1();
if((b!=0x0))
goto start4;
sensor1();
senout2++;
if(senout2<0x05)
delay_ms(200);
else if(senout2==0x05)
//reverse direction
{
delay_ms(0x2000);
{
delay_ms(0x2000);
//station 1
initbuf();
output_d(0x02);
//for station1 in reverse
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(1000);
initbuf();
output_d(0x01);
//for station1 in reverse
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(100);
}
if((senout3>0x05)&&(senout3<=0x09))
delay_ms(200);
if(i!=0x08)
delay_ms(200);
}
}
}
}
void sensor1()
{
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x20;
if(b!=0x20)
{
output_d(0x00);
output_low(PIN_E1);
output_high(PIN_E1);
station2reverse();
}
b=a;
b=b&0x04;
if(b!=0x0a)
crossingoff();
b=a;
b=b&0x08;
if(b!=0x08)
crossingon();
b=a;b=b&0x02;
if(b!=0x02)
station1reverse();
}
void station1reverse()
{
initbuf();
output_d(0x04);
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x02;
if(b==0x02)
senout3=0x01;
}
void station2reverse()
{
initbuf();
output_d(0x01);
output_low(PIN_E2);
output_high(PIN_E2);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x20;
if(b==0x20)
senout2=0x01;
}
void sw1()
{
output_low(PIN_B4);
a=input_d();
output_high(PIN_B4);
b=a;
b=b&0x40;
c=a;
c=c&0x80;
}
void initbuf()
{
output_d(0x00);
output_low(PIN_E1);
output_high(PIN_E1);
output_d(0x00);
output_low(PIN_E2);
output_high(PIN_E2);
output_d(0x00);
output_low(PIN_B1);
output_high(PIN_B1);
}
RESULT:
Thus the implementation of model train controller has been successfully done
using PIC microcontroller 16F877.