Digital System Design using Verilog

(DSD)
Even semester 2016

Course Overview
Module1

Module2

Module3

Design styles: Full-custom, semicustom

ASICs, FPGA & CPLDs -> Altera, Xilinx and Actel logic modules
Programmable IO cells, ASIC design flow, Logic synthesis

Testing combinational circuit fault models, Booloean difference

method, path sensitization method, D-Algorithm, PODEM etc.,
Testing Sequential circuits
Design for Test (DFT) and Y chart

Introduction to HDL, Verilog Vs VHDL

Verilog description for Comb. Circuits
Delays, data types, operators etc.,
System level design: Real world examples such as ALU, UART etc.,

Reference Text Books

[1] M.J.S.Smith (1997), Application Specific ICs, Addison

Wesley.

[2] Charles Roth, Lizy Kurian John, Byeongkil Lee, Digital System
Design using Verilog, (1e), 2016.
[3] Michael D. Ciletti, Advanced Digital Design with the Verilog
HDL, (2e), prentice hall publishing 2010.
[4]. Stephen, Brown and Zvonko Vranesic, Fundamentals of Digital
Logic with Verilog Design, TMH, 2013.
[5]. Parag K. Lala, Fault tolerant and Fault testable Hardware
Design, BS publication 1990.

Prerequisite: Digital Logic Design

Recommended Books

For FPGAs:

Application Specific ICs by M.J.S.Smith(1997), Addison

Wesley, Pearson education.

For Testing:

An Introduction to Logic circuit testing, by Parag K Lala,

Morgan & claypool publishers

Parag K. Lala, Fault tolerant and Fault testable Hardware

Design, BS publication 1990

For VHDL:

Fundamentals of Digital Logic with Verilog Design, by

Stephen, Brown and Zvonko Vranesic, TMH, 2013.

Introduction
The first electronic computer

Intel 4004 Microprocessor

Intel core 2 Microprocessor

Intel, 1971.

Intel, 2006.

2,300 transistors

291,000,000 transistors

740 KHz operation

3 GHz operation

(10m PMOS technology)

(65nm CMOS technology)

Moores Law

In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every 18 to 24
months.
He made a prediction that semiconductor
technology will double its effectiveness every 18
months

Moores Law

Technology generation

Basic programmable logic

Programmable Logic Devices (PLDs)

Definition: A Programmable Logic Device (PLD) is a chip that is

manufactured with a programmable configuration, enabling it to
serve in many arbitrary applications.

M N P PLD

PLDs are ICs whose ultimate function is determined by the designer;

they leave the manufacturer in an un-programmed state.

Programmable Logic Devices (PLDs)

Types of the ANDOR structured programmable logic devices are

1. Programmable read-only memory (PROM)

2. Programmable logic array (PLA)

3. Programmable array logic (PAL)

PLD Notation
Programmable (fig. a to f)
Fixed(Fig. g and h)

Programmable Read Only Memory

Programmable Logic Array (PLA)

Programmable Logic Array

Advantage

1. Logic function is implemented with minimum hardware.

2. Comparatively less power dissipation.

Disadvantage

1. We have two degree of freedom i.e. AND plane and OR

plane both are programmable therefore it is difficult to
program.

Programmable Array Logic (PAL)

Programmable Array Logic (PAL)

Advantage

1. The OR array is fixed and hence it is easy to program.

2. Less expensive.

3. Speed is high in PAL than PLA

Disadvantage

1. Common product term can not be used more than once.

PAL outputs

Output from Basic PAL can be taken through any

of the following

1. OR gate

2. NOR gate

3. EXOR gate

4. EXNOR gate

5. Registered output

6. Registered output with enable

7. Programmable Input/output

Simple PLDs (SPLD)

Devices

PAL22V10

Manufacturers

Atmel

PAL22V10

PAL22V10 Macro cell

Applications of SPLD

Glue Logic

Counter

FSM

Wide decoding is not required for many

applications
Less FFs

More about ICs

Why Integrated circuits?

Integration of a large function of large no of logic devices on
a single chip provides the following advantage

Less area or increased volume, and therefore

compactness.

Less power consumption.

Less testing requirement at the system level.

Higher reliability mainly due to improved on chip

interconnection.

Higher speed due to significant reduced interconnection

length.

Significant cost saving.

ICs may be categorized as standard, custom or

semicustom.

Standard ICs have their architecture and function

defined by the user for a specific function.

Custom ICs are those which are fully defined by the

user for a specific function

Semicustom, or application-specific, ICs (ASICs) have

a standard circuit framework or set of cells which are
wired in a pattern defined by the user to suit
application.
Programmable logic fits into the semicustom category

Types of ICs

Standard ICs

Some digital ICs and their analog counter parts

(Analog/digital converters, for example) are standard
parts or standard Ics

Systems manufacturers and designers can use the same

standard part in a variety of different microelectronic
systems.

Custom ICS
Application Specific IC (ASIC)

1.Full Custom ICs

1. Full Custom ICs

It includes all logic cells that are customized and all mask layers
that are customized.

The designer abandons the approach of using pretested and precharacterized cells for all or part of that design.

This approach will take only if

There is no suitable existing cell libraries

Existing cell libraries are not fast enough, not small enough,
consumes too much power
ASIC technology is new or so specialized that there are no
existing cell libraries

1.Full Custom ICs

Full Custom ICs

Full custom ICs are most expensive to manufacture and to

design.

The time takes just make an IC (not including design time) is

typically eight weeks.

2.Semi Custom ICs : Non-programmable

2.1 Standard Cell Based ASICs

A Cell-based ASIC (CBIC) uses predesigned logic cells (AND

gates, OR gates, multiplexers, and flip-flops for example) known
as standard cells.

The standard cell areas (also called flexible blocks) in a CBIC

are built of rows of standard cells like a wall built of bricks.

Standard cells may be used in combination with larger

predesigned cells called Mega cells.

Mega cells are also called mega functions, full custom blocks,
System level macros (SLMs), fixed blocks, cores , functional
standard blocks (FSBs)

2.Semi Custom ICs : Non-programmable

Standard Cell Based ASICs

2.Semi Custom ICs : Non-programmable

Standard Cell Based ASICs

The ASIC designer defines only the placement of the standard

cells and the interconnect in a CBIC

However the standard cells can be placed anywhere in the silicon

Advantages

Save time, money

Reduce risk by using a Predesigned, pretested and Precharacterized cell library.

Disadvantages

The time or expense of designing or buying the standard cell

library

Time needed to fabricate all layers of the ASIC for each new
design.

2.Semi Custom ICs : Non-programmable

Important features of Standard Cell Based ASICs

All mask layers are customized transistors and interconnect

Custom blocks can be embedded

Manufacturing lead time is about 8 weeks

2.Semi Custom ICs : Non-programmable

2.2 Gate Array(GA or MGA) based ASIC

In a MGA based ASIC the transistors are predefined on the

silicon wafer

The predefined transistors on a gate array is the base array, and

the smallest element that is replicated to make the base array is
the base cell

Types of MGA

2.2.1 Channeled gate arrays

2.2.2 Channel less gate arrays

2.2.3 Structured gate arrays

2.Semi Custom ICs : Non-programmable

2.2.1 Channeled Gate array

Features

Only the interconnect is customized

The interconnect uses predefined spaces between rows of
base cells
Manufacturing lead time is between two days and two weeks

A channeled gate array is similar to CBIC both uses rows

of cells separated by channels used for interconnect. One
difference is that the space for interconnect between rows
of cells are fixed in height in a channeled gate array, where
as space between rows of cells may be adjusted in CBIC

2.Semi Custom ICs : Non-programmable

Channeled Gate array

2.Semi Custom ICs : Non-programmable

2.2.2 Channel less Gate array

Features

Only some (top few) mask layers are customized the

interconnect
Manufacturing lead time is between two days and two weeks

2.Semi Custom ICs : Non-programmable

Channel less Gate array

2.Semi Custom ICs : Non-programmable

2.2.3 Structured Gate Array

An embedded Gate array or structured gate array

combines some of the features of the CBICs and MGAs

Features

Only the interconnect is customized

Custom blocks(the same for each design) can be embedded

Manufacturing lead time is between two days and two weeks

2.Semi Custom ICs : Non-programmable

Structured gate array

3.Semi Custom ICs : Programmable

3.1 PLDs

Features

No customized mask layers or logic cells

Fast design turnaround

A single large block of programmable interconnect

A matrix of logic macrocells that usually consist of

programmable array logic followed by a flipflop or a latch

3.1 PLDs

3.2 FPGAs

There is a very little difference between an FPGA and PLD, an

FPGA is usually just larger and more complex than a PLD.

Features

None of the mask layers are customized

A method of programming the basic logic cells and the
interconnect
The core is a regular array of programmable basic logic cells
that can implement combinational as well as sequential logic
(flipflops)
A matrix of programmable interconnect surrounds the basic
logic cells

Programmable I/O cells surround the core

Design turn around is few hours

3.2 FPGAs

Advanced PLDs

Simple PLDs (SPLD)

Devices

PAL22V10

Manufacturers

Atmel

PAL22V10

PAL22V10 Macro cell

Complex PLD (CPLD)

Not a big SPLD, as the SPLD already has wide

product terms.
What is sensible
is multiple
SPLDs
interconnected, such that blocks of a medium sized
design can fit into these SPLD blocks.

CPLD manufacturers

Xilinx

Altera

Max3000A, Max7000S, Max II, Max V

Atmel

XC9500XL, CoolRunner-II

ATF15xx

Lattice Semiconductors

ispMACH4000ZE

MAX 7000 CPLD

CPLD Applications

Small design comprising of counters, FSM, small

logic
Examples

Memory controllers (DRAM controller)

Bus protocol translation (CPU bus PCI bus)

Optical encoders

Small control circuit in Instrumentation, power

electronics for Data Acquisition control, Small digital
control circuits

CPLD Applications

Designs which require lot of registers and memory

and complex designs cannot be implemented.

Signal processing architectures (Filters)

Complex arithmetic circuits

Communication circuits (Packet processing, Modems)

CODECs

Cryptographic circuits

Field Programmable Gate Array (FPGA)

Array of logic resources with programmable

interconnection

Logic resources (combinational, Flip flops)

Combinational: LUT, multiplexers, Gates

Programmable Interconnections: SRAM, Flash,

Anti-fuse
Special resources: PLL, RAMS, FIFOs
Memory Controllers, Network interfaces,
Processors

Commercial FPGAs

Xilinx

Spartan-3, Spartan-6

Virtex-4, Virtex-5, Virtex-6

Artix-7, Kintex-7, Virtex-7, Zynq

Altera

Cyclone, Cyclone II, Cyclone III, Cyclone IV,

Cyclone V

Arria II, Arria V

Stratix II, Stratix III, Stratix IV, Stratix V

Commercial FPGAs

Actel

Axcelerator (Anti-fuse)

IGLOO, IGLOOE (Flash)

ProASIC Plus (Flash)

ProASIC3, ProASIC3E (Flash)

RTAX (Radiation Tolerant, Anti-fuse)

RTSX-SU (Radiation Tolerant, Anti-fuse)

Smart Fusion, Smart Fusion 2 (ARM cortex M3)

Structure of FPGA

ASIC design flow

References

[1]. Digital Principles & Design by Donald D. Givone, Tata

McGraw-Hill Edition.
[2]. Application Specific ICs by M.J.S.Smith(1997), Addison
Wesley, Pearson education.