International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 4 Issue: 3

ISSN: 2321-8169
466 - 468

_______________________________________________________________________________________

A Review - Quaternary Signed Digit Number System by Reversible Logic Gate

Purva Agarwal1, Dr. Pawan Whig2
1
2

M.Tech Scholar, R.I.E.T , Jaipur, Rajasthan, India

Deputy Director., R.I.E.T , Jaipur, Rajasthan, India

Abstract:- A limitation is applied over the speed of latest computers while performing the arithmetic functions such as subtraction, addition &
multiplication have to deal with delay in propagation. The arithmetic operations that are free of carry are attained by implementation of high
level radix number system such as QSD. We suggest high speed adders constituted over QSD number system. In QSD, every digit is presented
by a number in between -3 to 3. The operations on greater numbers like 64, 128 & addition that is carry free is implemented with a persistent
delay & low complicacy. In this document, a reversible logic gate is implemented that is constituted over QSD. The performance of QSD adder
can be improvised by invading adder based over logic gate that absorbs low power & delay.
Keywords- Carry free addition, Fast computing, FPGA, Quaternary Signed Digit, VHDL, VLSI.

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I.

INTRODUCTION

There is major role of arithmetic operations in variegated digital

circuitries like process controllers, computers, computer graphics,
signal processors & image processing. The advancements in the
techniques implemented in digital circuitries form arithmetic
circuitries that work fine with implementation of VLSI circuits [1].
Though arithmetic operations have to deal with some acknowledged
issues such as low number of bits, time delay in propagation &
complicacy of circuitry. Since, FPGAs i.e. flexibility of field
programmable gate arrays supports the advancement in the
customized hardware that gives high level of performances. By
choosing arithmetic algorithms that match FPGA technique &
implementing optimal mapping stratagems, development of high
performance FPGA can be done [7].
In this document, a reversible logic gate with higher speed reversible
logics that re constituted over QSD logical unit can carry free
addition, borrow free subtraction, multiplication operations & updown count. The addition pr subtraction operations of QSD require a
definite numbers of minimum terms for any size of operand. Signed
digit number system offer the occurrence of carry free addition. QSD
adder/multiplier circuitries are logic gates that re formulated with the
purpose to do arithmetic operations at a faster rate. In the number
system of QSD, carry propagation chin is eliminated that helps in the
deduction of computational time & so rising the speed of machine
[2].

II.

QUATERNARY SIGNED DIGIT NUMBERS

such as 64, 128, or more can be implemented through constant delay.

Features such as low level of complexity, information storage
density, less system constituents & cascade gates & operations are
attained by implementation of a high radix based signed digit number
system like QSD. The adders & multipliers with advantages of area
and speed efficiency can be implemented through this technology.

III.

ADDER DESIGN

The arithmetic unit that works with higher speed permits the
expansion of application domain for fast multipliers used in digitized
signal processing, inversing the matrices, digits filters, modular
exponential, computing Eigen values etc. it also helps to gain control
over some other functions like square roots, reciprocals, inverse
square roots & various other kind of elementary operations. For some
of the functions a final multiplication is also obtained.
Addition is considered as the important operation in the digitized
computations. As the number of digits grew, demand for carry free
additions is more. This type of addition is attained by exploitation of
redundancy of QSD numbers & QSD addition. Redundancy helps to
present an integer in various different forms.

QSD numbers are presented by using a 3-bits complement notation.

Every number is presented as:

D=

Here xi can be put as any number from the set {3, 2, 1, 0, 1, 2, 3} for
generating an appropriate decimal presentation. A negative number
of QSD act as complement of QSD for QSD positive number i.e.3 = 3, 2 = -2, 1 = -1. For digital implementation, large number of digits

There are two steps that are required for performing carry free
addition. The first step produces an intermediate carry & sum from
the augends & addend. In the next step, carry of lower significant
digits is combined with the addition of current digits [3]6].
In order to avoid rippling of carry, two guidelines are explained. As
per the first rule, magnitude of intermediate sum should be either
equal or less than 2. The second rule explains that carry should be
466

IJRITCC | March 2016, Available @ http://www.ijritcc.org

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International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 4 Issue: 3

ISSN: 2321-8169
466 - 468

_______________________________________________________________________________________
equal or less than 1. Simultaneously, magnitude of 2nd step outcome
must not be higher than 3 that is presented by a QSD number of
single digit. This is why no additional carry is needed. In the 1 st step,
all permissible pairs of inputs of augends & addend are taken into
account. The outcome range in between -6 to 6 as presented in Table
1.

Table I. The Outputs Of All Possible Combinations Of A Pair

Of Addend (A) And Augends (B)
The range of outcomes lies from -6 to 6 that is presented in median
carry & sum in QSD form as in Table 2.

Few numbers can be presented in different forms, but the selections

are made for the one that follow the defined guidelines. The selected
median carry & sum are presented in last column of Table 3.
Both of the outcomes & inputs are encoded in a 3-bit 2s
complement binary number. Mapping done in the addend, inputs &
augends & the outcomes, median carry & sum are presented in
binary form in Table 4. As the median carry lie in between the -1 &
1, only2-bit presentation is needed for it. Lastly, five of the 6-varible
Boolean expressions are obtained. The median carry & sum circuitry
is visualized from the Figure 1.

Figure.1. The intermediate carry and sum generator

In the 2nd step, the median carry out the less significant figure that is
included in the addition of current figure to give out an outcome. No
carry is observed even though the step is added as current digit is
able to intake the carry-in from lower digit. All the relative
combinations of summation are presented by table 3 in between the
sum & median carry.

Table II:- Outputs Of All Possible Combinations Of A Pair Of

Intermediate Carry (A) And Sum (B)
Figure 2. The second step QSD adder.

Table IV:- Selected Pair Of Intermediate Carry And Sum

IV.

Table III :- The Intermediate Carry And Sum Between -6 To 6

PROBLEM STATEMENT

Complicacy in a circuitry & delay in propagation are some of the

main problems that every digital circuitry has to deal with. In binary
system of numbers, speed of computation relies on propagation &
formulation of carry particularly when quantity of bits gets raised.
The QSD number system has advantages of performing fast
computations with the help of characteristics of redundancy that
perform the operations of addition, subtraction, multiplication
without free of carry & borrow free subtraction. N arithmetic
operation that is free of any array is attained by implementation of a
467

IJRITCC | March 2016, Available @ http://www.ijritcc.org

_______________________________________________________________________________________

International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 4 Issue: 3

ISSN: 2321-8169
466 - 468

_______________________________________________________________________________________
greater radix number system like QSD. The number system of QSD
is presented by the numbers of -3, -2, -1, 0, 1, 2, 3. Addition,
subtraction & other functions on higher bits like 64, 128, 256, 512 or
can be employed with low complicacy & persistent delay that rise on
a linear pace. In the past document, working of normal full adder was
observed that absorbs more mount of power. The delay & power of
QSD adder can be lessened further.

V.

PROPOSED METHODOLOGY

Full adder can be designed by implementing the reversible logic gate.

This gate is able to minimize the power absorption by QSD circuitry.
Peres gate will be invaded for designing a full adder that will be
further implanted in QSD adder.

Fig 3:- Peres Gate

[2] I.M. Thoidis, D. Soudris, J.M. Fernandez , A. Thanailakis,

The circuit design of multiple-valued logic voltage-mode
adders, 2001 IEEE International Symposium on Circuits
and Systems, pp 162-165,Vol. 4 , 2001.
[3] Hwang K. (1979) Computer Arithmetic Principles
Architecture and Design. New York : Wiley.
[4] N. Takagi, H. Yasuura, and S. Yajima, High Speed VLSI
Multiplication Algorithm with a Redundant Binary
Addition Tree, IEEE Trans. Comp., C-34, pp. 789-795,
1985.K. Elissa, Title of paper if known, unpublished.
[5] O. Ishizuka, A. Ohta, K. Tannno , Z. Tang, D. Handoko ,
VLSI design of a quaternary multiplier with direct
generation of partial products, Proceedings of the 27th
International Symposium on Multiple Valued Logic, pp.
169-174, 1997.
[6] J.U.Ahmed, A.A.S. Awwal, Multiplier design using
RBSD number system, Proceedings of the 1993 National
Aerospace and Electronics Conference, pp. 180-184, Vol.
1, 1993.
[7] A. Avizienis, Signed-Digit Number Representation for
Fast Parallel Arithmetic, IRE Transaction Electron.
Comp., EC-10, pp. 389-400, 1961.
[8] M. E. Louie and M. D. Ercegovac, On Digit -Recurrence
Division Implementations for Field Programmable gate
Arrays In Proc. Of the 11th symposium on Computer
Arithmetic, PP. 202-209, Canada.

It is seen from the figure 3, that peres gate is comprised of three

inputs & outputs. Figure 4 presents the suggested circuitry for
designing of a full adder by making use of peres reversed gate. A
suggested circuitry for designing a full adder is presented in figure 4
by making use of peres reversible gates. This design will be
implemented in QSD adder.

Fig 4:- Full adder design by peres gate

VI.

CONCLUSION

Some arithmetic circuitries that are efficient and comprised of

multiplier, adder & subtractor are formed by making use of QSD
number system. Some persistent delays are faced with the function of
raising the quantity of bits. This design possesses fewer amounts of
delay & power in accordance to the design of adder that was
suggested in last paper of QSD systems.

References
[1] Chao Cheng; Parhi and K.K. High-Throughput VLSI
Architecture for FFT Computation, IEEE Transactions on
Volume 54, Issue 10, Page 863 867, October 2007.
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