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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Figure : Computer
Figure : Functional View of
Computer.
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
History of Computers
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Performance Balance
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VJEC, Chemperi
Hardwired Program
Program in the form of hardware
Configuration of particular components for specific
computation
Software
General purpose configuration of arithmetic and logic
functions.
Based on control signal and data, result will be generated.
Unique code for each control signal
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Components of System
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VJEC, Chemperi
Components of System
CPU
Instruction interpreter + arithmetic and logic functions.
MAR - address in memory for next read/write
MBR - data to be written or received
I/O Components
Accepting data
Memory
To store instructions and data
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
Figure : Formats
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
Interrupts
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
Multiple Interrupts
Two approaches
Sequential Interrupt Processing - disable other interrupts
Nested Interrupt Processing (ISR processing) - Priority based
execution of interrupt
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
Multiple Interrupts
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components
Computer Functions
I/O Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Interconnection Structures
Collection of Paths connecting computer components
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Interconnection Structures
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
BUS Interconnection
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Bus Structure
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Multiple-Bus Hierarchies
More devices connected to sinle bus, performance will suffer
Bus length increases, more propagation delay
Data transfer demand approaches capacity of bus
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Bus Types
Method of Arbitration
Timing
Bus Width
Data Transfer type
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Bus Types
Time Multiplexed
Address and data through same line
Initially address through line
After certain period of time data through line
Advantages - Fewer lines required
Disadvantages - More complex circuity required
Dedicated
Separate address and data lines
Each bus connects only a subset modules
Eg: I/O bus interconnect I/O modules only
Advantage - High throughput
Disadvantage - Increased size
Computer Organization & Architecture - Module 1
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Method of Arbitration
Centralized
Bus controller or arbiter is responsible for allocating time on
bus
Distributed
No central controller
Each module contains control logic
Master may initiate data transfer
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Timing
Synchronous Timing
Occurrence of events on the bus is determined by a Clock
Clock Cycle - 1 - 0 transmission
All events start at the beginning of clock
Asynchronous Ting
Occurrence of one event depends on previous event
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Bus Width
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
PCI
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
PCI Configutations
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
PCI Commands
Bus activity occurs in the form of transactions between master and
target.
Commands are:
Interrupt Acknowledge
Serial Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Memory Read Line
Memory Read Multiple
Memory Write
Memory write and Invalidate
Computer Organization & Architecture - Module 1
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Each data transfer - one address phase and more data phase
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Figure : PCI Data Transfer
- Read
VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
CPU
Contents
Computer Arithmetic
Instruction Sets: Characteristics and Functions
Instruction Sets: Addressing Modes and Formats
CPU Structure and Function
Reduced Instruction Set Computers
Instruction Level Parallelism
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Integer Representation
(1)
i=0
Computer Organization & Architecture - Module 1
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Sign-Magnitude Representation
Sign Magnitude
a=
n2
P i
2 ai if an1 = 0
i=0
n2
P i
2 ai if an1 = 1
(2)
i=0
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
2s Compliment Representation
A = 2n1 an1 +
n2
X
2i ai
(3)
i=0
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Integer Arithmetic
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Addition
Chance of overflow
When overflow occurs if and only if the result has the
opposite sign
If overflow occurs, ALU will not consider result- Overflow Rule
Subtraction
To subtract one number take the twos complement of the
subtrahend and add it to the minuend. - Subtraction Rule
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Multiplication
Unsigned Integers
Generation of partial products then summation
Partial product - multiplier bit is 0, the partial product is
0.When the multiplier is 1, the partial product is the
multiplicand
The total product is produced by summing the partial
products
For n bit multiplication, Result will 2n bit length
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Unsigned Multiplication
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Different Approaches
Covert both multiplier to positive and then take twos if sign of
original numbers differed
Booth Algorithm
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Booth Multiplication
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Addition
Subtraction
Multiplication
Division
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Representation
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Types
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Number of Addresses
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Number of Addresses
AB
C +(DxE )
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Number of Addresses
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operands
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Numbers
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Characters
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Logical Data
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operations
Data transfer
Move - Transfer word or block from source to destination
Store - Transfer word from processor to memory
Load - Transfer word from memory to processor
Exchange - Swap contents of source and destination
Clear- (reset) Transfer word of 0s to destination
Set - Transfer word of 1s to destination
Push - Transfer word from source to top of stack
Pop - Transfer word from top of stack to destination
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operations
Arithmetic
Add - Compute sum of two operands
Subtract - Compute difference of two operands
Multiply - Compute product of two operands
Divide - Compute quotient of two operands
Absolute - Replace operand by its absolute value
Negate - Change sign of operand
Increment - Add 1 to operand
Decrement - Subtract 1 from operand
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operations
Logical
Perform - logical AND
OR - Perform logical OR
NOT - (complement) Perform logical NOT
Exclusive-OR - Perform logical XOR
Test - Test specified condition; set flag(s) based on outcome
Compare - Make logical or arithmetic comparison of two or
more operands; set flag(s) based on outcome
Set Control Variables - Class of instructions to set controls for
protection purposes, interrupt handling, timer control, etc.
Shift Left (right) - shift operand, introducing constants at end
Rotate Left (right) - shift operand, with wraparound end
Computer Organization & Architecture - Module 1
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operations
Transfer of Control
Jump (branch) - Unconditional transfer; load PC with
specified address
Jump Conditional - Test specified condition; either load PC
with specified address or do nothing, based on condition
Jump to Subroutine - Place current program control
information in known location; jump to specified address
Return - Replace contents of PC and other register from
known location
Execute - Fetch operand from specified location and execute
as instruction; do not modify PC
Skip - Increment PC to skip next instruction
Skip Conditional - Test specified condition; either skip or do
nothing based on condition
Computer Organization & Architecture - Module 1
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operations
Input/Output
Input (read) - Transfer data from specified I/O port or device
to destination (e.g., main memory or processor register)
Output (write) - Transfer data from specified source to I/O
port or device
Start - I/O Transfer instructions to I/O processor to initiate
I/O operation
Test - I/O Transfer status information from I/O system to
specified destination
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Types of Operations
Conversion
Translate - Translate values in a section of memory based on
a table of correspondences
Convert - Convert the contents of a word from one form to
another (e.g., packed decimal to binary)
Data Transfer
Transfer data from one location to another - If memory is
involved: Determine memory address Perform
virtual-to-actual-memory address transformation Check cache
Initiate memory read/write
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Assembly Langage
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Addressing
To refer a large range of locations in main memory or, for some
systems, virtual memory
Common addressing techniques
Immediate
Direct
Indirect
Register
Register indirect
Displacement
Stack
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Immediate Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Immediate Addressing
Operand = A
(4)
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Direct Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Direct Addressing
EA = A
(5)
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Indirect Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Indirect Addressing
EA = (A)
(6)
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Register Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Register Addressing
EA = R
(7)
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
EA = (R)
(8)
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Displacement Addressing
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Displacement Addressing
EA = A + (R)
(9)
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Displacement Addressing
Relative Addressing
Also called PC-relative addressing
Implicitly referenced register is the program counter (PC).
next instruction address is added to the address field to
produce the EA
three of the most common uses: Relative addressing,
Base-register addressing, Indexing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Displacement Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Indexing
Indexing
address field references a main memory address,
Referenced register contains a positive displacement from that
address
postindexing : EA = (A) + (R)
preindexing : EA = (A + (R))
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Stack Addressing
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Stack Addressing
EA = topofstack
(10)
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Formats
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Length
Affected by memory size, memory organization, bus structure,
processor speed etc
Trade-off here - Powerful instruction repertoire and a need to
save space
Instruction length should be equal to the memory-transfer
length or multiple.
Processor speed
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Variable-Length Instructions
Provide a large repertoire of opcodes, with different opcode
lengths. Addressing can be more flexible
Increase in the complexity of the processor
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Variable-Length Instructions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Processor Organization
Processor must do
Fetch instruction: Reads an instruction from memory
Interpret instruction: The instruction is decoded to determine
what action is required.
Fetch data: Reading data from memory or an I/O module
Process data: Perform some arithmetic or logical operation on
data.
Write data: Writing data to memory or an I/O module
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Processor - Components
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Processor
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Register Organization
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Register Organization
User-Visible Registers
General purpose - Can contain the operand for any opcode,
may be dedicated registers, can be used for addressing
functions
Data - to hold data
Address - Segment pointers, Index registers, Stack pointer
Condition codes - flags, part of control register
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Essential Registers
Program counter (PC): Contains the address of an instruction
to be fetched
Instruction register (IR): Contains the instruction most
recently fetched
Memory address register (MAR): Contains the address of a
location in memory
Memory buffer register (MBR): Contains a word of data to be
written to memory or the word most recently read
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Cycle
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Cycle
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Cycle
Indirect Cycle
indirect addressing is used, then additional memory accesses
After fetching, operands must be identified
Then operand memory will be fetched
Then check for indirect addressing
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Cycle
Data Flow
Processor uses a memory address register (MAR), a memory
buffer register (MBR), a program counter (PC), and an
instruction register (IR)
Fetch cycle - an instruction is read from memory
PC - address of the next instruction to be fetched
PC address is moved to the MAR and placed on the address
bus
Control unit requests a memory read, and the result is placed
on the data bus and copied into the MBR and then moved to
the IR.
After fetch - control unit examines the contents of the IR to
determine if it contains an operand specifier using indirect
addressing
Computer Organization & Architecture - Module 1
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Cycle
Data Flow - Conti..
The rightmost N bits of the MBR, which contain the address
reference, are transferred to the MAR
Control unit requests a memory read, to get the desired
address of the operand into the MBR
Execute cycle - transferring data among registers, read or
write from memory or I/O, and/or the invocation of the ALU
Interrupt cycle - current contents of the PC must be saved so
that the processor can resume normal activity after the
interrupt
PC are transferred to the MBR to be written into stack
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VJEC, Chemperi
Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Instruction Pielining
Pipelining Strategy
Technique used in the design of computers to increase their
instruction throughput
Pipeline - basic instruction cycle is broken up into a series
Processing each instruction sequentially
Different steps can be executed concurrently
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Pipelining
Siplified View
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Pipelining
Decomposition of the instruction processing
Fetch instruction (FI): Read the next expected instruction into
a buffer.
Decode instruction (DI): Determine the opcode and the
operand specifiers.
Calculate operands (CO): Calculate the effective address of
each source operand. This may involve displacement, register
indirect, indirect, or other forms of address calculation.
Fetch operands (FO): Fetch each operand from memory.
Operands in registers need not be fetched.
Execute instruction (EI): Perform the indicated operation and
store the result, if any, in the specified destination operand
location.
Write operand (WO): Store the result in memory
Computer Organization & Architecture - Module 1
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Pipelining
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Pipelining Algorithm
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Pipeline Performance
Measures of pipeline performance
= max[i + d] = m + d1 i k
(11)
Where
i = time delay of the circuitry in the ith stage of the pipeline m
= maximum stage delay (delay through stage which experiences
the largest delay)
k = number of stages in the instruction pipeline
d = time delay of a latch, needed to advance signals and data
from one stage to the next
Total time required for a pipeline with k stages to execute n
instructions
Tk,n = [k + (n 1)]
Computer Organization & Architecture - Module 1
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(12)
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Pipeline Hazards
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Pipeline Hazards
Resource Hazards
Occurs when two (or more) instructions that are already in
the pipeline need the same resource
Result is that the instructions must be executed in serial
rather than parallel
Referred to as a structural hazard
Another example of a resource conflict is a situation in which
multiple instructions are ready to enter the execute instruction
phase and there is a single ALU
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Resource Hazards
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Pipeline Hazards
Data Hazards
When there is a conflict in the access of an operand location
Two instructions in a program are to be executed in sequence
and both access a particular memory or register operand
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Data Hazards
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Data Hazards
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Data Hazards
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Pipeline Hazards
Control Hazards
known as a branch hazard
Control Hazards arise from the pipelining of branches and
other instructions that change the Program Counter
When a branch is executed it may or may not change the
Program Counter and thus may not change the instruction
that is to be fetched
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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions
Approaches
Multiple streams
Prefetch branch target
Loop buffer
Branch prediction
Delayed branch
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Multiple streams
replicate the initial portions of the pipeline and allow the pipeline
to fetch both instructions Problems with this approach
With multiple pipelines there are contention delays for access
to the registers and to memory
Additional branch instructions may enter the pipeline (either
stream) before the original branch decision is resolved.
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Multiple streams
Loop Buffer
A loop buffer is a small, very-high-speed memory maintained
by the instruction fetch stage of the pipeline and containing
the n most recently fetched instructions, in sequence
If a branch is to be taken, the hardware first checks whether
the branch target is within the buffer
If so, the next instruction is fetched from the buffer
Advantages :- Less memory access time, for dealing with loops
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Branch Prediction
Various Techniques
Predict never taken
Predict always taken
Predict by opcode
Taken/not taken switch
Branch history table
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Branch Prediction
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Branch Prediction
Predict by opcode
By reading opcode
Taken/not taken switch
One bit reflects branching history
Branch history table
Two bits or more for branching status. It can store more than two
previous conditions
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Branch Prediction
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Branch Prediction
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Delayed Branch
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Why CISC
larger number of instructions and more complex instructions.
complex machine instructions are often hard to exploit
Compiler Simplification - Optimization more difficult
Program takes up less memory but Memory is now cheap
number of bits of memory occupied may not be noticeably
smaller
Longer opcodes are required, producing longer instructions
More complex control unit
thus simple instructions take longer to execute
It is far from clear that CISC is the appropriate solution
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Characteristics of RISC
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CISC Vs RISC
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RISC Pipelining
Load/Store : 3 stages
I: Instruction fetch
E: Execute : Calculate memory address
D: Memory : Register to memory or memory to register
operation
E1: Register file read
E2: ALU operation and Register write
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Pipelining
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Pipelining
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Pipelining
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