UCF Nexys 3

##
##
##
##
This file is a general .ucf for Nexys2 rev A board

To use it in a project:
- remove or comment the lines corresponding to unused pins
- rename the used signals according to the project
##
er
##
##
Signals Led<7> Led<4> are assigned to pins which change type from s3e500 to oth
dies using the same package
Both versions are provided in this file.
Keep only the appropriate one, and remove or comment the other one.
## Clock pin for Nexys 2 Board

NET "clk"
LOC = "B8";
# Bank = 0, Pin name = IP_L13P_0/GCLK8, Type =
GCLK,
Sch name = GCLK0
#NET "clk1"
LOC = "U9";
# Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Ty
pe = DUAL/GCLK,
Sch name = GCLK1
## onBoard USB controller
## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use bot
h DEPP and DSTM use a signle net name for each shared pin.
## Data bus for both the DEPP and
either one
#NET "DB<0>"
LOC = "R14";
UAL,
Sch name =
#NET "DB<1>"
LOC = "R13";
UAL,
Sch name =
#NET "DB<2>"
LOC = "P13";
UAL,
Sch name =
#NET "DB<3>"
LOC = "T12";
Sch name =
#NET "DB<4>"
LOC = "N11";
Sch name =
#NET "DB<5>"
LOC = "R11";
Sch name =
#NET "DB<6>"
LOC = "P10";
e = DUAL/GCLK,
Sch name =
#NET "DB<7>"
LOC = "R10";
e = DUAL/GCLK,
Sch name =
DSTM interfaces uncomment lines 20-27 if using

# Bank
U-FD0
# Bank
U-FD1
# Bank
U-FD2
# Bank
U-FD3
# Bank
U-FD4
# Bank
U-FD5
# Bank
U-FD6
# Bank
U-FD7
= 2, Pin name = IO_L24N_2/A20, Type = D

= 2, Pin name = IO_L22P_2/A23, Type = D
= 2, Pin name = IO_L20P_2, Type = I/O,
= 2, Pin name = IO_L18N_2, Type = I/O,
= 2, Pin name = IO, Type = I/O,
= 2, Pin name = IO_L15N_2/D1/GCLK3, Typ
= 2, Pin name = IO_L15P_2/D2/GCLK2, Typ
## If using the DEPP interface uncomment lines 30-33

#NET "EppWRITE"
LOC = "V16"; # Bank = 2, Pin name
Sch name = U-FLAGC
#NET "EppASTB"
LOC = "V14"; # Bank = 2, Pin name
,
Sch name = U-FLAGA
#NET "EppDSTB"
LOC = "U14"; # Bank = 2, Pin name
,
Sch name = U-FLAGB
#NET "EppWAIT"
LOC = "N9";
# Bank = 2, Pin name
pe = DUAL/GCLK,
Sch name = U-SLRD
## If using the DSTM interface uncomment lines 36-45
#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name
Sch name = U-IFCLK
#NET "DstmSLCS"
LOC = "T16"; # Bank = 2, Pin name
= DUAL,
Sch name = U-SLCS
#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name
,
Sch name = U-FLAGA
#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name
,
Sch name = U-FLAGB
= IP, Type = INPUT,

= IP_L23P_2, Type = INPUT
= IP_L23N_2, Type = INPUT
= IO_L12P_2/D7/GCLK12, Ty
= IO/VREF_2, Type = VREF,

= IO_L26P_2/VS0/A17, Type
= IP_L23P_2, Type = INPUT
= IP_L23N_2, Type = INPUT
#NET "DstmADR<0>"
UAL,
#NET "DstmADR<1>"
= VREF,
#NET "DstmSLRD"
pe = DUAL/GCLK,
#NET "DstmSLWR"
pe = DUAL/GCLK,
#NET "DstmSLOE"
= DUAL,
#NET "DstmPKTEND"
LOC = "T14";
Sch name
LOC = "V13";
Sch name
LOC = "N9";
Sch name
LOC = "V9";
Sch name
LOC = "V15";
Sch name
LOC = "V12";
Sch name
# Bank = 2,
= U-FIFOAD0
# Bank = 2,
= U-FIFOAD1
# Bank = 2,
= U-SLRD
# Bank = 2,
= U-SLWR
# Bank = 2,
= U-SLOE
# Bank = 2,
= U-PKTEND
Pin name = IO_L24P_2/A21, Type = D
#NET "UsbMode"
= DUAL,
#NET "UsbRdy"
LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type

Sch name = U-INT0#
LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT,
Sch name = U-RDY
Pin name = IO_L19N_2/VREF_2, Type

Pin name = IO_L12P_2/D7/GCLK12, Ty
Pin name = IO_L13N_2/D3/GCLK15, Ty
Pin name = IO_L25P_2/VS2/A19, Type
Pin name = IO_L19P_2, Type = I/O,
## onBoard Cellular RAM and StrataFlash

#NET "MemOE"
LOC = "T2";
# Bank = 3, Pin name = IO_L24P_3, Type = I/O,
Sch name = OE
#NET "MemWR"
LOC = "N7";
Sch name = WE
#NET "RamAdv"
= LHCLK,
#NET "RamCS"
#NET "RamClk"
#NET "RamCRE"
#NET "RamLB"
= LHCLK,
#NET "RamUB"
= LHCLK,
#NET "RamWait"
LOC = "J4";
Sch name
LOC = "R6";
Sch name
LOC = "H5";
Sch name
LOC = "P7";
Sch name
LOC = "K5";
Sch name
LOC = "K4";
Sch name
LOC = "F5";
Sch name
# Bank =
= MT-ADV
# Bank =
= MT-CE
# Bank =
= MT-CLK
# Bank =
= MT-CRE
# Bank =
= MT-LB
# Bank =
= MT-UB
# Bank =
= MT-WAIT
3, Pin name = IO_L11N_3/LHCLK1, Type

2, Pin name = IO_L05P_2, Type = I/O,
3, Pin name = IO_L08N_3, Type = I/O,
3, Pin name = IP, Type = INPUT,
#NET "FlashRp"
LOC = "T5";
# Bank = 2, Pin name = IO_L04N_2, Type = I/O,
Sch name = RP#
#NET "FlashCS"
LOC = "R5";
Sch name = ST-CE
#NET "FlashStSts" LOC = "D3";
# Bank = 3, Pin name = IP, Type = INPUT,
Sch name = ST-STS
#NET "MemAdr<1>"
= LHCLK,
#NET "MemAdr<2>"
Type = LHCLK,
#NET "MemAdr<3>"
#NET "MemAdr<4>"
#NET "MemAdr<5>"
#NET "MemAdr<6>"
= LHCLK,
#NET "MemAdr<7>"
LOC = "J1";
Sch name
LOC = "J2";
Sch name
LOC = "H4";
Sch name
LOC = "H1";
Sch name
LOC = "H2";
Sch name
LOC = "J5";
Sch name
LOC = "H3";
Sch name
# Bank
= ADR1
# Bank
= ADR2
# Bank
= ADR3
# Bank
= ADR4
# Bank
= ADR5
# Bank
= ADR6
# Bank
= ADR7
= 3, Pin name = IO_L12P_3/LHCLK2, Type

= 3, Pin name = IO_L12N_3/LHCLK3/IRDY2,
#NET "MemAdr<8>"
#NET "MemAdr<9>"
#NET "MemAdr<10>"
#NET "MemAdr<11>"
#NET "MemAdr<12>"
#NET "MemAdr<13>"
= VREF,
#NET "MemAdr<14>"
#NET "MemAdr<15>"
#NET "MemAdr<16>"
#NET "MemAdr<17>"
#NET "MemAdr<18>"
#NET "MemAdr<19>"
#NET "MemAdr<20>"
= VREF,
#NET "MemAdr<21>"
Type = LHCLK,
#NET "MemAdr<22>"
#NET "MemAdr<23>"
= LHCLK,
#NET "MemDB<0>"
#NET "MemDB<1>"
#NET "MemDB<2>"
#NET "MemDB<3>"
#NET "MemDB<4>"
#NET "MemDB<5>"
#NET "MemDB<6>"
#NET "MemDB<7>"
#NET "MemDB<8>"
#NET "MemDB<9>"
= VREF,
#NET "MemDB<10>"
#NET "MemDB<11>"
#NET "MemDB<12>"
#NET "MemDB<13>"
LOC = "H6";
Sch name
LOC = "F1";
Sch name
LOC = "G3";
Sch name
LOC = "G6";
Sch name
LOC = "G5";
Sch name
LOC = "G4";
Sch name
LOC = "F2";
Sch name
LOC = "E1";
Sch name
LOC = "M5";
Sch name
LOC = "E2";
Sch name
LOC = "C2";
Sch name
LOC = "C1";
Sch name
LOC = "D2";
Sch name
LOC = "K3";
Sch name
LOC = "D1";
Sch name
LOC = "K6";
Sch name
# Bank
= ADR8
# Bank
= ADR9
# Bank
= ADR10
# Bank
= ADR11
# Bank
= ADR12
# Bank
= ADR13
# Bank
= ADR14
# Bank
= ADR15
# Bank
= ADR16
# Bank
= ADR17
# Bank
= ADR18
# Bank
= ADR19
# Bank
= ADR20
# Bank
= ADR21
# Bank
= ADR22
# Bank
= ADR23
LOC = "L1";
Sch name
LOC = "L4";
Sch name
LOC = "L6";
Sch name
LOC = "M4";
Sch name
LOC = "N5";
Sch name
LOC = "P1";
Sch name
LOC = "P2";
Sch name
LOC = "R2";
Sch name
LOC = "L3";
Sch name
LOC = "L5";
Sch name
LOC = "M3";
Sch name
LOC = "M6";
Sch name
LOC = "L2";
Sch name
LOC = "N4";
# Bank
= DB0
# Bank
= DB1
# Bank
= DB2
# Bank
= DB3
# Bank
= DB4
# Bank
= DB5
# Bank
= DB6
# Bank
= DB7
# Bank
= DB8
# Bank
= DB9
# Bank
= DB10
# Bank
= DB11
# Bank
= DB12
# Bank

= 3, Pin name = IO_L06N_3/VREF_3, Type
= 3, Pin name = IO_L13P_3/LHCLK4/TRDY2,

#NET "MemDB<14>"
#NET "MemDB<15>"
Sch name = DB13

LOC = "R3";
Sch name = DB14
LOC = "T1";
Sch name = DB15
## 7 segment display
#NET "seg<0>"
LOC = "L18";
Sch name
#NET "seg<1>"
LOC = "F18";
Sch name
#NET "seg<2>"
LOC = "D17";
UAL,
Sch name
#NET "seg<3>"
LOC = "D16";
DUAL,
Sch name
#NET "seg<4>"
LOC = "G14";
Sch name
#NET "seg<5>"
LOC = "J17";
Y1, Type = RHCLK/DUAL, Sch name
#NET "seg<6>"
LOC = "H14";
Sch name
#NET "dp"
LOC = "C17";
DUAL,
Sch name
#NET "an<0>"
#NET "an<1>"
AL,
#NET "an<2>"
DUAL,
#NET "an<3>"
LOC = "F17";
Sch name
LOC = "H17";
Sch name
LOC = "C18";
Sch name
LOC = "F15";
Sch name
## Leds
#NET "Led<0>"
LOC
pe = RHCLK/DUAL,
#NET "Led<1>"
LOC
pe = RHCLK/DUAL,
#NET "Led<2>"
LOC
pe = RHCLK/DUAL,
#NET "Led<3>"
LOC
Y1, Type = RHCLK/DUAL,
#NET "Led<4>"
LOC
#NET "Led<5>"
LOC
#NET "Led<6>"
LOC
#NET "Led<7>"
LOC
#NET "Led<4>"
LOC
#NET "Led<5>"
LOC
#NET "Led<6>"
LOC
#NET "Led<7>"
LOC
## Switches
= "J14";
Sch name
= "J15";
Sch name
= "K15";
Sch name
= "K14";
Sch name
= "E17";
Sch name
= "P15";
Sch name
= "F4";
Sch name
= "R4";
Sch name
= "E16";
Sch name
= "P16";
Sch name
= "E4";
Sch name
= "P4";
Sch name
# Bank
= CA
# Bank
= CB
# Bank
= CC
# Bank
= CD
# Bank
= CE
# Bank
= CF
# Bank
= CG
# Bank
= DP
# Bank
= AN0
# Bank
= AN1
# Bank
= AN2
# Bank
= AN3

= 1, Pin name = IO_L23P_1/HDC, Type = D
= 1, Pin name = IO_L23N_1/LDC0, Type =
= 1, Pin name = IO_L13P_1/A6/RHCLK4/IRD
= 1, Pin name = IO_L24N_1/LDC2, Type =
= 1, Pin name = IO_L16N_1/A0, Type = DU

= 1, Pin name = IO_L24P_1/LDC1, Type =
# Bank = 1, Pin name =

= JD10/LD0
= JD9/LD1
= JD8/LD2
= JD7/LD3
= LD4? s3e500 only
= LD5? s3e500 only
= LD6? s3e500 only
= LD7? s3e500 only
= LD4? other than s3e500
IO_L14N_1/A3/RHCLK7, Ty
IO_L14P_1/A4/RHCLK6, Ty
IO_L12P_1/A8/RHCLK2, Ty
IO_L12N_1/A7/RHCLK3/TRD
IO, Type = I/O,
IO, Type = I/O,
IO, Type = I/O,
IO/VREF_3, Type = VREF,
N.C., Type = N.C.,
N.C., Type = N.C.,
N.C., Type = N.C.,
N.C., Type = N.C.,
NET "rst"
LOC = "G18"; # Bank = 1,

Sch name = SW0
LOC = "H18"; # Bank =
Sch name = SW1
LOC = "K18"; # Bank =
Sch name = SW2
LOC = "K17"; # Bank =
Sch name = SW3
LOC = "L14"; # Bank =
Sch name = SW4
LOC = "L13"; # Bank =
Sch name = SW5
LOC = "N17"; # Bank =
Sch name = SW6
LOC = "R17"; # Bank =
Sch name = SW7
#NET "sw<1>"
#NET "sw<2>"
#NET "sw<3>"
#NET "sw<4>"
#NET "sw<5>"
#NET "sw<6>"
#NET "sw<7>"
## Buttons
#NET "btn<0>"
LOC = "B18";
Sch name
LOC = "D18";
Sch name
LOC = "E18";
Sch name
LOC = "H13";
Sch name
#NET "btn<1>"
#NET "btn<2>"
#NET "btn<3>"
# Bank
= BTN0
# Bank
= BTN1
# Bank
= BTN2
# Bank
= BTN3
Pin name = IP, Type = INPUT,

1, Pin name = IP/VREF_1, Type = VREF,
= 1, Pin name = IP, Type = INPUT,

= 1, Pin name = IP/VREF_1, Type = VREF,
## VGA Connector
NET "r<0>" LOC = "R9";
# Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name
= RED0
NET "r<1>" LOC = "T8";
Sch name = RED1
NET "r<2>" LOC = "R8";
Sch name = RED2
NET "g<0>" LOC = "N8";
Sch name = GRN0
NET "g<1>" LOC = "P8";
Sch name = GRN1
NET "g<2>" LOC = "P6";
Sch name = GRN2
NET "b<0>" LOC = "U5";
# Bank = 2, Pin name = IO/VREF_2, Type = VREF,
Sch name = BLU1
NET "b<1>" LOC = "U4";
# Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DU
AL,
Sch name = BLU2
NET "hs"
= DUAL,
NET "vs"
L,
LOC = "T4";
# Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type
Sch name = HSYNC
LOC = "U3";
# Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUA
Sch name = VSYNC
## PS/2 connector
#NET "PS2C"
LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O,
Sch name = PS2C
#NET "PS2D"
LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O,
Sch name = PS2D
## FX2 connector
#NET "PIO<0>"
#NET "PIO<1>"
LOC = "B4";
Sch name = R-IO1
LOC = "A4";
#NET "PIO<2>"
#NET "PIO<3>"
#NET "PIO<4>"
#NET "PIO<5>"
= VREF,
#NET "PIO<6>"
#NET "PIO<7>"
#NET "PIO<8>"
= VREF,
#NET "PIO<9>"
#NET "PIO<10>"
#NET "PIO<11>"
#NET "PIO<12>"
= VREF,
#NET "PIO<13>"
#NET "PIO<14>"
#NET "PIO<15>"
= GCLK,
#NET "PIO<16>"
#NET "PIO<17>"
#NET "PIO<18>"
#NET "PIO<19>"
GCLK,
#NET "PIO<20>"
GCLK,
#NET "PIO<21>"
GCLK,
#NET "PIO<22>"
#NET "PIO<23>"
#NET "PIO<24>"
GCLK,
#NET "PIO<25>"
#NET "PIO<26>"
#NET "PIO<27>"
#NET "PIO<28>"
#NET "PIO<29>"
#NET "PIO<30>"
#NET "PIO<31>"
Sch name
LOC = "C3";
Sch name
LOC = "C4";
Sch name
LOC = "B6";
Sch name
LOC = "D5";
Sch name
LOC = "C5";
Sch name
LOC = "F7";
Sch name
LOC = "E7";
Sch name
LOC = "A6";
Sch name
LOC = "C7";
Sch name
LOC = "F8";
Sch name
LOC = "D7";
Sch name
LOC = "E8";
Sch name
LOC = "E9";
Sch name
LOC = "C9";
Sch name
LOC = "A8";
Sch name
LOC = "G9";
Sch name
LOC = "F9";
Sch name
LOC = "D10";
Sch name
LOC = "A10";
Sch name
LOC = "B10";
Sch name
LOC = "A11";
Sch name
LOC = "D11";
Sch name
LOC = "E10";
Sch name
LOC = "B11";
Sch name
LOC = "C11";
Sch name
LOC = "E11";
Sch name
LOC = "F11";
Sch name
LOC = "E12";
Sch name
LOC = "F12";
Sch name
LOC = "A13";
= R-IO2
# Bank
= R-IO3
# Bank
= R-IO4
# Bank
= R-IO5
# Bank
= R-IO6
# Bank
= R-IO7
# Bank
= R-IO8
# Bank
= R-IO9
# Bank
= R-IO10
# Bank
= R-IO11
# Bank
= R-IO12
# Bank
= R-IO13
# Bank
= R-IO14
# Bank
= R-IO15
# Bank
= R-IO16
# Bank
= R-IO17
# Bank
= R-IO18
# Bank
= R-IO19
# Bank
= R-IO20
# Bank
= R-IO21
# Bank
= R-IO22
# Bank
= R-IO23
# Bank
= R-IO24
# Bank
= R-IO25
# Bank
= R-IO26
# Bank
= R-IO27
# Bank
= R-IO28
# Bank
= R-IO29
# Bank
= R-IO30
# Bank
= R-IO31
# Bank

= 0, Pin name = IO_L14P_0/GCLK10, Type
= 0, Pin name = IO_L11P_0/GCLK4, Type =
= 0, Pin name = IO_L12N_0/GCLK7, Type =
= 0, Pin name = IO_L12P_0/GCLK6, Type =
= 0, Pin name = IO_L11N_0/GCLK5, Type =
= 0, Pin name = IO/VREF_0, Type = VREF,
#NET "PIO<32>"
= VREF,
#NET "PIO<33>"
#NET "PIO<34>"
#NET "PIO<35>"
= VREF,
#NET "PIO<36>"
#NET "PIO<37>"
#NET "PIO<38>"
#NET "PIO<39>"
Sch name
LOC = "B13";
Sch name
LOC = "E13";
Sch name
LOC = "A14";
Sch name
LOC = "C14";
Sch name
LOC = "D14";
Sch name
LOC = "B14";
Sch name
LOC = "A16";
Sch name
LOC = "B16";
Sch name
## 12 pin connectors
##JA
#NET "JA<0>"
LOC
UAL,
#NET "JA<1>"
LOC
pe = RHCLK/DUAL,
#NET "JA<2>"
LOC
= VREF,
#NET "JA<3>"
LOC
##JB
#NET "JB<0>"
= VREF,
#NET "JB<1>"
UAL,
#NET "JB<2>"
#NET "JB<3>"
UAL,
#NET "JB<4>"
#NET "JB<5>"
= VREF,
#NET "JB<6>"
UAL,
#NET "JB<7>"
UAL,
##JC
#NET "JC<0>"
#NET "JC<1>"
pe = RHCLK/DUAL,

= "L15";
Sch name
= "K12";
Sch name
= "L17";
Sch name
= "M15";
Sch name
= "K13";
Sch name
= "L16";
Sch name
= "M14";
Sch name
= "M16";
Sch name
# Bank
= JA1
# Bank
= JA2
# Bank
= JA3
# Bank
= JA4
# Bank
= JA7
# Bank
= JA8
# Bank
= JA9
# Bank
= JA10
LOC = "M13";
Sch name
LOC = "R18";
Sch name
LOC = "R15";
Sch name
LOC = "T17";
Sch name
LOC = "P17";
Sch name
LOC = "R16";
Sch name
LOC = "T18";
Sch name
LOC = "U18";
Sch name
# Bank
= JB1
# Bank
= JB2
# Bank
= JB3
# Bank
= JB4
# Bank
= JB7
# Bank
= JB8
# Bank
= JB9
# Bank
= JB10
#NET "JA<4>"
LOC
ype = RHCLK/DUAL,
#NET "JA<5>"
LOC
UAL,
#NET "JA<6>"
LOC
#NET "JA<7>"
= R-IO32
# Bank
= R-IO33
# Bank
= R-IO34
# Bank
= R-IO35
# Bank
= R-IO36
# Bank
= R-IO37
# Bank
= R-IO38
# Bank
= R-IO39
# Bank
= R-IO40
LOC
= 1, Pin name = IO_L11N_1/A9/RHCLK1, Ty

= 1, Pin name = IO_L11P_1/A10/RHCLK0, T

LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O,

Sch name = JC1
LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Ty
Sch name = JC2
#NET "JC<2>"
#NET "JC<3>"
#NET "JC<4>"
#NET "JC<5>"
#NET "JC<6>"
#NET "JC<7>"
AL,
LOC = "G13";
Sch name
LOC = "H16";
Sch name
LOC = "H15";
Sch name
LOC = "F14";
Sch name
LOC = "G16";
Sch name
LOC = "J12";
Sch name
# Bank
= JC3
# Bank
= JC4
# Bank
= JC7
# Bank
= JC8
# Bank
= JC9
# Bank
= JC10

= 1, Pin name = IO_L15P_1/A2, Type = DU
##JD - NOTE: For other JD pins see LD(3:0)

#NET "JD<0>"
LOC = "J13"; # Bank =
AL,
Sch name = JD1
#NET "JD<1>"
LOC = "M18"; # Bank =
Sch name = JD2
#NET "JD<2>"
LOC = "N18"; # Bank =
Sch name = JD3
#NET "JD<3>"
LOC = "P18"; # Bank =
Sch name = JD4
above under "Leds"

1, Pin name = IO_L15N_1/A1, Type = DU
1, Pin name = IO_L08P_1, Type = I/O,
## RS232 connector
#NET "RsRx"
LOC = "U6";
# Bank = 2, Pin name = IP, Type = INPUT,
Sch name = RS-RX
#NET "RsTx"
LOC = "P9";
# Bank = 2, Pin name = IO, Type = I/O,
Sch name = RS-TX

UCF Nexys 3

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UCF Nexys 3

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##

This file is a general .ucf for Nexys2 rev A board

## Clock pin for Nexys 2 Board

DSTM interfaces uncomment lines 20-27 if using

= 2, Pin name = IO_L24N_2/A20, Type = D

## If using the DEPP interface uncomment lines 30-33

= IP, Type = INPUT,

= IO/VREF_2, Type = VREF,

Pin name = IO_L24P_2/A21, Type = D

LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type

Pin name = IO_L19N_2/VREF_2, Type

## onBoard Cellular RAM and StrataFlash

3, Pin name = IO_L11N_3/LHCLK1, Type

= 3, Pin name = IO_L12P_3/LHCLK2, Type

= 3, Pin name = IO_L08P_3, Type = I/O,

= 3, Pin name = IO_L15P_3, Type = I/O,

= 3, Pin name = IO_L05P_3, Type = I/O,

= 3, Pin name = IO_L16N_3, Type = I/O,

Sch name = DB13

= 1, Pin name = IO_L10P_1, Type = I/O,

= 1, Pin name = IO_L19N_1, Type = I/O,

= 1, Pin name = IO_L19P_1, Type = I/O,

= 1, Pin name = IO_L16N_1/A0, Type = DU

# Bank = 1, Pin name =

LOC = "G18"; # Bank = 1,

Pin name = IP, Type = INPUT,

= 1, Pin name = IP, Type = INPUT,

= 0, Pin name = IO_L25P_0, Type = I/O,

= 0, Pin name = IO_L05N_0/VREF_0, Type

= 1, Pin name = IO_L09N_1/A11, Type = D

= 1, Pin name = IO_L05N_1/VREF_1, Type

= 1, Pin name = IO_L11N_1/A9/RHCLK1, Ty

= 1, Pin name = IO_L02P_1/A14, Type = D

LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O,

= 1, Pin name = IO_L20N_1, Type = I/O,

##JD - NOTE: For other JD pins see LD(3:0)

above under "Leds"

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