International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org

Volume 5, Issue 12, December 2016

ISSN 2319 - 4847

Performance Analysis Of Low Power Using Hybrid

And Subthreshold Adiabatic Logic For Digital
Circuit
S.Yamuna1, Dr.Deepa Jose2
1

PG student,Centre for Excellence in VLSI Design,

Department of Electronics and Communication engineering,
KCG College of Technology, Chennai-97.
2

Associate Professor, Centre for Excellence in VLSI Design,

Department of Electronics and Communication engineering,
KCG College of Technology, Chennai-97.

ABSTRACT
By using CMOS logic and transmission gate logic, a hybrid 1-bit full adder is designed, which is reported in this paper. The
design is first implemented for 1-bit full adder and then extended for application of 4-bit Ripple Carry Adder(RCA).The
Modification in the 4-bit Ripple Carry Adder is done by using Subthreshold adiabatic logic(SAL) circuits.It is analyzed to
make great improvement in ultra low power circuit design. When comparing with the existing full adder designs, the present
implementation was found to offer significant improvement in terms of power.After the implementation, the comparison of
power is made between Hybrid logic and the Subthreshold adiabatic logic for 4-bit Ripple Carry Adder.Hence, 18% of power is
reduced using SAL logic. The circuit is simulated using Cadence Virtuoso tool in 180nm technology.

Keywords: Hybrid Logic, Low Power, Subthreshold Adiabatic Logic.

1. INTRODUCTION
Full adders, is one of the most important block of all the VLSI circuitapplications, it is the main domain for the
researchers. For implementing1-bit full adder, different logic styles are used each having itsown merits and
demerits.All these designs are classified into two categories: 1. static design and 2. dynamic design. Static full adders
are generally simple with less power consumption but the requirement of chip area is larger compared with its
dynamicdesign.By using more than one logic style for the implementation is known as hybrid-logic design style[1-5].
The features of different logic styles of these designs is used to improve the performance of the full adder.The merits
of standard complementary CMOS style-based adders with 28 transistors are its robustness against transistor sizing
and voltage scaling; the requirement of buffers and high input capacitance are the demerits of this design.The other
logic style is CPL, it shows good voltage swing restoration employing32 transistors. The disadvantages of the CPL are
its highswitching activity and high transistor count [5-11]. So, it is not an appropriate choice for low-power
applications. The main disadvantage of CPL is voltage degradation. It uses only20 transistors for full adder
implementation. Later, the hybrid logicstyle is used to improve the performance of power.
The knowledge about power dissipation, leakage current, and noise immunity is required to analyze and design of
SAL. The behaviors of adiabatic logic in subthreshold region is discussed in this paper. To analyze the workability of
adiabatic logic circuits in subthreshold region, here 4-bit Ripple Carry Adder is used as a reference circuit.

2. METHODOLOGY
2.1 HYBRID FULL ADDER
The full adder circuit is designed by three Modules as shown in Fig. 1(a). Module 1 and module 2 represents the
XNOR modules to generate the sum signal (SUM) andmodule 3 to generate the output carry signal (Cout). Here, each

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 5, Issue 12, December 2016

ISSN 2319 - 4847

module is designed individually. So that the entire adder circuit is optimized in terms of power. These modules are
explained below in detail.
In the proposed full adder circuit, the power consumption of the entire adder circuit depends on XNOR module. The
modified XNOR circuit is shown in Fig. 1(b) where the power consumption is reduced mainly by the use of weak
inverter. It is formed by transistors Mp1 and Mn1 [Fig. 1(b)]. Output signals is generated by level restoring transistors
Mp3 andMn3 [Fig. 1(b)]. The modified XNOR presented in this paper gives low-power and high-speed compared with
conventional full adder.

Fig.1 (a) Schematic structure of full adder.

(b) XNOR module.
(c) Carry generation module.
In the proposed circuit, the output carry signal is generated by the transistors Mp7, Mp8, Mn7, and Mn8 as shownin
Fig. 1(c). Mn7 and Mp7 represents singletransmission gate, theinput carry signal (Cin) propagates only through it.
Which reduce the overall carry propagation path significantly. In strong transmission gates,channel width of
transistorsis made large.The main use of strong transmission gates is to furtherreduction in propagation delay of the
carry signal

Fig. 2. Detail circuit diagram of proposed full adder.

The detail circuit diagram of the proposed full adder is shown in Fig.2.The output of sum in the full adder is
implemented by XNOR modules. The transistors Mp1 and Mn1 shows an inverter which generate B, it is effectively
used to design the controlled inverter using the transistors Mp2 and Mn2. Controlled inverter has some voltage
degradation problem, to overcome that two pass transistors Mp3 and Mn3 is used. The second stage of XNOR module
to implement the complete SUM function is realized by pMOS transistors and nMOS transistors.
If, A = B, thenCout= B; else,Cout= Cin.
If the inputs are same, then Cout = B, it is implemented by the transmission gate transistors of Mp8 and Mn8. Else, the
input carry signal(Cin) is Cout then it is implemented by another transmission gate transistors of Mp7 and Mn7.

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 5, Issue 12, December 2016

ISSN 2319 - 4847

Fig. 3 4-bit Ripple Carry Adder

The implementation of hybrid logic style in 1-bit full adder consumes less power when compared with the
conventional full adder. So, it is applied to the application of 4-bit Ripple Carry Adder. Fig.3 shows the 4-bit Ripple
Carry Adder
2.2 SUBTHRESHOLD ADIABATIC LOGIC
Basic Model of MOSFET in Subthreshold Region
Using EKV model, the IV characteristics of the subthresholdpMOS device can be expressed by
ISub= I0e(VSG|VTH|)/n pVT (1 eVSD/VT)
whereI0= 2ppCox(W/L)V2T VSG, VSD, and VTH aresource to gate, source to drain, and threshold voltage ofpMOS,
respectively. VT= (kT/q) is thermal voltage, pissubthreshold slope factor, and pis the mobility of pMOSdevice. In
subthreshold regime, the threshold voltage (VTH) depends on source-to-drain voltage (VSD) through body effectand
drain-induced barrier lowering. Considering these effects,threshold voltage can be expressed as follows:
VTH= VTO VSB VSD.
Here, VTO is the threshold voltage at zero bias and and are the body effect and drain-induced barrier lowering
coefficient, respectively. The Drain Induced Barrier Lowering coefficient () which is a unitless quantity, can be
expressed as
= 1/2 cosh(Leff/2lt )
wherelt= (SiToxXDep/ox)1/2 and
=
ISUB= KPexp(VSG/nPVT)(1 exp(VSD/VT))
whereKP= I0 exp(VTO VSD/nPVT ). For the sake of simplicity, let us further simplify the magnitude of Kpby
assuming, VSD/n pVT-1

Fig. 4.Logical structure of basic SAL logic gates.

2.3 SUBTHRESHOLD ADIABATIC LOGIC-BASED 4-BIT RCA

To analyse the workability of proposed logic, here SAL-based 4-bit RCA is designed. By using the SAL based standard
library gates like buffer/inverter, AND, OR, NAND, NOR, which are necessary to implement the 4- bit RCA. Fig 4
shows the structure of SAL based logic gates. This logic structure requires either the pull-up or pull-down network of
static conventional logic. For example, implement a NAND or a NOR gate, the pull-up network is placed between the
supply clock and the output load capacitors.

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 5, Issue 12, December 2016

ISSN 2319 - 4847

Fig. 5.Logic structure of 4-bit CLA.

In NAND structure, the output node voltage will follow the supply clock closely, and we get a triangular output
waveform , for every input combination except A = B = 1. When A = B = 1 leakage currents will flow through parallel
pMOS transistor. In the load capacitor , a very small amount of charge will be stored. The structure of 4-bit RCA is
shown in Fig.5

3. RESULT AND OUTPUT

1-bit Full adder is implemented by using Hybrid logic and the Subthreshold Adiabatic Logic(SAL). In this the power
consumption is reduced in SAL logic and it is extended to the application of 4-bit Ripple Carry Adder(RCA). The
power consumption of Hybrid and SAL logic are shown in tabular format. The simulation and the Output Waveform
is shown below.

Fig. Schematic of 1-bit Hybrid Full adder

Fig. Schematic of 1-bit SAL Full adder

Fig. Schematic of 4-bit RCA of Hybrid logic

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 5, Issue 12, December 2016

ISSN 2319 - 4847

Fig. Schematic of 4-bit RCA of SAL logic

Fig. Output Waveform of 4-bit RCA of Hybrid logic

Fig. Output Waveform of 4-bit RCA of SAL logic

Table 1: Power consumption of full adder using Hybrid and SAL logic

Table 2: power consumption of 4-bit RCA using Hybrid and SAL logic

5. CONCLUSION
In this paper, a low-power hybrid 1-bit full adder has been designed and it is extended for 4-bit RCA. The simulation
was carried out using standard Cadence Virtuoso tools with 180-nm technology and compared with 4 bit RCA of
subthreshold adiabatic logic design. SAL has been presented in this paper to advance the ultralow power research.
The simulation results established that the proposed adder offered improved Power compared with the earlier reports.

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 5, Issue 12, December 2016

ISSN 2319 - 4847

This proposed logic scheme can be used in future power-saving embedded circuits and mainly for power efficient
devices where ultralow power and longevity are thepivotal issues.

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