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VDSS
RDS(on)
ID
24 V
< 0.0105
50 A
2
1
IPAK
TO-251
(Suffix -1)
DPAK
TO-252
(Suffix T4)
DESCRIPTION
The STD50NH02L utilizes the latest advanced design
rules of STs proprietary STripFET technology. This is
suitable fot the most demanding DC-DC converter
application where high efficiency is to be achieved.
APPLICATIONS
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY DC/DC CONVERTES
Ordering Information
SALES TYPE
STD50NH02LT4
STD50NH02L-1
MARKING
D50NH02L
D50NH02L
PACKAGE
TO-252
TO-251
PACKAGING
TAPE & REEL
TUBE
Parameter
Drain-source Voltage Rating
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 k)
Gate- source Voltage
Drain Current (continuous) at TC = 25C
Drain Current (continuous) at TC = 100C
Drain Current (pulsed)
Total Dissipation at TC = 25C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
September 2003
Value
30
24
24
20
50
36
200
Unit
V
V
V
V
A
A
A
60
0.4
280
W
W/C
mJ
-55 to 175
C
1/12
STD50NH02L
THERMAL DATA
Rthj-case
Rthj-amb
Tl
Max
Max
2.5
100
275
C/W
C/W
C
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 25 mA, VGS = 0
VDS = 20 V
VDS = 20 V
Gate-body Leakage
Current (VDS = 0)
VGS = 20V
Min.
Typ.
Max.
24
Unit
V
TC = 125C
1
10
A
A
100
nA
Max.
Unit
ON (4)
Symbol
Parameter
Test Conditions
VGS(th)
VDS = VGS
ID = 250 A
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
VGS = 5 V
ID = 25 A
ID = 12.5 A
Min.
Typ.
1.8
0.0085
0.012
0.0105
0.020
Typ.
Max.
Unit
DYNAMIC
Symbol
Test Conditions
gfs (4)
Forward Transconductance
VDS = 15 V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
RG
2/12
Parameter
ID = 25 A
Min.
27
1400
400
55
pF
pF
pF
STD50NH02L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
td(on)
tr
ID = 25 A
VDD = 10 V
RG = 4.7
VGS = 10 V
(Resistive Load, Figure 3)
10
130
Qg
Qgs
Qgd
24
5
3.4
Output Charge
VDS= 16 V
9.4
Qoss (5)
VGS= 0 V
Max.
Unit
ns
ns
32
nC
nC
nC
nC
SWITCHING OFF
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
ID = 25 A
VDD = 10 V
RG = 4.7,
VGS = 10 V
(Resistive Load, Figure 3)
Typ.
Max.
Unit
27
16
21.6
ns
ns
Typ.
Max.
Unit
50
200
A
A
1.3
Parameter
ISD
ISDM
Source-drain Current
Source-drain Current (pulsed)
VSD (4)
trr
Qrr
IRRM
Test Conditions
Forward On Voltage
ISD = 25 A
di/dt = 100A/s
ISD = 50 A
VDD = 20 V
Tj = 150C
(see test circuit, Figure 5)
Min.
VGS = 0
36
36
2
ns
nC
A
Thermal Impedance
3/12
STD50NH02L
Output Characteristics
Transfer Characteristics
Transconductance
Capacitance Variations
4/12
STD50NH02L
Normalized Gate Threshold Voltage vs Temperature
5/12
STD50NH02L
Fig. 1: Unclamped Inductive Load Test Circuit
6/12
STD50NH02L
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
6.2
0.236
0.244
6.4
6.6
0.252
0.260
4.4
4.6
0.173
0.181
15.9
16.3
0.626
0.641
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
0.031
0.039
A1
C2
A3
B3
=
=
B2
B5
D
B6
L2
L1
0068771-E
7/12
STD50NH02L
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
6.2
0.236
0.244
6.4
6.6
0.252
0.260
4.4
4.6
0.173
0.181
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
0.023
0.039
A1
C2
A2
DETAIL "A"
L2
=
=
E
=
B2
DETAIL "A"
L4
0068772-B
8/12
STD50NH02L
9/12
STD50NH02L
APPENDIX A
Buck Converter: Power Losses Estimation
SW1
SW2
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is er moved to allow for a safer working junction
temperature.
The low side (SW2) device requires:
Small Rg and Ls to allow higher gate current peak and to limit the voltage
feedback on the gate
10/12
STD50NH02L
Pconduction
Pswitching
R DS(on)SW1 * I 2L * d
R DS(on)SW2 * I 2L * (1 d )
IL
Ig
Recovery
Not Applicable
Conduction
Not Applicable
Vf(SW2) * I L * t deadtime * f
Pgate(Q G )
Q g(SW1) * Vgg * f
Q gls(SW2) * Vgg * f
PQoss
Vin * Q oss(SW1) * f
Vin * Q oss(SW2) * f
Pdiode
Parameter
d
Qgsth
Qgls
Pconduction
Pswitching
Pdiode
Pgate
PQoss
Vin * Q rr(SW2) * f
Meaning
Duty-cycle
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
11/12
STD50NH02L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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2003 STMicroelectronics - All Rights Reserved
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