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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2582206, IEEE
Transactions on Power Electronics
I. INTRODUCTION
With the increasing demands for power supplies in
computer, telecom, electric vehicle, and other similar areas
where low voltage and high current are needed, the traditional
dc power distribution system (DC PDS) is gradually unable to
meet the requirements due to its insufficiencies such as more
This work was supported in part by the National Natural Science
Foundation of China No. 61573155, in part by Guangdong Natural Science
Foundation No.2016A03031358, in part by Guangdong Science and
Technology Planning Project No.2016A010102007, and in part by Science
and Technology Program of Guangzhou No. 201607010209. (Corresponding
author: Jun Zeng)
J. Liu is with the School of Automation Science and Engineering, South
China University of Technology, Guangzhou 510640, China (e-mail:
jf.liu@connect.polyu.hk).
J. Wu and J. Zeng are with the New Energy Research Center, South China
University of Technology, Guangzhou 510640, China (e-mail:
jialei_wu@139.com; junzeng@scut.edu.cn).
H. Guo is with Guangzhou Institute of Energy Conversion, Chinese
Academy
of
Sciences,
Guangzhou
510640,
China
(e-mail:
guohf@ms.giec.ac.cn).
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2582206, IEEE
Transactions on Power Electronics
performance
evaluations
including
simulation
and
experimental results are presented in Section V, followed by
concluding remarks.
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2582206, IEEE
Transactions on Power Electronics
current paths for each voltage level in the positive half cycle. It
can be found that the output voltage levels remain the same
regardless of the directions of the load current. In other words,
proposed topology can be used as an independent inverter.
TABLE I
SWITCHING PATTERNS AND STATES OF THE DIODES AND CAPACITORS AT EACH VOLTAGE LEVEL
Switches in HBC
Switches in DSCC
Diodes
Capacitors
voltage
levels
S1
S2
S3
S4
S5
S6
S7
S8
S9
D1
D2
C1
C2
2Vdc
1
0
0
1
1
1
1
0
0
0
0
D
D
3Vdc/2
1
0
0
1
1
1
0
0
1
0
1
D
D
Vdc
1
0
0
1
1
0
0
1
0
1
0
C
C
Vdc/2
1
0
0
1
0
0
0
1
1
0
1
D
D
0
0
1
0
1
0
0
0
1
1
0
0
-Vdc/2
0
1
1
0
0
0
0
1
1
0
1
D
D
-Vdc
0
1
1
0
1
0
0
1
0
1
0
C
C
-3Vdc/2
0
1
1
0
1
1
0
0
1
0
1
D
D
-2Vdc
0
1
1
0
1
1
1
0
0
0
0
D
D
where symbols of 1 or 0 in the switches column indicate that the switches are turned on or turned off; symbols of 1 or 0 in the diodes column indicate that the
diodes are forward passed or reverse biased; symbols of C, D or in the capacitors column indicate that the capacitors are charged, discharged or unchanged.
(a)
(b)
(c)
(d)
(e)
(f)
(h)
(i)
(g)
Fig. 3. Current paths for different output voltage levels. (a) Forward current path at level 2Vdc. (b) Forward current path at level 3Vdc/2. (c) Forward current path
at level Vdc. (d) Forward current path at level Vdc/2. (e) Forward current path at level 0. (f) Reverse current path at level 2Vdc. (g) Reverse current path at level
3Vdc/2 (h) Reverse current path at level Vdc. (i) Reverse current path at level Vdc/2.
C. Modulation Analysis
Fig.4 shows the operational principles of proposed inverter.
The nine-level staircase output can be synthesized by four
quasi-square waves voi (i=1, 2, 3, 4), whose amplitudes and
conducting angles are Vdc/2 and i, correspondingly.
Obviously, the angles should satisfy
0 1 <2 3 4 5 90
(1)
The Fourier decomposition of each quasi-square waveform is
voi
2Vdc
k 1,3,
cos ki
k
sin kt
(2)
vo
2Vdc
k 1,3 i 1
cos ki
k
sin kt
(3)
vof
2Vdc
cos i sin t
(4)
i 1
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Transactions on Power Electronics
M of
1 4
cos i
4 i 1
4 cos k
k i
k 3,5 i 1
THD
(5)
2
100%
(6)
cos k
k 1
(7)
1 9.84 2 20.37
3 40.05 4 60.42
(8)
io
2 dt
3
io
dt
io
d t
2
4
(9)
Vdc
4 33 5 4
4 f o Ro
(10)
Vdc
4 33 54
4 f o Ro C
(11)
Cmin
Vdc
4 33 5 4
4 f o Ro U ripple
(12)
V '
Vdc
2 1
2 f o Ro C
(13)
Prip f o C ( V 2 V '2 )
(14)
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Transactions on Power Electronics
5
Capacitance versus load resistance at 1 kHz
rD rS
req rD 3rS
r ESRc
D
3rS
2
2 ESRc 4r
5000
1% voltage ripple
5% voltage ripple
10% voltage ripple
4000
3000
2000
1000
0
0
i 1
i2
(17)
i3
i4
20
30
40
50
Load resistance Ro/
60
2vo
(18)
Vdc
From Fig.4 and Fig.6, the average conducting loss can be
calculated by
2
2 4 Veq VDeq
req i 1 i
Pcon
(19)
i 1 req Ro
(a)
Capacitance versus output frequency with 32 load
5000
i0
1% voltage ripple
5% voltage ripple
10% voltage ripple
4000
3000
2000
1000
0
0
1000
2000
3000
4000
Output frequency fo/Hz
5000
(b)
Fig. 5. Curves of minimum capacitance versus load resistance and output
frequency. (a) Curves of minimum capacitance versus load resistance at
frequency 1 kHz. (b) Curves of minimum capacitance versus output
frequency with rated load resistance of 32 .
0
V
dc
2
Veq Vdc
3V
dc
2
2V
dc
VDeq
i0
i 1
i2
(15)
Ro
45 f 0 CdsVdc 2
2
(21)
i4
req
Veq
Pswitch
i3
i 0, 2, 3
VD
2VD i 1
i4
0
VDeq
Po
Prip Pcon Psw Po
(22)
TABLE II
DETAILED OPERATIONAL PARAMETERS OF EACH SWITCH
Switches in HBC
Switches in DSCC
Parameters
S1~S4
S5
S6
S7
S8
S9
fs
fo
2fo
2fo
2fo
2fo
6fo
Vb
2Vdc
Vdc/2 Vdc Vdc/2 Vdc Vdc/2
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2582206, IEEE
Transactions on Power Electronics
(a)
TABLE III
PARAMETER COMPARISONS WITH THE TOPOLOGIES IN [21]-[24]
Proposed Inverter Inverter Inverter Inverter
Parameters
inverter
in [21]
in [22]
in [23]
in [24]
Nsource
1
1
2
1
1
Ncap
2
3
2
3
3
Nswitch
9
13
12
10
8
Ndiode
2
0
2
3
6
PIV
2Vdc
4Vdc
2Vdc
4Vdc
4Vdc
where Nsource, Ncap, Nswitch, Ndiode and are the numbers of voltage sources,
electrolytic capacitors, switches, and diodes, correspondingly.
(b)
Fig. 7. Simulation waveforms of driving signals.
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Transactions on Power Electronics
(a)
(b)
Fig. 8. Simulation waveforms of output voltages and currents under different
load-types. (a) Ro = 32 . (b) ZL = 24+j20 Ro =24 Lo = 3.2
mHL31.2= 40.
B. Experimental Results
To further verify the feasibility of proposed HF inverter, an
experimental prototype is implemented as shown in Fig.11.
The circuit parameters are set the same as those listed in Table
IV and the specifications of the used devices are tabulated as
Table V.
Fig. 12. Experimental results of the output voltage and load current with a
pure resistor.
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Transactions on Power Electronics
(a)
REFERENCES
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[2]
(b)
Fig. 13. Experimental results of the two capacitors voltages and currents.
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
(a)
[11]
[12]
[13]
[14]
(b)
Fig. 14. Experimental results of the voltages on switches.
VI. CONCLUSION
[15]
[16]
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Transactions on Power Electronics
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