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10.1109/TPEL.2015.2399853, IEEE Transactions on Power Electronics
I. INTRODUCTION
1
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Pin1
C1
S1
U1
U1
C2
D2
C3
U2 U2
C4
S2
Po
Pin 2
D1
D3
Uc1
Uc2
C1
C2
(a)
D1
U1
D2
Pin1
S1
U1
C2
C1
D2
Po
D3
U2 U2
Pin 2
S2
C4
C3
D4
(b)
Fig.2 Two SDCVA structures: (a) parallel SDCVA; (b) serial SDCVA
2
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L1
u L1
U in1
iDo
iS1
C2
U1
C1
U1
C4
U2
Co
C3
A.
Operation Principle
Fig.3 shows the basic topology of the double-input
converter based on the parallel SDCVA, which is made of
two switched-diode-capacitor cells in parallel. In the circuit
topology, two switched-diode-capacitor cells are respectively
labelled as cell 1, cell 2, and the two input sources are
respectively labelled as input source 1, input source 2. Cell 1
and cell 2 share the same diode D2. As the converter feeds
power to the load R individually, the specific two analysis
processes when input source 1 and input source 2 respectively
works independently are presented below.
L1
u L1
D1
U1
U1
Uin1
S1
Do
C2
C1
D2
C3
L2
uL 2
Co
U2 U2
C4
S2
R Uo
Uin2
D3
Uo
(a)
i1
U in1
iDo 0
L1
u L1
C1
U1
C2
U1
Co
U2
C3
U2
C4
Uo
U2
(b)
Fig.4 Equivalent circuits when input source 1 works independently: (a) stage
1; (b) stage 2.
uL1 Uin1
(2)
In the serial-parallel pathway of capacitors C1-C4, the
output voltage is achieved as U1+2U2 or 2U1+U2:
Uo U1 2U 2 2U1 U 2
(3)
Stage 2: When switches S1 and S2 are turned off (Fig.4(b)),
diodes D1, D2, D3 are forwarded while diode Do is
reverse-biased. During the switch-off period. Capacitors C1,
C2 of cell 1 and capacitors C3, C4 of cell 2 are respectively
connected in parallel, making each capacitor voltage of each
cell equal. The voltage across the inductor L1 is written by:
uL1 Uin1 U1
(4)
In addition, by applying the principle of voltage-second
balance on the inductor L1 according to (2)-(4), we attain the
capacitor voltage of the parallel SDCVA and the output
voltage of the double-input step-up converter based on the
parallel SDCVA as follows:
3
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U1 U 2
1
U in1
1 D
(5)
3
(6)
U in1
1 D
2) When input source 2 works independently
Operation principle of the converter based on the parallel
SDCVA when input source 2 works independently is similar
to that when input source 1 works independently. Therefore,
it is easy to obtain the capacitor voltage and the output
voltage of the converter as follows:
1
(7)
U1 U 2
U in 2
1 D
3
(8)
Uo
U in 2
1 D
Uo
(i 1, 2...N )
U ini
1 D
B. Performance Analysis
As the converter could attain a similar output effect no
matter which input source works independently, the operating
mode when input source 1 works independently is taken as an
example, to do detailed performance analysis below. Firstly,
the transient characteristic of the converter is analyzed in
detail. Then, the current ripple, voltage ripple, voltage stress
and current stress are respectively discussed. Finally, a novel
voltage balance system is proposed to extend the application
of the multi-input converter based on the parallel SDCVA.
1) Transient circuit characteristic
some definitions are given:
C1 C2 C3 C4 C
U1 U 2 U c
I1min I1 i1
I1max I1 i1
U c min U c uc
U c max U c uc
U in1
U
t I1 i1 in1 t
L1
L1
iDo =
(11)
2 duc
C
5
dt
(14)
uc U c max e
15
t
R
2C +15Co )
(15)
iDo
t
6CU c max
e R2C +15Co )
R(2C +15Co )
(16)
U in1 U c
U Uc
t I1 i1 in1
t
L1
L1
(17)
(10)
where the four capacitors C1-C4 have the same capacitance C;
Uc represents the capacitor voltage value of the parallel
SDCVA; Ucmin, Ucmax represent the minimum value and
maximum value of the capacitor voltage; uc represents the
capacitor voltage ripple; I1 represents the average current of
the inductor L1; I1min and i1 respectively represents the
minimum value of I1 and the current ripple of the inductor L1.
During the stage 1, Uin1 is applied to the inductor L1 and
the input current i1 can be written by:
i1 I1min
d 2uc
uc U in1
dt
(20)
1
t)
2 L1C
L1
1
I1max sin(
t ) U in1 (21)
2C
2 L1C
U in1
DTs
2 L1
(22)
According to (22), the expression of input current ripple is
similar to that of the conventional boost converter.
In addition, according to the definitions mentioned in (10),
the four capacitors have the same capacitance C. An equation
can be obtained based on the energy conservation principle:
4
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1
3 C (U 2c max U 2c min ) 3C (U U )(U U ) U 2
c max
c min
c max
c min
2
o
Ts
2Ts
R
(23)
In addition,
U c max U c min 2U c
(24)
U c max U c min
3U in1Ts
2
2(1 D) RC
(25)
15 DTs
1
3
uo1 (3U c max 3U c max e R2C +15Co ) ) U c max (1 e R2C +15Co ) ) (26)
2
2
As only the capacitor Co feeds power to the load during the
switch-off period, it is easy to attain the output voltage ripple
uo2 during the switch-off period as follows:
uo 2
(1 D)U oTs
2 RCo
I1min
(28)
I1max
Uin1
L1
i1
Uin1 U1
L1
DTs
(1 D)Ts 2Ts
Ts
(a)
uo (t )
3U c max e
15
t
R
2C +15Co )
uo1
uo 2
0
U o
RCo
DTs
iDo
15
6CU
t
c max
e R2C +15Co )
R
2C +15Co )
Ts
(b)
Fig.5 Key waveforms: (a) input inductor current; (b) output voltage.
0 t DTs
(29)
(30)
DTs t Ts
15 DTs
(1 D)U oTs
3
uo uo1 uo 2 U c max (1 e R2C +15Co ) )
2
2RCo
I1
U in1
U in1
0 t DTs
I1 2 L DTs L t
1
1
i1
I U in1 DT DU in1 (t DT ) DT t T
1
s
s
s
s
2 L1
(1 D) L1
(27)
i1 (t )
3) Component stress
In the parallel SDCVA, all switches and diodes are
subjected to a low voltage stress, which is described by the
product of the input source voltage and 1/(1-D). Combining
(5) and (7), it is clear to know that the capacitors have the
same voltage stress as the switches and diodes. As a result,
small and equal voltage stress of switches, diodes and
capacitors enables the use of the components with a low rated
voltage and low RDS-ON, which greatly reduces losses.
Combing (11), (16), (17), and (22), the input inductor
current i1 and the current iDo through the diode Do can be
respectively described as follows:
U c min U in1
2 L1C
sin(
duc I1max
1
cos(
t)
dt
2C
2 L1C
1
2 L1C
t)
(33)
5
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C1
S1
Uin1
Do
D1
U1
U1
C2
D2
L2
uL 2
C3
S2
U in 2
Co
D3
U2 U2
R Uo
C4
D4
C1 C2 Ccell1
C3 C4 Ccell 2
(34)
L1
u L1
U in1
C2
U1
C1
U1
L2
R Uo
Co
uL 2
U in 2
C4
U2
C3
U2
(a)
L1
u L1
Uin1
C1
U1
C2
U1
Co
L2
uL 2
U in 2
C3
U 2 C4
Uo
U2
(b)
Fig.7 Equivalent circuits when the converter is under the operating mode of
simultaneous supplying power: (a) stage 1; (b) stage 2.
uLi Uini (i 1, 2)
(35)
Since all capacitors of the SDCVA are connected in series
to feed the load, the output voltage of the converter based on
the serial SDCVA can be written by:
6
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U o 2U1 2U 2
(36)
Stage 2: When switches S1, S2 are turned off (Fig.7(b)),
capacitors C1, C2 of cell 1 and capacitors C3, C4 of cell 2 are
respectively connected in parallel, making each capacitor
voltage of each cell equal. During this period, the voltages
across L1 and L2 are respectively expressed as follows:
uLi Uini Ui (i 1, 2)
(37)
N
2
U ini
1 D i 1
(40)
1
U in1
1 D
(41)
1
U in 2
1 D
(42)
1
1
1
U in1
U in 2 U o
1 D
1 D
2
(43)
ii
U ini
DTs
2 Li
(i 1, 2)
(44)
As the two input sources work together in series, their
average input currents are equal:
I1 I 2
(45)
In addition, by applying the energy conservation principle,
we attain:
I1U in1 I 2U in 2
U o2
R
(46)
Combining (45) and (46), two average input currents are
achieved as follows:
I1 I 2
2U o
(1 D) R
(47)
U1min U1 u1
U1max U1 u1
U 2 min U 2 u2
U 2 max U 2 u2
C1 C2 Ccell1
C3 C4 Ccell 2
(48)
where U1min, U1max respectively represents the minimum value
and maximum value of capacitor voltage of cell 1; U2min,
U2max represent the minimum value and maximum value of
capacitor voltage of cell 2; u1, u2 represent the capacitor
voltage ripples of cell 1 and cell 2.
In terms of the capacitor voltage of cell 1, an equation can
be obtained by applying the energy conservation principle:
1
(49)
2 Ccell1 (U 21max U 21min ) / Ts U in1 I1
2
In addition, the minimum value and the maximum value of
the capacitor voltage of cell 1 has the relation as follows:
(50)
By substituting (50) into (49), the capacitor voltage ripple
of cell 1 can be attained as follows:
U
U1min
U oTs
(51)
u1 1m ax
2
2 RCcell1
By applying the computing method above, the capacitor
voltage ripple of cell 2 can be attained as follows:
U
U 2 min
U oTs
(52)
u2 2 m ax
2
2 RCcell 2
Like the double-input step-up converter based on the
parallel SDCVA, the load of the converter based on the serial
SDCVA is always charged by capacitors. Therefore, the
output voltage ripple can also be divided into two different
parts: voltage ripple uo1 during the switch-on interval and
voltage ripple uo2 during the switch-off interval, shown in
Fig.8. A little difference is that during the switch-on interval,
the load of the converter based on the serial SDCVA is fed by
all capacitors while the load of the converter based on the
parallel SDCVA is fed by three capacitors.
During the switch-on period, as the output voltage equals
to the accumulation of all capacitor voltages, it reaches the
maximum value 2(U1max+U2max) at the beginning of the
switching period and the minimum value 2(U1min+U2min) at
the end of the switching period. Combining (49) and (50), the
7
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o s
2
RCcell1 RCcell 2
(53)
Also, uo2 during the switch-off period could be easily
deduced like (27):
(1 D)U oTs
uo 2
2 RCo
(54)
Therefore, the output voltage ripple can be achieved:
uo uo1 uo 2
U oTs
UT
(1 D)U oTs
o s
RCcell1 RCcell 2
2 RCo
(55)
uo (t ) 2(U1max U 2max )
2(U1min U2min )
uo1
uo 2
U o
RC o
DTs
Ts
A. Comparative Analysis
A comparison of voltage stresses among the two proposed
converters and the traditional Boost converter is presented in
Table I. It can be seen from Table I that the voltage gains of
the two proposed converters are both higher than that of the
traditional Boost converter. And in the double-input step-up
converter based on the parallel SDCVA, the component
voltage stress of each cell is the product of its corresponding
input source voltage and 1/(1-D), which is also 1/3 of its
output voltage. In addition, the voltage stress of the output
diode Do is also 1/3 of its output voltage. In the double-input
step-up converter based on the serial SDCVA, the component
voltage stress of each cell is the product of its corresponding
input source voltage and 1/(1-D). And the component voltage
stress of each cell and the voltage stress of the output diode
Do are all half of its output voltage. On the whole, if these
three converters output a same voltage, the voltage stresses of
all components of the proposed converters are smaller than
that of the traditional Boost converter. Low voltage stress
across component will reduce cost and size of circuit designs.
TABLE I
Comparison of voltage stresses among the two proposed converters and the traditional Boost converter
The proposed double-input step-up converters
Output voltage
Voltage stress of switches, diodes, capacitors
Uo
Cell 1
Cell 2
Do
The converter based on
Individual/
Input source 1
3Uin1/(1-D)
1/3 Uo
1/3 Uo
1/3 Uo
the parallel SDCVA
Simultaneous
Input source 2
3Uin2/(1-D)
1/3 Uo
1/3 Uo
1/3 Uo
The converter based on
Simultaneous
Input sources 1, 2
(2Uin1+2Uin2)/(1-D)
Uin1/(1-D)
Uin2/(1-D)
1/2 Uo
the serial SDCVA
Individual
Input source 1
2Uin1/(1-D)
1/2 Uo
1/2 Uo
Input source 2
2Uin2/(1-D)
1/2 Uo
1/2 Uo
Traditional boost converter
Uin/(1-D)
Uo
Uo
B. Closed-loop Control
As the two proposed converter topologies are similar, they
can be designed in one variable-structure circuit presented in
Fig.9 by adding three toggle switches Q1, Q2, Q3. The two
converter topologies can be transformed from one to the other
by the on-off transition of these three switches. When Q1, Q2
are both turned on and Q3 is turned off, the circuit is
equivalent to the circuit of the double-input step-up converter
based on the parallel SDCVA. When Q1, Q2 are both turned
off and Q3 is turned on, the circuit is equivalent to the circuit
of the double-input step-up converter based on the serial
SDCVA. In the experimental prototype, these three switches
are implemented based on toggle switches.
To make the proposed converters operate stably when the
input voltage varies, a voltage closed-loop control is essential.
Structure diagram of the voltage closed-loop control circuit
for the proposed converters is presented in Fig.10, in which
an a voltage error signal is obtained by taking the referring
signal of the output voltage Uref to subtract the sampling
output voltage, which is designed to be Uo/240, and then
passes through the proportional-integral (PI) regulator to
compare with the carrier signal to achieve the driving signal
for the two switches S1, S2. It should be noted that the driving
signal must be isolated during the experimental research,
because the switches S1, S2 do not share the same ground with
the output port. But on the whole, the control circuit is simple
S1
Uin1
Do
D1
C1
U1
U1
C2
D2
Q2
Q1
Co
Q3
L2
uL 2
D3
S2
U in 2
R Uo
C3
U2
U2
C4
D4
U ref
Isolated driving 1
PI
S1
PWM
Isolated driving 2
S2
8
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Main Circuit
Voltage Measurement
(a)
Three Cells
Toggle Switches
Driven Circuit
Output Port
(b)
Fig.11 Experimental prototypes: (a) the proposed converter prototypes; (b)
the voltage balance circuit for three batteries.
TABLE II
Experimental parameters
Components
Switching frequency fS
Inductors L1, L2 in Section III
Inductors L1, L2 in Section IV
Load R
Control circuit
Optocoupler
High frequency switches S1, S2
Switches Q1, Q2, Q3
Diodes D1, D2, D3, D4, D5, D6
Output diode Do
Capacitors C1, C2, C3, C4, C5, C6
Output filter capacitor Co
Three lead-acid rechargeable batteries
A.
Rated Value
30kHz
900uH
800uH
1000 Ohm
TMS320F2812
TLP250
IRFP250
toggle switch
MUR420
MUR440
100uF/250V
470uF/470V
12V/7AH
9
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i2.5A/
div
L1
i2.5A/
div
L1
U o (100 V/ div)
U o (100 V/ div)
driven signal
5V/div
Voltage Gain
driven signal
5V/div
20us / div
20us / div
(a)
(b)
Duty-cycle D
uS 1 (100 V/ div)
i1A/
div
L1
U o (100 V/ div)
uS 2 (100 V/ div)
driven signal
5V/div
10us / div
20us / div
(c)
(d)
U c1 (100 V/ div)
U c 2 (100 V/ div)
uD2 (100 V/ div)
U c 3 (100 V/ div)
uD3 (100 V/ div)
U c 4 (100 V/ div)
10us / div
10us / div
(e)
(f)
U100V/
div
o
U100V/
div
o
100mS / div
U o (200 V/ div)
driven signal
5V/div
20us / div
50mS / div
(g)
(h)
Fig.12 Experimental results when the input source 1 works independently: (a)
33V input voltage; (b) 40V input voltage; (c) 50V input voltage; (d)
waveforms of S1, S2 and Do; (e) waveforms of D1, D2 and D3; (f) capacitor
voltage waveforms; (g) the input voltage jumps from 33V to 40V; (h) the
input voltage jumps from 40V to 33V.
iL2.5A/
div
2
Experimental Value
iL2.5A/
div
2
U o (200 V/ div)
driven signal
5V/div
20us / div
(a)
(b)
Fig.13 Experimental results when the input source 2 works independently: (a)
33V input voltage; (b) 50V input voltage.
10
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U c1 (100 V/ div)
U c 2 (100 V/ div)
U o (200 V/ div)
U c3 (100 V/ div)
U c 4 (100 V/ div)
20uS / div
20uS / div
(a)
(b)
Fig.15 Experimental results when Uin1=30V, Uin2=20V: (a) inductor currents,
output voltage, and driving signal; (b) capacitor voltage.
U o (100 V/ div)
U o (100 V/ div)
i2.5A/div
L1
20uS / div
20uS / div
(a)
(b)
Fig.16 Experimental results when the input source 1 works independently: (a)
50V input; (b) 66V input.
U o (100 V/ div)
U o (100 V/ div)
iL2.5A/div
2
iL 2 (2.5 A/ div)
20uS / div
20uS / div
(a)
(b)
Fig.17 Experimental results when the input source 2 works independently: (a)
50V input; (b) 66V input.
O u tp u t V o lta g e
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Theoretical Value
Experimental Value
Duty cycle D
Fig.18 The graph comparing theoretical and experimental voltage values vs
duty-cycle for the mode of simultaneous supplying power when Uin1=30V
and Uin2=20V.
11
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[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
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