Performance assessment of

graphene-based lateral and

vertical heterostructure
transistors
D. Logoteta, G. Fiori, G. Iannaccone,
University of Pisa
Acknowledgments:

Giuseppe Iannaccone

EC FP7 Project GRADE (n. 317839 )

EC FP7 Project GO-NEXTs (n. 309201)

University of Pisa

The short story

Go lateral, forget vertical

Giuseppe Iannaccone

University of Pisa

K. Yang, Science 2012

(SAIT,Columbia U.,
Samsung)

Giuseppe Iannaccone

Graphene Barristor

University of Pisa

L. Britnell et al.,
Science v. 335,
p. 947, 2011

Britnell et al. Nano Letters 2011

Britnell et al. Science 2011

Giuseppe Iannaccone

University of Pisa

Graphene-base hot electron transistor

S. Vaziri et al.
(KTH,U. Siegen, IHP)
Nano Letters 2012

Giuseppe Iannaccone

University of Pisa

Atomic layers of hBN and graphene domains

L. Ci et al.(Rice) Nat. Mat. 9, 430 (2010)

Absorption rate of BN 5.68 eV Egap
Giuseppe Iannaccone

University of Pisa

Lateral
heterostructure FET

G. Fiori, G. Iannaccone,
Patent Appl. 2011,
Giuseppe
IEDM Iannaccone
2011, ACS Nano 2012

University of Pisa

Lateral G-BN Heterostructures

M.P. Levendorf
Nature 2012
(Cornell)

Giuseppe Iannaccone

University of Pisa

LHFET Experimental Demonstration

Moon et al. (HRL), EDL 34, 1190, 2013

Giuseppe Iannaccone

University of Pisa

Figures of merit from the ITRS 2012

(International Technology Roadmap for Semiconductors)
HP = High Performance Channel length (nm)
VDD (V)
Ioff (nA/A)
Ion (A/A)
PDP (fJ/m)
(ps)
Ion/Ioff
!

LP = Low Power

HP2014

LP2014

HP2018

LP2018

HP2026

LP2026

18
0.82
100
1573
0.47
0.361
15730

19
0.65
5
765
0.29
0.58
153000

12.8
0.73
100
1805
0.31
0.24
18050

13.1
0.57
5
794
0.18
0.4
158800

5.9
0.57
100
2308
0.14
0.1
23080

5.8
0.43
5
666
0.07
0.26
133200

I on = I DS (VGS = 0,VDS = VDD )

I off = I DS (VGS = VDD ,VDS = VDD )

Giuseppe Iannaccone

10

University of Pisa

Device modeling tool: NanoTCAD VIDES

n 3D Non-Equilibrium Green s Functions

(NEGF) solver
n Fully coherent transport
n Generic 3D structures
CNT and GNR FETs (TB atomistic)
Bilayer graphene FETs (TB atomistic)
Semiconductor NW Transistors (EMA
+ TB atomistic)
hBCN

n New version of the code as a python

module all documentation and code

at: http://vides.nanotcad.com and on
the nanohub.org

Giuseppe Iannaccone

11

University of Pisa

Multi-scale
Modeling
A multi-scale approach for
the simulation of
nanoscale devices with
self-extraction of
tight-binding parameters
from ab-initio simulations
1. DFT (Materials
modeling)
Quantum Espresso
2. Wannier 90
3. NEGF-TB
NanoTCAD ViDES
Giuseppe Iannaccone

University of Pisa

Barristor

Sensitivity on oxide thickness, semiconductor material, doping

Giuseppe Iannaccone

13

University of Pisa

Barristor

Delay time is terrible and PDP is poor

Giuseppe Iannaccone

14

University of Pisa

VHFET

Device design space: barrier thickness (NL) and

barriere height (EV) Current modulation is
maximum for thicker and higher barrier
Giuseppe Iannaccone

15

University of Pisa

VHFET

Delay time and PDP are terrible

Giuseppe Iannaccone

16

University of Pisa

LHFET

Every figure of merit is optimized for tB=L

Giuseppe Iannaccone

17

University of Pisa

LHFET

Small dependence on the barrier height

(EV = 0.64 eV corresponds to BC2N)
Giuseppe Iannaccone

18

University of Pisa

Graphene LHFET - Comparison with ITRS 2012

VHFET: = 625 ps

Giuseppe Iannaccone

Barristor: = 160 ps

19

University of Pisa

Conclusion

go lateral, forget vertical

Giuseppe Iannaccone

20

University of Pisa

Conclusion
Both the barristor and the VHFET are intrinsically far
from the ITRS targets (a factor 103 in terms of delay time)
Why: in simple terms, graphene screens the electric field
induced by the gate. It is not a metal (otherwise vertical
device would not work), but almost.
Only the LHFET is promising with respect to CMOS
technology, and has good scaling prospects (in the
optimistic case of our defectless devices)

Giuseppe Iannaccone

21

University of Pisa