Getting into simulation Introduction

(Implementation and Simulation of Mixed Signal Models in VHDL-AMS)

1 Training
1.1

Preface

VHDL-AMS is a hardware description language for mixed signal models. It contains not
only the simultaneous representation of digital and analogue electrical signals, but also
nonelectrical quantities can be described with that. Indeed it is an addition to the classic
VHDL (IEEE 1076-1993) which only enables description of time-, and value-discrete
models. At first VHDL was developed to define a uniform description language for digital
systems and to simplify the simulation and synthesis of digital circuits. Because of the
rapid development in computer technology and more efficient mathematical algorithms it
has become possible to simulate time-continuous analogue systems too. Therefore a
description standard was fixed with the AMS expansion to VHDL (IEEE 1076.1-1999) for
mixed signal models in 1999.
This workshop shall give you an introduction to the modeling with VHDL-AMS. The
hAMSTer tool from SIMEC serves as simulation software. This software is still in
development

and

can

be

downloaded

from

the

Internet

free

of

charge:

http://www.hamster-ams.com.

1.2

Introduction to VHDL-AMS

VHDL is a hardware description language.

All instructions are executed simultaneously (except processes).

1.2.1

Interface description (Entity)

Each component consists of one interface and at least one behaviour description. The
implementation of a component always starts with the definition of its interface.
Description of an interface:
ENTITY example1 IS
GENERIC ( vref : Real: = 10.0;
tau : Real: 8.0 = E 6);
PORT (clk: IN bit;
TERMINAL input: ELECTRICAL;
TERMINAL output: ELECTRICAL);
BEGIN
END ENTITY example1;
The keyword ENTITY means the beginning of the interface description. This is followed
by the name of the component. Finally the description of the interface starts after IS.
The keyword GENERIC indicates values which don't change during the simulation. In
principle these are constants to adjust the characteristics of the component. This is very
meaningful for influencing the parameters in the netlist without doing changes in the
model description itself.
The 'real' interfaces are declared in the PORT-section. These interfaces are signals
which may change during the simulation depending on conditions of the system.
In the allocation of identifiers the user has to pay attention to the fact, that in VHDL no
difference is made between capital and small letters. It is Case-insensitive!
In addition to the special signal types, introduced in VHDL-AMS, the traditional type
SIGNAL was taken over from classical VHDL also. This means discrete electrical signals
which can be provided with a delay time too! Therefore bus systems can be described
very well. SIGNAL ports e.g. may be of the type BIT or STD_ULOGIC. These signals
can have the following modes: IN, OUT, INOUT or BUFFER. Signals with the mode IN
can only be read while ports with mode OUT may only be written and not be read.
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Attention: On defining the PORTS you must pay attention that only PORTS of
equal type can be connected together for proper compilation and simulation!

The behaviour description (ARCHITECTURE)

1.2.2

At least one behaviour description should follow after an interface was defined for the
object to fill the model with some functionality.
Description of an ARCHITECTURE:
ARCHITECTURE test1 OF example1 IS
QUANTITY Voltage_in ACROSS Current_in THROUGH input;
QUANTITY Voltage_out ACROSS Current_out THROUGH output;
QUANTITY sum: Real;
QUANTITY isum: Real: = 0.0;
SIGNAL vref_help: Real: = vref;

BEGIN
........
END ARCHITECTURE test1
The example would specify the behaviour test1 of the component example1. It is
necessary to give the behaviour model a unique name, since for every component
several behaviour descriptions can be modelled. This possibility is very meaningful with
regard to different implementations (bipolar, fet etc.) or model levels (system level,
differential equations ...).
After the keyword IS the declaration of signals as well as variables and constants starts.
The definitions that have already been done in the interface description don't have to be
repeated, but it is necessary to assign the corresponding signals to every terminal. This
is done as shown in the example above. It is only possible to assign QUANTITY signals
to the terminals, so its a Branch Quantity (unlike the interface Quantity).

After the declaration part the behaviour description starts, which is enclosed by BEGIN
and END ARCHITECTURE. A short description of the needed language elements is
given in the appendix on pages 23 and following.
Comment starts with two hyphens (--) and ends at next line break.
1.2.3

Configuration (CONFIGURATION)

In the CONFIGURATION is defined, which one of the described architecture variants is

assigned to the respective ENTITY and which assignments shall apply to used
submodules. Furthermore you can assign architectures to hierarchically lower Entities
and parameter values to subordinate components here too.
1.2.4

Package

Packages contain instructions like type or object declarations as well as descriptions of

procedures and frequently used functions.
1.2.5

Natures

In the NATURE is set up which kind of signal within a physical model or at an interface is
used. The type of the potential differences as well as the flux sizes are described
between two potentials. Furthermore a reference potential is fixed in the NATURE.
This means in the NATURE electrical the voltage between two points and the current
which flows into a node are declared. As a reference potential ground or
electrical_ground is defined.
Example for the declaration of a NATURE:
NATURE electrical IS
voltage
ACROSS
current
THROUGH
ground
REFERENCE
END NATURE electrical

1.2.6

Terminals

The TERMINAL serves as a junction point (PORT) between two components. The
corresponding NATURE is always given in the definition of the TERMINAL.
In VHDL-AMS a TERMINAL corresponds to a physical connection! For every
TERMINAL several signals can be assigned in the behaviour description: Signals for the
potential (e.g. voltage) and for the 'flux' (e.g. current). Terminals typically aren't
nonreactive. Depending on the model implementation the output load can react in
changing internal signals of the model too! The type of the signal is defined in the
description of the NATURE (see 1.2.5). Since a TERMINAL isn't a signal but an
interface, the corresponding signals must be assigned in the behaviour description.
Details to this are mentioned under 2-1-2

1.2.7

Quantities

A Branch QUANTITY (declaration in the ARCHITECTURE) assigns the corresponding

names to every signal of a terminal. This means it will submit names to the potential and
the flux. Both can be accessed by name within the ARCHITECTURE. In principle the
Quantities are signed, as it is usual in a conventional net analysis. So the current is
always positive if it flows into the node and negative, if it flows out of it.
An Interface QUANTITY (declaration in the ENTITY) describes a signed signal flow. It
represents another kind of interface.
Declaration of an Interface Quantity:
ENTITY example2 IS
PORT (QUANTITY input: IN REAL;
QUANTITY output: OUT REAL);
BEGIN END ENTITY example2;

Quantities can be provided with many different attributes. So qdot for example means
the first derivation of time for QUANTITY q. With these attributes, e.g. it is very easy to
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implement differential equation systems. For further information consult the appendix on
page 23 and following.
1.2.8

Simultaneous instructions

Many instructions which can only be processed sequentially in VHDL are able to be
executed simultaneously in VHDL-AMS too. The compatibility to VHDL remains
unchanged since the simultaneous variant has different syntax.

1.3

Description and Simulation of simple example

The first part of this Tutorial should make you familiar with the simulator and introduce to
the basic structure of VHDL-AMS models.
So start hAMSter and open the file mixed_mode_simple.vhd using the menu file->open
or by clicking

in the symbol bar. The file is located in the subdirectory Examples of

the contents directory of hAMSter

This file contains the model of a D-A convertor using method of pulse width modulation.

1.3.1

Model description

Block circuit diagram to mixed_mode_simple.vhd:

It bargains for a very simple method to convert digital signals into analogue. This is
reached by changing the input signal into quasi-analogue through the 1 bit D/A
convertor, which is often realized by a comparator, and filtering this stream over RCLowpass. The data stream consists of digital pulses with a varying width repeated in
regular distances. The da_convertor causes a voltage of +vref if logical 1 appears at
the input. Logical '0' means that Node n1 is held on -vref. The following RC low-pass
works as short time integrator here. The temporal mean average value of the pulse
sequence shall result at the output (voltage over the capacitance). The precision and the
remaining ripple of the analogue output voltage and the fastest change speed are
depending on the time constant of lowpass. The larger the time constant is, the more
exact the analogue output voltage gets and the slower the process of signal change
gets.
The flipflop is only a component of the Testbench, which is generating the test signal to
check the function of the convertor. This is a usual procedure for the description with
VHDL-AMS. The very simple example is therefore suited well to demonstrate the
construction of a model. It contains many innovations of the AMS extensions.
The simultaneous IF instruction is used in the da_convertor to change the serial digital
data stream into quasi-analogue pulses:
- List of included libraries
LIBRARY DISCIPLINES;
LIBRARY IEEE;
- announce the used functions out of the libraries
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
USE IEEE.MATH_REAL.ALL;
- interface description
ENTITY da_convertor IS
PORT (TERMINAL p, m: ELECTRICAL; signal input: IN BIT);
END ENTITY da_convertor;
- behaviour description
ARCHITECTURE behav OF da_convertor IS

QUANTITY v_in ACROSS i_out THROUGH p TO m;

BEGIN
IF (input = '0') USE
v_in ==-2.0 ;
ELSE
v_in == 2.0;
END USE;
END ARCHITECTURE behav;

The da_convertor has a digital input (input: in bit ) and one analogue output which is
represented by two connections (output voltage and ground). In the behaviour
description signals are defined for the output voltage and the output current (v_in and
i_out). The behaviour of a comparator is then modeled. Logical '0' at the input means
that the output voltage becomes -2.0 Volts, at logical 1 the output is switched to 2.0
Volts.
Important: Quantities of NATURE ELECTRICAL are signals of the type REAL. The
submitted numerical values must therefore contain at least one comma place.
WRONG: v_in == -2
RIGHT: v_in == -2.0
The description of the capacitance contains a differential equation: Ic = C*dU/dt:
- The capacitor definition begins
LIBRARY DISCIPLINES;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
ENTITY Capacitance IS
GENERIC (Val: REAL);
PORT (TERMINAL p, m: ELECTRICAL);
END ENTITY Capacitance;
ARCHITECTURE behav OF Capacitance IS
QUANTITY u_c ACROSS i_c THROUGH p TO m;
BEGIN
i_c == Val * u_c'dot;
END ARCHITECTURE behav;

In the interface section the size of the capacitance is defined as GENERIC (Val: REAL ).
The PORT-Description is done in the same way as described above in da_convertor.
In the behaviour description the capacitance equation is implemented. The construct
u_c'DOT returns the first derivation of the function u_c after the time (Derivation of time).
It consists of the quantity name (u_c) followed by the attribute ('DOT ). There are even
further attributes for Quantities defined, for example the attribute 'INTEG means the
integral of a Quantity over the time from the simulation beginning to current simulation
time.

1.3.2

Simulation of the example

Start the simulation of mixed_mode_simple.vhd over the menu simulation/start. After

that a window will open to select nodes of individual instances of the components to be
represented and to adjust the simulation parameters.
The choice box in the upper left corner selects the model which can be chosen for
simulation. Please choose the model bench because this model contains the complete
implementation.
Furthermore you can select the simulation method in this menu. TR stands for a
simulation in the time domain, DC means operating point analysis and by choosing
DC-> TR you can execute both one by one. Please choose TR here since the behaviour
of the model shall be examined in the time domain.
You can adjust the parameters for the simulation now. In the field End time you can
enter the duration of simulation. Under Min Step Size and Max Step Size you can
choose the minimal and maximal duration of one time step during the simulation. If the
rising edges should be represented in the simulation trace wrongly, you may correct this
by reducing minimal step size!
You can determine the maximum fault under Max Error. If the desired precision cannot
be achieved with the given time steps, a warning message appears in the status window
(below the Editor window).
The model hierarchy is shown on the right side of the simulation parameters window.
The node voltages are shown here and can be marked. The individual components and
signals assigned to them are announced. The top level model in our example is the

model bench in which all other components are instanced. The internal connections of
this model are listed under

Cons. nodes. These signals represent internal signals of

the model and can't be traced during simulation run. Below this, the interfaces to the
outside are listed under

N.-cons nodes. In this category all selectable signals of the

primary models are listed:

stand for an exit (nonreactive)
stand for a bidirectional connection (In and Out)
Below the list of Nodes, the individual components which the model consists of, are
shown. Every component also is subdivided like the model described above. The
components often contain even further components which are indicated by

. The

nodes contained in these models can also be called and marked to be displayed if
necessary. Please try and select the following nodes in the example:
rc: rc1/capacitance:: c1/N.-cons. nodes/u_c
da_convertor:: da1/N.-cons. nodes/output
flipflop:: ff1/N.-cons nodes/output

Start the simulation by clicking the Run button and interpret the signal traces. A new
window with the title hAMSter view tool' will open. If the signal traces aren't displayed
completely, choose

(coordinate system). Then choose 'all diagrams'. In the following

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window select 'x-axis', press the button 'Simulator defaults' and click OK. The time
domain is limited to the simulation duration now. You can optimize the representation
area of the y-axis for all diagrams by clicking on

(Best Representation). Interesting

periods of time can be zoomed in by moving the cursor onto the initial position, keeping
mouse button pushed down, selecting the zoom area with a rectangle and then
releasing the mouse button.
For particularly exact evaluations it is possible to store the output signals into files.
Different formats and the signals to be stored can be chosen.
After all is done, return to the model editor, start the simulation once more and choose
the voltage over the resistor (u_r) to be shown additionally.
To become more familiar with the simulation software, select some other signals for
representation. You may also change the output of the flipflop or vary the time constant
of the low pass filter by changing the capacitance and/or the resistance.

Simulation results of the example model

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