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Getting started with Icarus Verilog on Windows
August 25, 2013
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Megusta

Jose Vargas

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Icarus Verilog is a Verilog standard IEEE-1364 compiler that targets Linux but works almost as well on
Windows. It's lightweight, free software and includes a virtual machine that simulates the design. This
tutorial goes through the process of downloading, installing and using Icarus Verilog to write a simple
program, compile it, simulate it and view the simulation results on a timing diagram. It assumes no previous
knowledge on Verilog, but prior programming experience is recommended.

Installing Icarus Verilog

Download Icarus Verilog latest stable release for Windows from: bleyer.org/icarus
Installing Icarus Verilog is as easy as installing any other Windows program. Just hit next, but be sure to select
GTK Wave (full installation) and "Add Executables to Windows Path" option. You should be able to use it from
a Command Prompt by now. On Windows Vista/7/8 press Windows key and type cmd to open a command
prompt. Just type "iverilog" and you should get a message saying "iverilog: no source les" and some
instructions. Type "gtkwave" and the GTKWave GUI should open. This program is used to view the simulation
results graphically on a timing diagram.
If these commands are not recognized but the installation was successful chances are the executables were
not added to Windows Path. See How to set the Path on Windows to add "C:\iverilog\bin" to Path manually.

Writing a simple program

Now you are ready to write your rst Verilog program. For this tutorial we'll write a D type ip-op description,
that is, a Verilog module that works like a D ip-op. At the same time you'll learn some of the basic Verilog
concepts by example. You'll also write a tester module to reproduce the following D ip-op timing diagram:

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Verilog programs are separated in modules, which are functional blocks that have inputs, outputs and
internal logic. You can think of them like the blocks on a circuit's block diagram, but in this case they work.
There are two types of Verilog modules: behavioral modules and structural modules. Both may have the same
behaviour but are dierent in the way they are written as you'll see throughout the example.
For the ip-op program three modules are used: the ip-op module, tester module and testbench module.
The last two are modules you'll need on almost every design in order to test your circuit.

Flip-flop module
Represents a simple D type ip-op. Receives a clock signal and D signal as inputs and outputs Q and QN
signals. The outputs may change on the positive clock edge. The code for this module is:

//dffmodulesrepresentsaDtypeflipflop
moduledff(d,clk,q,qn);

inputd,clk;

outputq,qn;

regq,qn;

//Initializeflipflopoutputs
initialbeginq=0;qn=1;end

//Changeoutputonpositiveclockedge

always@(posedgeclk)

begin

q<=d;

qn<=!d;

end
endmodule
From this code, you can see the basic structure of every Verilog module. It starts with a declaration: module

dff(d,clk,q,qn); and ends with endmodule. The declaration states the module's name and both its inputs
and outputs. In the module we must declare which variables are inputs and which are outputs, using "input"
and "output".
Variables in Verilog are wires or regs. A wire, like a real wire, has no memory. Thus Verilog wire variables do
not retain their values by themselves. The reg keyword gives variables the ability to hold their values after
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they are assigned, until their value is changed, of course. We want this behaviour for the ip-op's outputs so
q and qn are dened as regs. If we use a wire the output is never seen by other blocks. It loses its value
immediatly after any assignment. There is no need to dene variables as wires, because they are all wires by
default.
The way the inner logic of the module is written deppends on wether it is behavioral or structural. The ipop module is an example of behavioral code. That is, you describe the behavior the module should have. To
do it, use initial and always blocks. The code within an initial block is executed once, when the ip-op is
created. In the example it's used to dene q=0 and qn=1 initially. By default in Verilog the variables are
undened (represented by an "x"), not zero, not one. If we did'nt use this initial block q and qn would be left
undened until they are assigned for the rst time.
The code within an always block is executed when a condition is met. In this case, when the clock has a
positive edge, q and qn are reassigned. This describes completely the ip-op's logic. As you can see, it is
simple. When the condition is not met, Verilog keeps the outputs' values.
As a rule of thumb, when writing a behavioral module, dene outputs as wires.
Verilog has control structures like while, if-else, case, for and repeat (similar to for) like most programming
languages. These assist you on writting your behavioral code. For example, replacing the ip-op module's
always block by:

always@(clk)

begin

end

if(clk==1)
begin

q<=d;

qn<=!d;
end

produces exactly the same behaviour. Some things changed. Now the always condition is always@(clk)
instead of always@(posedgeclk). This means that now the always block is executed every time clk
changes its value, on positive and negative edges. An always block can be triggered by any number of
variables. For example, @(clkord) would trigger it whenever clk or d change. This is used in combinational
logic where the output is recalculated whenever an input changes. Back to the example, if clk==1 then the
edge is positive. We check it using an if statement. Note that adding the "begin" and "end" keywords is
necessary when any block (always, initial, if, for...) has more than one instruction. If omitted for the "if"
statement above the second instruction: qn<=!d; would be executed always (it would be ouside of the if
statement). These two keywords act like the curly brackets on many programming languages.

Tester module
This module tests the ip-op by generating the clock and D signal of the timing diagram above and dumping
the Q and QN signals of the ip-op. It's outputs are the ip-op's inputs and viceversa.

//Testermodulesendsaperiodicclocksignaltotheflipflop
moduletester(q,qn,clk,d);

inputq,qn;
outputclk,d;

regclk,d;

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//Runthetestonce
initial

begin

clk=0;

//Dumpresultsofthesimulationtoff.cvd
$dumpfile("dff.vcd");

$dumpvars;
//Generateinputsignald

d=0;#9d=1;#1d=0;#1d=1;#2d=0;#1d=1;#12d=0;

#1d=1;#2d=0;#1d=1;#1d=0;#1d=1;#1d=0;#7d=1;
#8$finish;

end

//Generateperiodicclocksignal
always

begin

end

#4clk=!clk;

endmodule
This module is behavioral too as we have initial and always blocks. You should be able to undestand most of
the code. However, there are a few new concepts here. The $dumple and $dumpvars commands tell the
Verilog simulator (more on this ahead) to log the module's variables to the specied le, "d.vcd" in this case.
You may also be wondering what the #s do. These are Verilog delays. The delay the following instruction by a
given amount of time. For example, #4clk=!clk; within an always block changes "clk" every four time units
from 0 to 1, producing a square wave. The time unit is a second by default.
Without using delays there is no way of making the program work. This is the way to control time in the
design. You may add delays to any instruction. For example, you could model the ip-op's delay by adding
some to its always block. It's now easy to understand how the d=0;#9d=1;#1d=0;#1d=1;... lines
produce the D signal we want.
Finally, the $nish command tells the simulator to stop the simulation once the D signal was generated. If this
command was omitted the simulation would continue indenetly because this time the always block has no
condition (there is no @ like in the ip-op module).

Testbench module
This module just connects the tester module to the ip-op module:

//Testbenchconnectstheflipfloptothetestermodule
moduletestbench;

wireclk,d,q,qn;

dffff1(d,clk,q,qn);
testertst1(q,qn,clk,d);

endmodule
It is the most simple of the modules, but it's very dierent. This time it's structural code, that is, you dene the
structure of the circuit. It's like describing the circuit diagram. In this case the nal circuit is simply the ip-op
connected to the tester. To create a ip op use dffff1(d,clk,q,qn);. First goes the module name,
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followed by the part name, which could be almost any string, followed by the wires that connect to the
module in parenthesis. These must follow the order in the module's declaration. In a structural module we
use wires. Regs are not necessary because they are dened inside the dierent modules.

Compiling and simulating

Go ahead and copy/paste the modules into a text le, order doesn't matter. Call the le "d.v". The .v
extension is standard for Verilog les, but isn't required by the compiler. To compile open a Command
Prompt at your working directory (where you saved the le). A quick way to open a command prompt at any
directory is to hold shift and right-click the folder, then click "Open Command Window Here". Type:

iverilogodffdff.v
The "-o" tells Icarus Verilog to "save output to the following le". The output is then saved to "d". This le is
not executable. It has to be run using vvp, the Icarus Verilog simulator which is the one that actually produces
simulation results, zeros and ones for each of the model variables, as a function of time. To run the simulation
type:

vvpdff
This is what outputs the d.vcd le with all the simulation results. However if you open this le with your text
editor you'll see it's not easy to understand. To generate an easy-to-understand timing diagram from this le
we use GTKWave.
GTKWave does have a GUI. To open it press Windows key and type "gtkwave". Then click File -> Open New Tab
and chose the d.vcd le. Now you must add the variables in order to see their timing diagram. Click on
"testbench" at the left (SST panel) and then select all the variables using Ctrl or Shift and "Insert" them.
If everything is okay you should get a timing diagram exactly as the one at the beggining of the tutorial, just
like the following:

When testing your programs you'll have to go to the compiling-simulating-loading process every few minutes.
Remember you can use the up-down arrow keys while in the command prompt to access the last commands
and compile/simulate. On GTKWave use File->Reload Waveform to reload the .vcd le and refresh the timing
diagrams without having to reload each variable. By using these tips the whole proccess will take you a few
seconds.

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It's over. Now feel free to change the code around to see what happens. Mastering the use of delays, wires
and regs takes some time. See Verilog in One Day for a more in depth explanation of the language.

If you enjoyed this post, please consider following us, leaving a

comment or subscribing to the feed.

Megusta

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19 comments
July 15, 2014 at 7:47 pm

This was actually a very useful tutorial, but you sort of lost it at the
end.
You need to include the tester and the d in the top level test
bench:
`include "d_tester.v"
`include "d.v"

Chris

then you invoke iverilog on the top level test bench, not the d.v le. this will create the le
that you then invoke vvc, then you get your sim le.
Hope this helps everyone

May 12, 2014 at 1:38 am

I'm also having a problem with vvp. It runs, but never nishes and
doesn't generate a vcd le. Is there another program I can use to
generate it?

Anthony

April 8, 2014 at 5:30 am

Hi , help me please ...

I choose my work folder , ( hold shift and right-click the folder and
open cmd) , I wrote (iverilog -o d d.v) and I get this msg. "No
such le or directory , no top level modules and no -s option " .
What should I do ??
Rakesh

April 13, 2014 at 5:06 am

Hi rakesh,
I am also getting similar messages...please tell if you got any solutions

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priyadarshee

October 17, 2014 at 12:36 am

you can run cmd at windows key, and write

''d.v'''s address before it.
For example, if your d.v le's address is
''D:Desktop\cat\d.v'',you can just input
''iverilog -o d D:Desktop\cat\d.v''
Tang Kangqi

March 12, 2014 at 1:35 pm

Hi , help me please ...

I choose my work folder , ( hold shift and right-click the folder and
open cmd) , I wrote (iverilog -o d d.v) and I get this msg. "No
such le or directory , no top level modules and no -s option " .
What should I do ??
Ann

February 27, 2014 at 4:32 pm

hi I installed Verilog v9.7 (latest stable release ) I have windows 7

every time I try to compile a program it crashes with ivl.exe
stopped working any ideas why this is happening. please reply as
soon as you can thank you.
mohammedhashim

February 20, 2014 at 1:52 pm

Hi jose, I want to say you thank you. I read your notes and it was so
usefull for me. thank you. good luck.

david

February 6, 2014 at 3:35 pm

Hi,
I downloaded and installed the latest version, but iverilog always
crashes with no output with windows message "ivl.exe has stopped
working." I have it working ne on other machines with no
problem. I have tried all older versions too. What is up here?
Jesse

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February 7, 2014 at 9:29 am

Hi Jesse,
I never got that error and didn't nd any reports on
Google. You may get an answer by the developer by ling
a bug ticker here: http://sourceforge.net/p/iverilog/bugs.
If you do, specify the Windows version and programs you
are trying to compile. Thanks and good luck.

Jose Vargas
January 23, 2014 at 6:52 am

I installed, but when running iverilog from cmd, I get the message:
"iverilog" is not recognized as an internal or external command etc.

Stuart

February 4, 2014 at 9:25 am

Make sure you are in the correct directory. I installed in D

drive, so I have to change the directory from default C to
D, in command prompt. Also Jose mentioned how to
open cmd for a specic folder " hold shift and right-click
the folder".
Akshay

August 13, 2014 at 4:47 pm

During installation when it asks whether you should

update the path variable maybe you should say yes?

TheOriginalPC

December 28, 2013 at 11:54 am

Hi,
I was going to download verilog but there is ve option in
downloads and even more in the resources. Which one should I
download for windows xp???
Thanks.
David

December 28, 2013 at 1:03 pm

I installed (iverilog-20130827_setup.exe (development

snapshot) [11.2MB]) but did not work at all. It only took
me to a "explore folder". Not program to run.

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David

December 29, 2013 at 3:55 pm

Hi David, download the one labeled "latest

stable release".

Jose Vargas
December 8, 2013 at 1:52 pm

Hi I am new to verilog and iverilog. I followed the instructions here

but not able to get the d.vcd le generated. this is what I have got
d, d.v, testbench.v, tester, tester.v

sansuns

December 16, 2013 at 12:43 pm

Hi, the easiest way is to paste the three modules (d,

tester and testbench) to the same le (d.v) and compile
it. Then run the simulation with "vvp d" and you should
get the d.vcd le. It looks like your modules are in
separate les, so you should be able to compile them
together with "iverilog -o d d.v tester.v testbench.v"
and then run "vvp d" to get the d.vcd le. Hope it
helps.

Jose Vargas

October 16, 2014 at 1:07 am

I tried ur examples but do get "iverilog: cannot

open di.v le for reading... had set "path" of
source le also..
pls help
Ramesh

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