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Low Noise Amplifier Design Using 0.

35 m SiGe BiCMOS
Technology for WLAN/WiMax Applications
Mehmet Kaynak, Ibrahim Tekin, Ayhan Bozkurt and Yasar Gurbuz
Sabanci University, Faculty of Engineering and Natural Sciences, Orhanli, Tuzla, 34956, Istanbul,
Turkey Tel: ++90(216) 483 9533, e-mail:mehmetk@su.sabanciuniv.edu
Abstract This paper presents a design methodology of a
low noise and low power fully-integrated LNA, targeted to all
the three bands of IEEE 802.11a WLAN applications in the 56 GHz band and using 0.35m SiGe BiCMOS HBT
technology. We emphasized in this paper the importance
extraction of parasitic components through the use of
electromagnetic simulations, which is usually ignored in the
literature of similar works/research when reporting noise
figure. Finally, we have obtained a SiGe HBT on-chip matched
LNA, exhibiting NF of 2.75 dB, gain of >15dB, input return
loss of < -15dB, output return loss of < -10dB. The circuit
consumes only 10.6 mW under 3.3V supply voltage. The
circuit die area is 595 925 m2, including pads.
Keywords Low Noise Amplifier, LNA, SiGe, BiCMOS,
HBT, high-Q inductor, simultaneous matching

I.

INTRODUCTION

The trend demand for towards interactive multimedia


services has forced the development of new wireless
systems that has greater bandwidths. Next generation
WLAN operates in the 5-6 GHz frequency range. A frontend receiver capable of operating within this frequency
range is essential to meet the current and future of products.
One of the critical components, allowing the common use
of the technology can be attributed to the high performance
Low Noise Amplifiers (LNA) in the receiver chain of the
802.11a transceivers. In IEEE 802.11a, there are three
frequency bands; 5.15GHz - 5.25GHz, 5.25GHz - 5.35GHz
and 5.725GHz - 5.825GHz. A well-designed LNA should
not only supply sufficient gain to suppress the overall noise
figure but also have adequate bandwidth to cover all three
frequency bands. Recently, many LNAs have been
implemented using various semiconductor technologies
with excellent low noise figures (NFs) [1-5]. These low
noise figures are achieved at the expense of very high dc
power consumption, or other trade-offs such as high
input/output return loss, low linearity, or unsatisfactory
dynamic ranges. The compensation of the trade-offs
depends on applications as such ultra low noise may not be
priority because of the need for low power dissipation,
longer battery lifetime of portable communication systems.
For such portable systems, the total power consumption
could be as low as 15 mW, acceptable to be called as low
power consumption [6]. It is also possible to achieve low
noise together with low power consumption by using GaAs

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technologies or by using off-chip matching components.


However, these solutions also come at high technology
cost. There has been increasing effort toward the realization
of low-cost, on-chip high-Q inductors to keep the cost
lower.
In this paper, we present design and development of
low power and low noise integrated LNA for WLAN
applications in the 5-GHz band using 0.35m SiGe
BiCMOS HBT technology. A single-stage cascode
amplifier with emitter inductive degeneration was used. For
obtaining a low noise figure, different transistors, available
in the technology, analyzed and the optimum one (npn232)
was chosen. A formula of the NF of our circuit was derived
and used for optimizing the transistors and biasing points.
The electromagnetic (EM) simulations of the passive
components
are
performed
by
using
Agilent
MOMENTUM tool and all the parasitic components are
extracted, a crucial step for optimizing the performance
parameters of the LNA. Finally, we have obtained a SiGe
HBT on-chip matched LNA for 802.11a receivers,
exhibiting NF of 2.75 dB, input return loss of < -15dB,
output return loss of < -10dB and power consumption of
10.6 mW.
II. LNA DESIGN
In LNA circuits, gain can be achieved by a three
terminal single transistor means three different modes of
operation. The common-Emitter (CE) operating mode is
most often used as a driver for an LNA. The commonCollector (CC) stage has high input impedance and low
output impedance, a good candidate for buffer stages. The
common-Base (CB) is generally used as a cascode in
combination with the common-emitter driver stage, most
often used topology in LNA applications for achieving high
gain at RF frequencies. The loads of the topologies can be
made by using resistor for broadband applications or by
using tuned resonators for narrow-band applications. The
decision procedure of choosing input-matching network is
similar to load choice procedure. An LNA with resistive
input-matching has high noise figures due to the resistances
in the input of the circuit, generally not preferred for lownoise applications. This problem can be solved by using
inductors for simultaneous input and noise matching. In this
work, our topology of choice is emitter-degenerated
cascodeas detailed in the next subsections.

A. Topology of the Circuit and Detailed Description


Figure 1 illustrates the schematic of a cascode-connected,
common-emitter LNA with inductive emitter degeneration.

Figure 2: NFmin versus Ic curve for npn232 transistor

Figure 1: Cascode LNA circuit


The cascode amplifier has the advantage of having high
gain, low noise and stability, provided by large isolation.
The transistor Q1 provides the gain of the amplifier and
must be chosen out of the technology library carefully. The
typical application for achieving large area transistors is
connecting them in parallel. The transistor Q2 is a commonbase amplifier and provides the reverse isolation by
reducing the Miller capacitance between its input and
output. The inductor Ld is used for biasing, loading and
output matching purposes. Ld must be chosen as large
enough to block the flow of ac signal to Vdd and also to
increase the load of the circuit while keeping in mind that
Ld is also a part of output matching circuit. Co1 is used for
both loading and matching the output of the circuit. Also it
is used for dc blocking of output of the circuit. The Ccp
capacitor at the input is used for the purposes of both dcblocking and input-matching. Lg and degeneration
inductance Le are used to provide both the power and noise
matching. In the frequency range of 5 GHz, typical values
for Le is about 200-500 pH. These are the values that the
technology libraries dont have so these inductors should be
designed by the designer.

As seen in Fig. 2, 80-125 A of collector current range


provides the lowest noise figure and is suitable for the
npn232 transistor with unit device area for the 5.2 GHz
frequency band. Other collector currents increase the NFmin
of single transistor, directly increasing the overall NF of the
LNA.
C. Simultaneous Input and Noise Matching
In LNAs, gain versus noise figure trade-off is wellknown issue [7]. Gain and noise figure circles are easy way
of finding the optimum impedances which give the
maximum gain and maximum NF respectively. There are
several methodologies present that can be applied to obtain
a very low noise figure at the same time a good input
matching. In this work we will use the smith chart to deal
with this trade-off because the desired impedances can be
obtained simultaneously on the same smith chart. Hence a
designer can easily choose where the circuit should operate.

B. Low-Noise Transistor Design


One of the main efforts during the LNA design is given
into optimizing the bias currents and geometries of the
transistors for obtaining low noise figure. For a given
technology, the attainable noise figure is basically
dependent on the operating current density. In general,
design specific technological details of the process data are
not available. For finding the JCopt of the unit device, the
simulated or measured data could be used. The noise figure
versus collector current curves of npn232 transistor at 5.2
GHz are shown in Fig. 2 for the unit device area.

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Figure 3: Noise Circles of LNA

We performed simultaneous input and noise-matching


by designing the input-matching network so that the center
of the LNAs noise circles (NC) moves to the center of the
source admittance Smith chart, presented in Fig. 3.

the frequency range of our interest. As seen in Fig. 5, the


cascode feedback LNA achieves a power gain of above 15
dB in the 5-6 frequency range. The flatness of gain within
0.2 dB in this frequency range covers all the three band of
802.11a standard; 5. 15 GHz-5.25 GHz, 5.25 GHz-5.35
GHz and 5.725 GHz -5.825 GHz.

Figure 4: LNA Driver Transistor with two Inductors


Since the LNA is the first component in the receiver
chain, the input must be matched to 50- that is the output
impedance of the previous stage. The most convenient
method for input matching requires two inductors to
provide the power and noise match which is shown in Fig.
4. In Fig. 4 the inductors Lb and Le are designed to be onchip, as all the other passives in this circuit. In this
topology, input impedance can be written as

Zin =

j
g L
+ jwLe + m e + jwLb
wC
C

(1)

For input matching, the real part of the input impedance in


Eqn (1) must be equal to source resistance (50-). That is

Rs =

g m Le
C

(2)

Also, the imaginary part of the input impedance must be


equal to zero to obtain the value for Lb as

Lb =

RC
1
s
2
C w
gm

Figure 5: Gain Curve of the LNA (S21)


NFmin and NF curves of our LNA circuit are shown in
Fig. 6. A noise matching at the desired frequency range (56 GHz) and change of NF of 2.8 dB in 5-6 GHz band can
be observed in Fig. 6. In literature, noise simulations
generally dont include the inductors and series resistances
of wires. In this paper, all the parasitic effects of inductors
are taken into account and can be said that these parasitic
affecting the noise performance of the circuit up to %20,
For an example, addition of series resistance of Lb,
increases the noise figure from 2.1 dB to 2.8 dB. This
difference is attributed to the series resistance of the
inductor, contributing to the Q factor of the inductor. Lb
contribution to the Q factor is also seen in Fig. 6, changing
from 10 and 20. A lower quality factor for the inductors Lg
and Ls means an increase in the series resistance of the
input, causing an increase in the noise figure of the overall
circuit.

(3)

Before the matching, input of the circuit is capacitive


due to the C capacitance of the input transistor. Le in
Fig.1 tunes the real part of the input impedance and Lb in
Fig. 1 tunes the imaginary part of the input impedance. As a
result, final input impedance is near the center of the smith
chart, providing pure real 50- input impedance.
III. SIMULATION RESULTS
In this section, the simulation results of 5-6 GHz
wideband single-stage cascode LNA are presented. All the
simulations are performed using Agilent Design System
(ADS) and Cadence design tools with AMS 0.35m SiGe
HBT technology. This technology has a peak fT value of
50 GHz. Figure 5 presents the result of gain simulation of
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Figure 6: NFmin and NF analysis of the LNA


As seen in Fig. 6, NF of the circuit is nearly same to the
NFmin of the circuit which is highly desired. Also observed
in Fig. 6 is the input matching that gives the best value in
the same frequency range with NF.

The input matching of our circuit is also adequate for


WLAN applications. Fig. 7 illustrates a good input
impedance match of 50-. S11 of the circuit is below -15 dB
at the frequency of interest. This also shows us that
simultaneous input and noise matching is obtained.

Figure 7: Input Matching of the LNA (S11)

SiGe BiCMOS technology on a p-type substrate. There are


four metal layers in this technology and top metal layer has
a thickness of 3m, ideally suited for realizing inductors.
At a 5 GHz of operating frequency, all the paths will
have parasitic capacitances, resistances and also
inductances. Typical simulators can extract RC parasitic
components but inductance extraction is a very much
interesting topic for todays RF and Microwave
research/company communities. In this work all the
parasitic inductances are extracted by using Agilent
MOMENTUM tool. Lastly, all the paths in input part of
the LNA are realized by using the top metal layer because
of the reduction of series resistance. These series
resistances are directly adds noise and increase the overall
noise performance of the system.
Our circuit occupies an area of 595 925 m2. It is
operated with 3.3 V supply voltage for increasing the
output swing of the LNA. It only consumes 10.6 mW
power, very low as compared to similar bipolar LNAs [1-5].

Impedance matching at the input is always


required while at the output it is only necessary with the
LNA driving an external image-reject filter, placed between
the LNA and mixer. On the other hand, direct on-chip
connection between the LNA and mixer provides better
linearity and saves the power consumption. But more
stringent performance specifications of the image-reject
filter are required to avoid noise-figure degradation. In this
work, output is also matched to 50- source impedance.
The S22 result of the circuit is presented in Fig. 8. In the
frequency of interest, S22 is smaller than -10dB which is
enough for heterodyne transceiver architectures [8].
Figure 9 Layout of the LNA (595 925 m2)
V. CONCLUSION

Figure 8: Output Matching of the LNA (S22)


IV. LAYOUT ISSUES
The complete LNA layout, including bias circuitry, is
presented in Fig. 9. All components are on-chip, including
the dc blocking and by-pass capacitors. The LNA under
study was designed and simulated with a standard 0.35 m

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This paper presents the design, simulation and


implementation of a low noise amplifier for WLAN IEEE
802.11a applications in the 5-6 GHz operating frequency
range. We have demonstrated a careful design procedure
for the circuit, including inductors used in our design,
emphasizing
the
importance
of
electromagnetic
simulations/considerations, when the interest of frequency
is above 5 GHz. This is because as thickness/width aspect
ratios increase, horizontal currents also increases, hence,
should be considered for the accuracy of our results. The
importance of the passive components especially inductor
was specified and the solutions for the accurate simulation
results are provided. The NF of the circuit includes all the
parasitic components of the passives and very close to
NFmin that is 2.8 dB. In literature of similar research, it is
not a common practice to include parasitic extraction of
passive components when reporting Noise Figure. In this
paper, we proved that the parasitic components can degrade
the NF of circuit about 20%, having a great potential to

affect the dynamic-range of the overall transceiver. The


gain of the amplifier is sufficient enough for the specified
application, IEEE 802.11a, which is above 15 dB in the
frequency of interest. We have also presented gain flatness
within 0.2 dB for the same frequency. Input and the output
of the circuit have in-band return loss better than -15 dB
and -10 dB respectively. LNA is unconditionally stable
allover the band.
The circuit consumes only 10.6 mW under 3.3V supply
voltage. The circuit die area is 595 925 m2, including
pads. The result also unequivocally demonstrates that low
NF and low power consumption can be achieved
simultaneously with on-chip input and output matching
networks. From both a performance and cost perspective,
these results show that SiGe technology is very competitive
with its counterpart technologies, CMOS, BJT and GaAs
technologies.
VI. REFERENCES
[1] P. Ma, M. Racanelli, J. Zheng, M. Knight. A Novel BipolarMOSFET Low-Noise Amplifier (BiFET LNA), Circuit
Configuration,
Design
Methodology,
and
Chip
Implementation. IEEE Transactions on Microwave Theory
and Techniques, vol. 51, no 11, pp. 2175-2180, Nov. 2003.
[2] C. P. Moreira, E. Kerherve, P. Jarry, D. Belot. A LowConsumption LNA Using a 0.25-m 60 GHz fT SiGe:C
BiCMOS7RF Technology for Wireless Applications. IEEE
Mediterranean Microwave Symposium (MMS2004),
Marseille France, June 2004.
[3] D. J. Cassan and J. R. Long, A 1-V transformer-feedback
low-noise amplifier for 5-GHz wireless LAN in 0.18-m
CMOS, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 427
435, Mar. 2003.
[4] C.-Y. Cha and S.-G. Lee, A 5.2-GHz LNA in 0.35-m
CMOS utilizing inter-stage series resonance and optimizing
the substrate resistance, IEEE J. Solid-State Circuits, vol.
38, no. 4, pp. 669672, Apr. 2003.
[5] T. P. Liu and E.Westerwick, 5-GHz CMOS radio
transceiver front-end chipset, IEEE J. Solid-State Circuits,
vol. 35, no. 12, pp. Dec. 2000.
[6] H.W. Chiu, Shey-Shi Lu and Yo-Sheng Lin, A 2.17-dB NF
5-GHz-Band Monolithic CMOS LNA with 10-mW DC
Power Consumption, IEEE Transaction on Microwave
Theory and Techniques, vol. 53, no. 3, Mar. 2005
[7] Sorin P. Voinigescu, Michael C. Maliepaard, Jonathan L.
Showell, Greg E. Babcock, David Marchesan, Michael
Schroter, Peter Schvan, and David L. Harame, A Scalable
High-Frequency Noise Model for Bipolar Transistors with
Application to Optimal Transistor Sizing for Low-Noise
Amplifier Design IEEE Journal of Solid-State Circuits, vol.
32, no. 9, pp. 1430 1439, Sept. 1997

[8] Behzad Razavi, RF Microelectronics, Prentice Hall


PTR, 1998.

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VII. AUTHORS BIOGRAPHY


Mehmet Kaynak (BS04) He received his
B.S degree from Electronics and
Communication Engineering Department
of Istanbul Technical University (ITU) in
2004. Currently he is continuing his MS
degree at the Microelectronics Program of
Faculty of Engineering and Natural
Sciences of Sabanci University, Istanbul,
Turkey. His research interests are Analog
and Mixed mode IC design, RF and microwave design and RF
MEMS.
Ibrahim Tekin (MSc92PhD97) He
received his B.S and M.S degrees from
Electrical and Electronics Engineering
Department of Middle East Technical
University (METU) in 1990 and 1992,
respectively. From 1993 to 1997, he was
with
the
Electrical
Engineering
Department of the Ohio State University
(OSU) where he received his Ph.D degree
in 1997. During 1990-1993 he was a
research assistant at METU, and from
1993 to 1997 he worked as a Graduate Research Associate at the
ElectroScience Laboratory, OSU. 1997 to 2000, he worked as a
researcher in Wireless Technology Lab of Bell Laboratories,
Lucent Technologies. He is now with the Telecommunications
program at Sabanc University, Istanbul. His research interests are
RF and microwave design, UWB antennas and circuits, numerical
methods in electromagnetics. He is a member of the societies of
IEEE Antennas and Propagation and IEEE Communications.
Yasar Gurbuz
(MS93PhD97)
received the BS degree in electrical
engineering with high honors from
Erciyes University, in 1990. He received
the MS degree in 1993 and the PhD
degree in 1997 in electrical engineering
from Vanderbilt University in the USA.
He worked as a senior research associate
at Vanderbilt between 1997 and 1999.
His responsibilities included directing and performing research
projects, teaching courses and advising graduate students in the
areas of solid-state devices and sensors. From 1999 to 2000 he
worked at Aselsan Inc. In 2000, he joined Sabanci University,
Faculty of Engineering and Natural Sciences, as an assistant
professor and was promoted to associate professor in 2002. His
research areas include analog and mixed-signal integrated circuits,
solid-state devices and sensors, microelectromechanical systems
(MEMS) and wide-band gap semiconductor technologies. He has
more than 20 peerly-reviewed journal papers and more than forty
conference papers in his area of research. He is a member of IEEE
and SPIE.