CHAPTER 4

METHODOLOGY
This method is based on designing of multiplier working in four quadrants as both the input
use is out of phase. The main circuit consists of NMOS and PMOS connected in parallel
topology. Load used is the parallel combination of inductor and capacitor so that the
bandwidth of operation can be adjusted to the ISM band. Parallel combination of NMOS and
PMOS makes multiplication of the signal exact as both the device is having the threshold
voltage almost same. As both the device are getting no at the same instant so the need of
basing is avoided and harmonic distortion is reduce to high extant. Because the harmonic
distortion is the error related to turning on of device it also effect speed of operation of
circuit so this

are some of the important parameter which should be consider while

designing the multiplier. In analog circuit harmonic distortion is important parameter as

device take some time to turn on after applying input at gate.
This type of multiplier

exploits symmetry to remove the unwanted RF & LO

output signals from output by cancellation. Similarly symmetry will also reduce noise due to
cancellation at output. Same circuit is used as modulator, De-modulator by connecting the
external component like inductor and capacitor this component in the circuit is called lump
components.

4.1 PRINCIPAL OF OPERATION FOR MULTIPLIER DESIGN

To reduce the number of devices parallel structure is useful compared to cascaded
structure. The basic block diagram of four quadrant voltage mode Multiplier for ISM Band
is shown in fig.8.1 parallel structure is use to reduce the number of devices with minimum
size. In this paper load used as parallel combination Inductor and Capacitor for getting ISM
Band output instead of using NMOS at the load sides so that frequency adjustment for

desired band become possible. Output is the multiplication of two inputs with in ISM Band
can be obtain by adjusting the load value and by selecting proper W/L ratio (aspect ratio). In
this paper MOS devices are used in linear so that output should be in specific frequency
band but this increase the power losses for switching action of the PMOS and NMOS. The
PMOS output of one symmetric half is combine to the output NMOS of other half or load.
Resultant is the voltage multiplication of two input x and y as the circuit operates in four
quadrant. In this paper both the PMOS is feed by the negative gate signal supply so that
PMOS can conduct. Simulation is done by using TSMC 180nm foundry. Here threshold
voltage of both the NMOS and PMOS are all most same but out of phase i.e gate voltage of
NMOS is positive and gate voltage of PMOS is negative.
Fig 8.1 shows how transistors can be used to implement multipliers. In order to reduce the
number of devices parallel structure is useful compared to cascaded structure. The basic
block diagram of four quadrant voltage mode multiplier is shown in Fig.3. The purpose of
implementing this structure is to reduce the number of devices with minimum size. The
multiplier structure recommended in [6] uses NMOS as a load with constant Vbias voltage
to operate the loads in saturation region and all the input transistors in the linear region. The
only disadvantage of this structure is even though the number of devices is six; it requires
additional devices for generating the bias voltage, which makes device count more than six.
Using the same concept new structure is proposed to eliminate the Vbias sources. Hence the
number of devices required for proper operation is only eight. Here instead of using NMOS
at the load side Parallel combination of inductor and capacitor are used because for
obtaining the desired frequency band in ISM band range to design the multiplier for specific
purpose of ISM band application communication circuit design.

Figure 8.1. Proposed multiplier schamatice

Since transistors are operating in the triode region, let us consider the equation for small
signal model.
id = K' vdsvgs
vds1 = vo1 - vx
vds2 = vo2 - vx
vds3 = vo1 + vx
vds4 = vo2 + vx
id1 = K' vds1 (vy - vx )
id2 = K' vds2 (-vy - vx )
id3 = K' vds3 (-vy + vx )
id4 = K' vds4 (vy + vx )
id1 +id3 = K' [(-2vxvy )+(2vx 2)]
id2 +id4 = K' [(2vxvy )+(2vx 2 )]
(id2 +id4 ) -(id1 +id3 ) = 4K' vx vy
Above equation shows that the output of multiplier is depends on the trans-conductance
parameter, which in turn depends on the threshold voltage and W/L ratio of the device.

4.2 P OWER ANALYSIS

Let us consider the constant supply voltage in order to estimate the total supply current and
power.
I total = i d1+i d2 +i d3 +i d4
i d1,3 = K' [-2Vx Vy + 2Vx2 - 2Vth V01]
i d2,4 = K' [2V x V y + 2V x2 - 2V th V 02]
itotal = 2K' [2Vx -Vth (V01 +V02 )]
itotal = 4K' Vx2 - 2K'Vth (V01 +V02)
Power=Itotal.VDD.
Where, Vx is the input voltage and VDD is constant supply voltage. From above set of
quations we can observe that total current depends on V th, W/L ratio and input supply
voltage. Keeping W/L ratio minimum, Itotal will be directly proportional to input supply
voltage. Which implies that for low power applications input voltage and W/L should be
kept at minimum value.

Figure 8.2. Schematic under simulation

CHAPTER 5
APPLICATION USING ISM BAND MULTIPLIER
There is lot of application of the analog multiplier in the different process. Multiplier is the
important circuit used in mixed signal processing. Modulation is a process of increasing
signal strength so that signal transmits over long distance. Modulation is defined as The
process of varying one property of carrier signal in accordance with the instantaneous value
of modulating signal by keeping the other property constant. Now the amplitude
modulation The amplitude of the high frequency carrier signal vary in accordance with
amplitude of low frequency modulating signal by keeping frequency and phase
constant[13].
Demodulation is the technic of getting the original signal from received modulated signal
from channel at receiver these demodulated signal is actually contain information. In
demodulator carrier signal and information signal both are separated [13].
In [4] the design uses the cascaded topology which makes circuit larger as number of MOS
increase so the layout become complicated, at the same time body effect problem is having
the effect on result. This body effect will reflect on linearity of the circuit. Due to the body
effect the linearity of the circuit will increase.
In [9] separately RF and local oscillator section is design this make circuit complicated and
number of device increase. Local oscillator is used for generation ISM band frequency
signal for triggering of the RF section MOS.
The industrial, scientific and medical (ISM) radio bands are radio bands reserved
internationally for the use of radio frequency (RF) energy for industrial, scientific and
medical purposes other than communications in recent years the fastest-growing uses of
these bands have been for short-range, low power communications systems. Cordless
phones, Bluetooth devices, NFC devices, and wireless computer networks all use the ISM
bands [9].

5.1 AMPLITUDE MODULATION

Amplitude modulation is the process of increasing the strength of actual information signal
so that signal can travel the long distance with air as channel and minimum height of the
transmitting antenna. In this era of wireless communication lot many signal are present in
the air so the chance of noise interference is more so the circuit which is less affected by the
channel noise is needed. At the same time the modulation circuit should have the long range
so that the communication on a long range is possible. In paper the author proposed the
amplitude modulation circuit having this quality. Multiplier circuit is directly used for AM
directly in the above circuit two sinusoidal signal x and y is used as input signal. Where x is
the modulating signal with frequency 0.5 GHz and y is the carrier signal having the
frequency 10 GHz these shows the maximum carrier frequency range the circuit can also
work below this carrier frequency.
Noise is the mainly related to the amplitude design of the low noise multiplier and using the
same circuit for the amplitude modulation is advantage for designing the communication
circuit using the multiplier. As the circuit under simulation is supporting the high frequency
signal of 10 GHz carrier signal so the range of transmitting signal is also increase it is
possible to transmit the information to long distance by using small size antenna. In codeless
communication as the it is requirement of the design that size of antenna should be small
with large covering area and range to make the hand piece design small and at the same time
circuit should be low power consuming. All the parameters should be considered will
designing of the multiplier circuit to make the multiplier compatible for more number of
applications.
The advantage of designing of such high range device is that the device can be used for long
distance communication with low noise with the use of the free band using of which did not
require any license from the government so it will save the money and reduce the cost of
communication in some limited range of transmitter and receiver.
From simulated design it is clear that multiplier is used as AM circuit without any
adjustment or change in circuit same four quadrant multiplier is used. Parallel combination
of NMOS and PMOS in two half of the differential circuit combination is producing the
exact envelop of AM as shown in Fig.12. It is possible to change the frequency of the output
signal by changing the value capacitor and inductor connected at load. Simulation result

shown is for the in signal of 0.5v and frequency 0.5 GHz modulating signal x and carrier
signal of amplitude 0.5v and frequency 10 GHz showing the maximum range of the
modulator circuit.

Figure 9. Amplitude modulation circuit

5.2DEMODULATION
The processing of regenerating the original information signal from the received signal from
the transmitter at receiving end. The proposed demodulator is the designed by using the
same multiplier block which is used for generating the modulating signal. To demodulate
and generate the original signal from the received signal another multiplier block is
connected at the output of the modulator circuit and only capacitive load is used for the
demodulation. Demodulator circuit is shown in the Fig.10.
Demodulation is the process more affected by the channel noise so it is very important that
circuit itself is having the property of noise rejection. Design is using differential noise
rejection so the channel noise will get cancelled out and original information is generated
with less amount of distortion of the information. Simulation result will make this more

clear that noise is having the less effect on the information so the extra circuit required for
signal conditioning and noise filter is not required if the communication system is designed
using this proposed multiplier.
Advantage of DM design is the signals are processed by the same circuit at transmitter and
receiver so there is compatibility between the transmitter and receiver both the end so the
designing of the modem will become quite easy as compare to the other modem design
because their circuit is total different this will also makes the modem compact.

Figure 10. Simulated circuit of demodulator

CHAPTER 6

SIMULATION RESULTS
Simulation results for the ISM band multiplier is shown below this result shows the
operating band range, linearity, application result and comparison between the previous
work and design in thesis.
TABLE 1. MULTIPLIER SPECIFICATION

Above table shows the parameter used during the simulation and getting result. Two
ac signal can be multiplied and resultant signal is AC signal band with in ISM Band rang i.e
2.41GHz to 2.54GHz output with amplitude equal to 1.5v that is exact multiple of ac input x
and y with value 1v and 1.5v respectively .

6.1 AC ANALYSIS

Figure 11. Simulated result of ISM Band

Simulated multiplier design gives results of AC analysis specify that multiplier will operate
in ISM Band (2.4G to 2.5G)
In this result the input x and x- is out of phase but with same amplitude of 1v and
frequency 1GHz similarly y and y- are out of phase with amplitude 1.5v and frequency 10
GHz the resultant is having 1.5v in ISM Band as shown in fig.11 in this result PMOS is
having the negative gate signal so that PMOS will conduct at properly in synchronization
with the faster NMOS device.

6.2 DC ANALYSIS

10

Figure 12. Linearity graph

This result shows that the circuit is giving linear response. This means that even though the
multiplier is non-linear circuit it gives the linear result it means that the harmonica distortion
very less according to the result we can observe that harmonica distortion is of order 0.57%0.25%.

6.3 AMPLITUDE MODULATED OUTPUT

11

Figure 13. Simulated result for AM

The Fig.13. Show that amplitude modulated output same amplitude of both signal equal to
0.5v the gain of the circuit is one. So the resultant amplitude is 0.25v. Result is also
explaining the circuit is of t linear so that exact envelope for each modulating cycle. Output
frequency equal two the modulating frequency.

he signal of frequency 0.5GHz and

10GHZ.with
Measurement result summary
avgpwr1 = 8.8001e-005

Result in Fig 13. show that transient power amplitude modulated output by adding the
external component show precise difference between the two input x and y with 1v and 1.5v
with .2GHz and 10GHz respectively the result also shows the transient power due to the
source Vdd.
Result shows top most is the Y input with frequency 10 GHz, second shows the x input with
frequency .2GHz, third wave shows the modulated waveform with 10GHz. Last wave shows
power dissipation of the circuit due to Vdd.

6.4 TRANSIENT ANALYSIS

12

Figure 14. Simulated result for power, current, voltage

Fig .14 shows the current voltage and power consumed by the multiplier circuit .result is
explaining that transient analysis gives the plot between time and quantity under
observation. To analyses the proper operation of the circuit has to work in linear region of
the MOS characteristics. Power losses reduce because the circuit is working in linear region.
Most of the losses in the MOS device takes place while switching action takes place that is
when device move from saturation region to the cutoff region and vice versa.

6.5 DEMODULATED OUTPUT

13

Figure 15. Simulated result of demodulator

Fig.15 shows the simulation result for demodulation process the above wave show
modulated waveform and the lower waveform shows the demodulated result. Modulated
signals are having amplitude 0.25v and modulating frequency equal to 1GHz.Resultant
demodulate signal is having the amplitude almost 0.5v and frequency 1GHz.the amplitude is
0.5v because the modulated signal is the product of the signal having the amplitude 0.5v and
0.5v.
This demodulation is the result of obtained from differential output of the demodulator
circuit. But because of the inductive reactance and stage coupling loss the between the two
stages of the multiplier circuit.

6.6 NOISE BAND

14

Figure 16. Simulated result for noise

Above simulation result shows that the input noise is reduce to the 9 nV/Rt at the output
from the input noise 210 nV/Rt. The above wave is representing the output noise and the
lower wave representing the input noise. From the value noise reduce to large extant.
As noise rejection ratio is playing key role while designing any circuit used in
communication so this multiplier is good option for designing the Bluetooth. If the
Bluetooth device with low noise and high range is design the will revolutionized the
communication world and the networking world.
It has been founded in thesis that immunity to the noise makes the circuit under research
special because in this frequency band lot of the noise signals are present which interfere
with original information signal but because of the quality of the circuit to reject the
unwanted signal and except the desired signal special from the signal in atmosphere.

6.7 COMPARISON GRAPH

15

Figure 17. Comparison chart

Comparison chart is showing that the comparison between 3 design of multiplier with the
circuit in this thesis all of this are the four quadrant multiplier to make more ethical
comparison between different parameter of multiplier. The main parameter consider for
comparison are power, number of device, Vdd , W/L, frequency.

TABLE 2. C OMPARISON TABLE

16

CHAPTER 7

17

CONCLUSION
The specific ISM Band (2.4GHz-2.5GHz) has been used in thesis. It has been observed that
implemented circuit is operating in ISM Band exactly. The basic parameters of multiplier
such as linearity, modulation, power dissipation, frequency band have been verified. This
thesis shows the result of the ac analysis gives the frequency band which is ISM band. From
the comparison table it has been observed that design in this paper is having the low power.
It has been also concluded from the comparison table that design required small area (70%
less than other).
The power consumption of the circuit is also low so that battery life of the new device like
Bluetooth and codeless phone can be directly used. Also the range of the device is also
increase because circuit is design using the higher frequency range of 10GHz. this paper
shows the compatibility between transmitter and receiver as same circuit is used for
modulation and demodulation.
As the multiplier is sustaining to the channel noise is high circuit will give better result as
and the complexity of the circuit get reduce because extra circuit is not needed for the noise
rejection. Signal to noise rejection ratio is high this will reduce the layout size of the circuit.

REFERENCES

18

[1] C.Sawigun and A. Demosthenous, Compact low voltage CMOS our-quadrant analog
multiplier, 2007 IEEE pp 751-754
[2] Amir Ebrahimi, Hossein Miar Naimi, 1.2V Single Supply and LowPower CMOS
Four- Quadrant Analog Multiplier, 2010

XIth

International

Workshop

on

Symbolic and Numerical Methods, Modeling and Applications to Circuit Design

(SM2ACD),2010 pp 978-983
[3] R. Hidayat, K. Dejhan, P. Moungnoul1, Y. Miyanaga, A GHz Analog
for

UWB

Communications,

Proceedings

of

Asia-Pacific

Multiplier

Conference

on

Communications 2007,pp 55-58

[4] Amir Ebrahimi, Hossein Miar Naimi ,Compact, Low-Voltage, Low-Power and HighBandwidth CMOS Four-Quadrant Analog

multiplier 2010 XIth International

Workshop on Symbolic and Numerical Methods, Modeling and Applications to

Circuit Design ( SM2ACD)2010 pp 97-102
[5] Akshatha B C, A Vijay Kumar, Low Voltage, Low Power, High Linearity, High
Speed CMOS Mode Analog Multiplier,S econd International

Conference on

Emerging Trends in Engineering and Technology, ICETET-09 pp 149-154

[6] K.T. Lau, S.T. Lee, V.K.S. Ong our-quadrant analogue CMOS multiplier cell for
VLSI

signal and information processing, IEEE Proc Circuifs Devices Syst., Vol.

145, No. 2, April 1998 pp 132-134

[7] Chunhong Chen, Senior Member, IEEE, and Zheng Li , A Low-Power CMOS
AnalogMultiplier IEEE Transection on Circuits and Systems: Express Briefs, VOL.
53, NO. 2, February 2006 pp 100-104
[8] Mirko Gravati(1), Maurizio Valle(1), Giuseppe Ferri(2),Nicola Guerrini(2) and Linder
Reyes, A Novel Current-Mode Very Low Power Analog CMOS Four Quadrant
Multiplier Proceedings of ESSCIRC, Grenoble, France, 2005 pp 495-498
[9] N.V.Ghate, Dr. S.B.Pokle VLSI Design of ISM BAND Down Conversion Mixer
ICETET10
[10] Government of United States of America FCC Rule book vol.7, pp 284-345
[11] B. Razavi, Design of Analog CMOS Integrated Circuits New Yor :McGraw-Hill,
2000.

19

[12] R. Jacob Baker, Harry W. Li and David E. Boyce

and

MOS Circuit Design, Layout,

Simulation IEEE Press, pp 704-748

[13] Harihar Ghime, Communication Electronics,sai jeevan prakashan,pp 1-16.

ANNEXURE

20

A] NETLIST
I.

NETLIST FOR ISM BAND MULTIPLIER

CCapacitor_1 Vdd o1 1f
CCapacitor_2 Vdd o2 1f
LInductor_1 Vdd o1 L=36.37n
LInductor_2 Vdd o2 L=36.37n
MNMOS_1 o1 y x N_1 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 x- y o2 N_2 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_1 x- y- o1 N_3 PMOS W=1.8u L=180n AS=1.62p PS=5.4u AD=1.62p
PD=5.4u
MPMOS_2 x y- o2 N_4 PMOS W=1.8u L=180n AS=1.62p PS=5.4u AD=1.62p
PD=5.4u
VVoltageSource_5 Vdd Gnd DC 5
VVoltageSource_1 y- Gnd SIN(0 -1.5 10g 0 0 0)
VVoltageSource_2 x Gnd SIN(0 1.0 1g 0 0 0)
VVoltageSource_3 x- Gnd SIN(0 -1.0 1g 0 0 0)
VVoltageSource_4 y Gnd SIN(0 1.5 10g 0 0 0)

II.

NETLIST FOR DEMODULATION

CCapacitor_1 Vdd o1 1f

21

CCapacitor_2 Vdd o2 1f
CCapacitor_3 Vdd o3 100f
CCapacitor_4 Vdd o4 100f
LInductor_1 Vdd o1 L=35n
LInductor_2 Vdd o2 L=35n
MNMOS_1 o1 y x N_1 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 o3 o2 N_6 N_9 NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_3 o4 o2 N_5 N_10 NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_4 o2 y x- N_2 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_1 x- y- o1 N_3 PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_2 x y- o2 N_4 PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_5 o1 o3 N_7 PMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MPMOS_4 N_6 o1 o4 N_8 PMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
VVoltageSource_5 Vdd Gnd DC 1
VVoltageSource_1 Gnd y- SIN(0 1.5 10g 0 0 0)
VVoltageSource_2 x Gnd SIN(0 1 1g 0 0 0)
VVoltageSource_3 Gnd x- SIN(0 1 1g 0 0 0)
VVoltageSource_4 y Gnd SIN(0 1.5 10g 0 0 0)
VVoltageSource_6 Gnd N_5 SIN(0 1 1g 0 0 0)
VVoltageSource_7 N_6 Gnd SIN(0 1 1g 0 0 0)

B] PUBLICATION

22

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