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F.

Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Slide Set
Data Converters

High-Order, CT Converters and DAC

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Summary
SNR Enhancement
High Order Noise Shaping
Continuos-Time Modulators
Band-Pass Modulators
Oversampling DAC

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

SNR Enhancement
Many quantization levels augments the SNR . However, a many levels DAC
is problematic.
The SNR enhancement techniques aim at using many levels (n) in the
ADC and less levels (m) in the DAC.
Possible solution (Leslie Sing)
X
IN
DAC

SD

X
m

Y1
DAC

eQ,n

ADC
IN
DAC

Y2D
TRUNC

YD
Y1D PROC

(a)

SD

eQ,m

Y1
(b)

Y2
Y
Y1

PROC

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Two quantization errors


Y1 = X ST F + Q,m N T F

(1)

Y2 = Y1 Q,m + Q,n

(2)

the processing in the digital domain cancels the contribution of Q,m

Y2 N T F + Y1(1 N T F ) = X ST F + Q,n N T F.

(3)

That relies on a well predicted NTF as determined by the analog circuit to


be used in the digital processor. Any difference leads to a Q,m leakage.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Shaping of the truncation error


X +

1-z-1

S
-

z-1

1-z-1

n-bit
ADC

DAC

S
m-bit
DAC

Y1
Y+eT(1-z-1)k

Digital
SD

eT(1-z-1)k-1
Y

The shaped error due to truncation is predictable and can be compensated


for at the input of the second integrator.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

The output of the digital whose input is the main output Y results
Y1 = Y + T (1 + z 1)p

(4)

Since Y = P + Q,n, the signal feed back at the input of the sigma delta
(T Q,m) is
Y1 = P + Q,n + Q,m(1 + z 1)p

(5)

The output of the modulator becomes


Y2 = X ST F + Q,n N T F + Q,m ST F (1 + z 1)p.
Assume that Q,m ST F (1 + z 1)p is negligible.

(6)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

High Order Noise Shaping


Many integrators in the feedback loop give rise to high-order architectures.
Shaping of the quantization noise more effective but difficulty in designing
a stable modulator with many integrators around the loop.
Often, configurations that ensure stability bring about an extra denominator
in the STF and the NTF
N (z)
ST F (z) =
;
D(z)

(1 z 1)L
N T F (z) =
.
D(z)

(7)

If D = 1 we would have
2
Vn2 = Vn,Q

2L

"

fB
2L + 1 fs/2

#2L+1
2
= Vn,Q

2L
OSR(2L+1)
2L + 1

(8)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

The signal-to-noise ratio for an L-the order modulator with unity denominator in the STF and NTF is
SN R,L =

12 2 2L + 1
2L+1
k

OSR
8
2L

(9)

that, in dB, is
i
0
SN R,L = 1.78 + 6.02n +
h

2L
10log
+ 3.01(2L + 1) log2(OSR).
2L + 1

(10)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

SNR versus the OSR for different Modulator Order


180

N=8

140

SNR (dB)

N=4

N=7
N=6

160

N=3

N=5

120

N=2

100
N=1

80
60
40
20
0

10

OSR

100

1000

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Example 7.1
The denominator of STF and NTF has two poles that located at fp1= 4fB
and fp2 = 8fB in the frequency domain. Determine the effect of D(z) on
the NTF.

The positions of the poles in the z-plane are

zp1 = e/16 = 0.822,


on the real axis not so far from z=1

zp2 = e/8 = 0.675.

(11)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Effect of the denominator on the NTF


(notice that the region that matter is the one at low frequency).
0
20

NTF

40

NTF [dB]

60

without
D(z)

80
100
120
140
160
180
200

0.01

0.02

0.03

0.04

0.05

0.06

0.07

Normalized frequency [f/fs]

0.08

0.09

0.1

10

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

11

Single Stage Architectures


Many integrators in a architecture obtains high-order noise transfer functions but, at
the same time, poses special challenges for designing a stable architecture.
Well known stability criteria are not definite conditions for modulators. A stable linear
architecture becomes unstable when the quantizer is inserted into the loop.
Y

DAC

DAC

DAC

S
_

DAC

X+

(a)

eQ
X

S
_

Y
H(z)

(b)

ADC

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

12

with the simple scheme of a single feedback form output to input


ST F =

H(z)
;
1 + H(z)

NT F =

1
1 + H(z)

(12)

Assume that H(z) is given by


H(z) =
ST F =

P (z)
;
P (z) + Q(z)

P (z)
Q(z)
NT F =

(13)
Q(z)
.
P (z) + Q(z)

(14)

The goal is to have P(z) low-pass like; Q(z) high-pass (high-order) like and to have a
minimum degradation caused by P(z)+Q(z).

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Stability Analysis
Stability is the main issue. Having the quantizer makes the study problematic.
ADC

ADC

P
k
DAC

DAC
+Vref

+Vref

-Vref
a)

eQ
P

S
b)

-Vref

c)

eQ

P
k

S
d)

An amplifier before a 1-bit quantizer is irrelevant. Instead, the small signal model ...

13

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

14

The root locus technique is used to determine the stability limit. The gain can be assoe is reached, the unbounded nodes of the
ciated to the quantizer; when the limiting gain k
modulator can experience large and uncontrolled transients.
Indeed the quantizer sticks to one binary level for many clock periods causing low frequency oscillations (and tones in the signal band).
The key point is to find a meaningful definition of the quantizer gain. That is an opened
point, interesting from an academic point of view.
Warning!
What is important is to be aware of the .... ....

The study of the stability of a highorder modulator must be followed


by extensive time-domain simulations
with different amplitudes and frequencies of the sine wave input.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Weighted Feedback Summation


A possible scheme of single loop high-order modulator.
X +

S
-

z-k1

z-k2

z-k3

z-k4

z-kp

1-z-1

1-z-1

1-z-1

1-z-1

1-z-1

a1

a2

a3

a4

eQ

Integrators with or without delay.

P
S

ap

15

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

16

Estimation of the loop transfer function

Pp

ki
1
z (k1 +k2 )
z
z k1
a1 +
a2 + +
ap
Hp (z) =
1 z 1
(1 z 1 )2
(1 z 1 )p

Hp (z) =

P (z) = 1 z

+ 2 z

P (z)
(1 z 1 )p

+ + p z

(15)

(16)

p
X
1

i z i

(17)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

17

The STF and the NTF are

Pp
ST F = Pp

1 i z

1 i z

+ (1 z 1 )p

(1 z 1 )p
N T F = Pp
.
i + (1 z 1 )p

z
i
1

D(z) =

p
X
1

i z i + (1 z 1 )p = 1 + 1 z 1 + 2 z 2 + + p z r

(18)

(19)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

18

D(z) determine the poles of the STF and NTF. Moreover, the stability requires that the
poles be inside the unity circle

D(z) =

r
Y

(1 zi z 1 )

|zi | < 1.

(20)

Assuming that D(z) almost equals D(1) in the signal band, it results
N T Fid
N T Fid
N T F = Qr
=
.
(1

z
)
K
p
i
1

(21)

SN R|dB = SN Rideal |dB 20log10 Kp .

(22)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

19

Example 7.2
Study of a third order modulator with weighted feed- back summation and all delayed
integrators. Estimation of the quantizer resolution and ADC dynamic range.

1 + (a1 3)z 1 + (a2 2a1 + 3)z 2 + (a1 a2 + a3 1)z 3


resulting in a1 = 3, a2 = 3 and a3 = 1.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

20

Modulator with Local Feedback


Zeros of the NTF at z = 1 give rise to an optimum noise shaping for large OSRs.
Complex conjugate zeros on the z-circle obtains low noise around the zeros at the expense of a less effective shaping at z = 1. Therefore, we can increase the usable
frequency range.

(a)

(b)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

21

The use of local feedback obtains complex conjugate zeros as is achieved by the following
fifth-order modulator.

g1

X +
-

z-1
1-z-1

X1
+

a1

g2
Y1
-

z-1

1
1-z-1

1-z-1

a2

X2=Y1
S

a3

P
S

1-z-1

resonators obtained by closing loops of two integrators.

Y2

1-z-1

a4

eQ

z-1

ap

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

22

Transfer function of the first resonator loop.


z 1
= Y1 (z)
[X1 (z) g1 Y1 (z)]
(1 z 1 )2

(23)

Y1
z 1
=
.
X1
1 (2 g1 )z 1 + z 2

(24)

giving a pair of zeros on the unity circle that, using the z s relationship, are at


g1
1
g1 
1p = arccos 1
'
Ts
2
Ts

(25)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

23

HIGH-ORDER CT SD AND SD DAC

Chain of Integrators with Distributed Feedback


It is a generalization of the already studied second-order modulators (with two feedbacks
from the digital output to the inputs of the integrators).

eQ
X +

a1

z-1
1-z-1

a2

z-1
1-z-1

a3

z-1
1-z-1

a4

ap

p
X
Xz p
z i
P =
Y
api+1
.
1
p
1
i
(1 z )
(1 z )
1

z-1
1-z-1

S
P

(26)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Y = P + Q .

D(z) = (1 z 1 )p +

p
X

api+1 z i (1 z 1 )pi .

24

(27)

(28)

Observe that the input of the generic integrator is always given by the subtraction of two
terms
Vin,i = Vout,i1 ai Vout

(29)

where Vout is the analog conversion of Y . Since Vout,i1 is very close to ai Vout , the maximum amplitude of the (i-1)-th integrator output is approximately ai times the reference.
If necessary adjust the dynamic range of the integrators by using scaling.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

25

Cascaded Modulator
Is the alternative solution to high-order architectures (obtains high-order noise shaping
without incurring in stability troubles).

e1
X

SD-1
Order p1

Y1

e2
SD-2
Order p2

Y2
Signal
Processing

Y
Order
p1+p2

Each modulator provides, in addition to the digital output an analog signal: the quantization error.
The quantization error of the last modulator in not used.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

26

Study of a cascade of two modulators.


Y1 = X ST F1 + Q1 N T F1 = Xz r1 + Q1 (1 z 1 )p1

(30)

Y2 = Q1 ST F2 + Q2 N T F2 = Q1 z r2 + Q2 (1 z 1 )p2

(31)

It is possible to eliminate the quantization error of the first modulator in the digital domain.

Yout = Y1 ST F2 Y2 N T F1

(32)

Notice that the cancellation relies on the knowledge of the STF and NTF of the second
and first modulator respectively.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

27

Assume that the orders are p1 and p2 : N T F1 = (1 z 1 )p1 and


N T F2 = (1 z 1 )p2 ); moreover, ST F1 = z r1 , ST F2 = z r2 .
Yout = Y1 z r2 Y2 (1 z 1 )p1 = Xz (r1 +r2 ) Q2 (1 z 1 )p1 +p2

(33)

The STF is a delay; Q2 is shaped by an NTF of order (p1 + p2 ).


Possible op-amp non-idealities and component mismatches can make the actual NTF
different from the ideal one. The cancellation of Q1 is incomplete.

n,out = (N T Freal N T Fideal )Q1

(34)

If the N T F is [1 (1 I )z 1 ] (first order with zero shifted by I ) the residual noise is


n,out,1 = I z 1 Q1
The spectrum is white and only reduced by the oversamping ratio.

(35)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

28

If the number of bits of 1 and 2 are equal the spectra of the quantization noise
are also equal, therefore
I2
2L
1
; L = p1 + p2 .
<
OSR
(2L + 1) OSR2L+1

(36)

With a second order sigma delta in the first cell of the MASH
and N T F = [1 (1 I )z 1 ]2
(1 z 1 )2 [1 (1 I )z 1 ]2
= I2 z 2 + 2I z 1 (1 z 1 )

(37)

the residual is represented by two terms: I2 (the square of the first order counterpart) and
2I passed through a first order shaping function.
Use a second-order modulator (which is the maximum order that does not create stability
problems) in the first cell of the MASH.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

29

The inaccuracy in generating the quantization error


Q1 is the difference between the input of ADC 1 and its DAC conversion
Both DAC and subtractor can give rise to inaccuracies. Namely, gain errors of the DAC,
D , gain error of subtractor, S
The error in the quantization error, 0Q,1 is
0Q,1 = [(1 + D )Y1 P1 ] (1 S )

(38)

0Q,1 = Q,1 + Q,1 S + Y1 D (1 + S ).

(39)

Giving rise to a total error equal to


out ' X(D N T F1 ) + Q,1 (S N T F1 + D N T F12 )

(40)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Warning

All the above helps in the design; the key ...

The cascade of modulators relies on the exact knowledge of the


noise transfer function and the exact generation of the quantization
error to be cancelled. Errors disputing the assumptions can greatly reduce the achievable SNR!

30

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC


Cascaded 2+1+1 MASH
eQ1

X +

1-z

-1

1-z

eQ1

1-z-1

k2
+

eQ2

S
-

-1

eQ3
z-1
1-z-1

+
S

Y1
S
I
G
N
A
L

+
S

eQ2

-1

k1

z-1

+
S

Y2

+
S
Y3

P
R
O
C
E
S
S
I
N
G

31

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

32

The three outputs are


Y1 = Xz 1 + Q,1 (1 z 1 )2
Y2 = 1 z 1 + Q,2 (1 z 1 )

(41)

Y3 = 2 z 1 + Q,3 (1 z 1 )
the signal processing that cancels the rst and second quantization noises for obtaining
the output Y is
Y = Y1 z 2 Y2 z 1 (1 z 1 )2 + Y3 (1 z 1 )3 .

(42)

Y = Xz 3 + Q,3 (1 z 1 )4

(43)

that obtains
order of the shaping: 2+1+1

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

33

Dynamic range for MASH


The dynamic range of the op-amps and the amplitude of the quantization errors are critical
design issues especially with 1-bit quantizers.
First Order

Amplitude

500

1000
Normalized time

Second Order

1500

3
2000 0

500

1000
Normalized time

1500

Signal and Quantization noise

Possible problem due to excessive amplitudes of the quantization noise.

2000

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

An input (quantization noise) that exceeds the dynamic range is a problem.


High Resolution MASH

Therefore, remember, for ... ........................

For a high resolution MASH it is


recommended always using multibit modulators to limit the dynamic
range of the op-amps and reducing
the amplitude of quantization errors
to be cancelled out.
The linearity of the DACs must be
enhanced by trimming or dynamic
matching of elements.

34

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

35

Example 7.3
Study a 2-1-1 MASH 1-bit modulator. Plot of SNR as a function of the input amplitude.
Effect of the finite gain of the op-amps and possible clipping.

F. Maloberti
DATA CONVERTERS
Springer
2007

with

Chapter 7

HIGH-ORDER CT SD AND SD DAC

36

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

37

Continuous-time Modulators
A continuous-time (CT ) modulator moves the interface between continuous-time and
sampled-data inside the feedback loop.
Continuous
Time

Discrete
Time
X
Y

Continuous
Time

IN
H (z)
DAC s

YD

P
ADC

Yc

Discrete
Time

P
IN
Hc(s)
DAC

DAC

(a)

ADC

YD

DAC

(b)

Sampler of a CT modulator inside the loop non-ideal operation attenuated with NTF.
Slew-rate: continuous-time input and DAC steps distributed over the clock period T.
Supply voltage of a CT can be lower than its SD counterpart.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

38

S&H Limitations
The DAC is the key (and difficulty) block of the CT modulator.
More specifically, the S&H of the DAC is the fundamental block as jitter and the finite rise
and fall-time of the generated waveforms limit the S&H linearity.
VDAC,ji

VDAC,rf

0 1 0 0 1 1 0 1 0 1 1 0

0 1 0 0 1 1 0 1 0 1 1 0
erf

eji

(a)

(b)

The clock jitter gives errors made by pulse with random duration tj,i.
The finite rise and fall time gives errors made by pseudo-exponential pulses.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

39

Assume a fraction tr of 0 1 or 1 0 transitions.


2 with Gaussian distribution
Assume the variance of the clock jitter ji
2
Pn,DAC,j = 4Vref
tr

2
ji

8Ts2

(44)

The noise power in the signal band must be smaller than the power of the shaped quantization noise.
2
ji
2L
(45)
<
OSR2L
2
Ts
6tr (2L + 1)
a very demanding request at high resolution.
With fs = 40 M Hz, = 0.25 L = 4 and OSR = 32, ji < 0.63 ps!!

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

The difference between rise and fall time matters because the error occurs randomly.
Key Limits

A possible remedy to the .... ........................

The clock jitter and the asymmetrical rise and fall response of the
DAC are the most relevant concerns in CT DAC design. Using
RTZ-DAC gives time for the ADC
operation and resolves the latter
limit but the jitter remains the critical issue.

40

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

41

CT implementations
Different methods implement a CT integrator:
an active RC circuit using an op-amp or an OTA; employing a MOS transistor with controlled equivalent resistance, use transconductors for realizing gm C schemes.
Various combinations of the above approaches lead to the following design solutions:
Use of all RC integrators to implement low-voltage low-pass modulators.
Use of Mosfet-C integrators with on-line tuning capabilities.
Use of gm C integrators with current steering DACs for low-power, medium order
modulators used in the audio band.
Mixed use of RC and gm C integrators: the use of a first RC stage and the remaining
gm C makes the architecture suitable for high-resolution audio band applications.
Use of current-mirror based integrators for very low-power.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

MOSFET-C Integrator
There are many technique to make linear the equivalent resistance of the MOSFET.
VC1 VC2
M1

CI

Vin+
M2
M'2

VinM'1

Vout-

+
_

Vout+
CI

42

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

43

Use of V-to-I converter


The transconductance gain is well controlled with resistors. The tunability can be ensured
by replacing resistors with MOS.
I+

I-

I+
Vin+

VinM1

Rs

IB

Vbias

IVin+

Vin-

M2

M1

IB

IB

M2
IB

Vcm

(a)

(b)

Injecting the current on a capacitance obtains a continuous-time integrator.

Gm =

gm
;
2 + Rs gm

r
gm =

2Cox

W
IB .
L

(46)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

44

Use of transistors in the linear region


The drain voltage is controlled and kept constant by the feedback loop. The transconductance is tuned by changing Vd .

Vd

Iout+

Iout-

Vd
Vin,d

Gm

Vout,d
C

Vcm- Vin

Vcm+ Vin
(a)

(b)

Iout = Iout,q Cox

W
Vd Vin
L

(47)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

45

Fully differential current-mode integrator for very-low voltage and low power.

IB

IB

IB

IB

IB

IB

Iin+

IinM1

M4

M2
C

Iout- Iout+

HI (s) =

1
.
1 + sC/gm

(Id,in + Id,out )HI (s) = Id,out


Id,out =

Id,in
sC/gm

M3
C

(48)
(49)
(50)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

46

Design of CT from Sampled-Data Equivalent


The design of CT architectures is critical: the interface between continuous-time and
sampled-data processing is inside the loop filter.
eQ(z)
X(s)

X(z)
+
S
-

Hs(z)

eQ(z)
Y(z)

X(s) +

S
-

Hc(s)

HDAC(s)
(a)

Critical is also the type of waveform generated by the DAC:


non-return-to-zero, NRTZ ), or return-to-zero, RTZ.

(b)

Y(z)
S

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

47

The design of CT modulator by using an already designed sampled-data prototype.


Identification of a corresponding CT architecture with an equal or very close noise transfer
function.
The loop transfer function of the discrete-time model is Hs (z).
The CT counterpart includes the response of the DAC.

Gc = Hc (s) HDAC (s).

(51)

Hs (z) = Z{Hc (s) HDAC (s)}

(52)

1 es
HDAC (s) =
s
n H (s) o


c
/Ts
Hs (z) = Z Gc (s) = (1 z
)Z
s

(53)
(54)

and, in the time-domain


Z 1 [Hs (z)] = L1 {Hc (s) HDAC (s)}

(55)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

48

How to estimate the STF and the NTF


eQ(z)
Hd(z)

X(z)
+
S
-

Y(z)

Hd(z)
(a)

eQ(z)
+

Hc(s)

Y(z)
S

Hc(s)

HDAC(s)

(b)

1
1 + Hd (z)

(56)

n
o
1
= Z L [Hc (s)HDAC (s)]

(57)

1
(z)
1 + HCT

(58)

N T Fd =

(z)
HCT

N T Fc =

ST Fc (s) =

Hc (s)
1 + Hd (esT )

(59)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

49

Band-Pass Modulator
If the loop filter has a resonance at a center frequency f0 , then the quantization noise is
strongly attenuated in that bandwith band-pass converter .
X

ADC
H(z)
Y

YD
NTF

STF
DAC

f0

(a)

(b)

H(z)
1
; NT F =
(60)
1 + H(z)
1 + H(z)
The digital filter after the modulator must rejects the noise outside the band interval.
ST F =

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

50

To obtain a band-pass move the poles of H(z) from z = 1 to complex conjugate


positions on the z-unity circle.
z 1 cos0 z 2
z
1 z 1 cos0
At the resonation frequency the NTF is zero while the STF is 1.
1

(61)

Far from the resonation frequency the module of H(z) becomes small (and possibly lower
than 1) the out-of-band input components can be attenuated and the noise amplified.

For the design of band-pass modulators start from a low-pass prototype and use a suitable
transformation.
If 0 = /2, then zbp = j or fbp =fs /4, which is half of the Nyquist frequency. The
corresponding transformation is z 1 z 2 .

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

51

Use of the transformation z 1 z 2 : a double delay and a subtracter replace the


single delay and the adder.
X -

0.5

S
-

P+

z -1

R +

+
2

YD

z -1

ADC

+
Y

DAC

(a)
-X -

0.5

S
-

P+

z -2

R +

+
2

S
+

-YD

z -2

ADC

-Y

DAC

(b)

(P R)z

=R

P z 2
R=
1 + z 2

(62)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Implementation details: double chopping and two-path scheme


1,1, -1, -1, ....
P+

R
S
-

z-2

R'
S

z-2

(a)

(b)
1,0, -1, 0, ....
x

Ro'
S
+

z-2

x
R

S
0,1, -1, 0, ....
+
x
S
z-2
+
(c)

+
Re'

52

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

R0 (n + 1) =
R0 (n + 2) =
R0 (n + 3) =
R0 (n + 4) =

P (n 1) + R0 (n 1)
P (n) + R0 (n)
P (n + 1) + R0 (n + 1)
P (n + 2) + R0 (n + 2).

R(n 1) = R0 (n 1); R(n) = R0 (n);


R(n + 1) = R0 (n + 1); R(n + 2) = R0 (n + 2);
R(n + 3) = R0 (n + 3); R(n + 4) = R0 (n + 4);

R(n + 1) =
R(n + 2) =
R(n + 3) =
R(n + 4) =

P (n 1) R(n 1)
P (n) R(n)
P (n + 1) R(n + 1)
P (n + 2) R(n + 2)

53

(63)

(64)

(65)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

54

HIGH-ORDER CT SD AND SD DAC

Interleaved N-Path Architecture


The method is a viable solution for band-pass converters by using two or more paths.
The analog input of each path is every third input sample decimation by 3 before the
.
F1

fs/3

fs/3

fs

Ts

SD
F1

F2
Vin

SD

M
U
X

F2

F3
F3

SD

zk =

i e(2k+i )/N

k = 0, , (N 1)

(66)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

55

NTF generated by applying a z 1 z 3 transformation to an NTF with two zeros at


z = 1.

1
3
z1 = 1; z2,3 = j
.
(67)
2
2
1

20

Magnitude (dB)

Imaginary Part

40
60
80

2
1
1

20

Real Part

100

0.2

0.4

0.6

Normalized Frequency (Nyquist)

(a)

0.8

(b)

amplification caused by the other zeros


ki = |zin zi |;

zin = e2fin T

(68)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Example 7.4
Three path sigma-delta modulator with second order 1-bit modulators.

PSD of a 3Path SigmaDelta Modulator

PSD [dB]

50

100

150

Frequency [Hz]

10

15
5

x 10

56

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC


PSD of a 3Path SigmaDelta Modulator

PSD of a 3Path SigmaDelta Modulator

Offset 10 mV

50

Gain error 0.01

PSD [dB]

PSD [dB]

50

100

100

150
0.9

0.95

1
Frequency [Hz]

1.05

x 10

(a)

1.1

150
0.9

0.95

1
Frequency [Hz]

1.05

(b)

PSD of a 3Path SigmaDelta Modulator

Clock misalignment 0.005 rad

50

1.1
6

x 10

PSD of a 3Path SigmaDelta Modulator

All the errors

PSD [dB]

PSD [dB]

50

100

150
0.9

100

0.95

1
Frequency [Hz]

(c)

1.05

1.1
6

x 10

150
0.9

0.95

1
Frequency [Hz]

(d)

1.05

1.1
6

x 10

57

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

58

Synthesis of the NTF


Inband tones are a limiting factor in the performance of an N-path .
Tones must be pushed to frequencies that are well outside the band of interest.
Possible solution: syntesis of the NTF by adding extra terms to an NTF close to the
desired function.
Suppose to apply z 1 z 2 to a second-order NTF
N T F 0 = (1 z 2 )2 = 1 2z 2 + z 4

(69)

which has the same order as the fourth order noise transfer function
N T F4 = (1 z 1 )4 = 1 4z 1 + 6z 2 4z 3 + z 4
missing terms to be synthesized are 4z 1 , 8z 2 , and 4z 3 .
The method is convenient for band-pass responses.

(70)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

59

Two-path sigma-delta modulator with 1/(1+z 2 ) loop gain that, with the addition of extra
noise terms to obtain the (1 + z 1 + z 2 ) band-pass NTF.

fck/2

Vin

F1

z-2

fck/2

F2

fck

F1 fck/2
1
1+z-2
F1 fck/2
z-1

F1
M
U
X

fck

fck/2
z-2

1
1+z-2

e1

Vin

1
1+z-2
(a)

fck/2

F2

M
U
X

z-2

z-1

1
1+z-2

e2

(b)

Ye = Xe z 2 + 1 (1 + z 2 ) + 2 z 2
Yo = Xo z 2 + 2 (1 + z 2 ) + 1 .
Y = Ye + Yo z 1 = Xz 1 +

1
(1 + 2 )(1 + z 1 + z 2 )
2

(71)

(72)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

As expected the tones caused by mismatch fall out of the band of interest.
The signal band is tone free.
0

Spectrum [dB]

-20
-40

-60
-80

-100
-120
0

10

20

30

40

Frequency [MHz]

50

60

60

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

61

Oversampling DAC
Oversampled DACs work very similarly to the oversampled ADC.
The difference between analog and digital oversampling converters is where the processing is performed and where is the interface between continuous-time and sampled-data.
M x fs
n
bit

n
bit

M x fs

2k
Binary
to
Thermometric

Digital
Modulator

Interpolator

fs

k
bit

M x fs

DAC

Reconstruction
Filter

M x fs

The interpolator is critical: small margin fB to fs fB normally used for storing or transmitting digital data.
Use high order filter to reject very close images without altering the signal band.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

62

1-bit DAC
1-bit digital modulators employ a 1-bit DAC followed by either a switched-capacitor and/or
continuous-time analog filters.
The noise specifications of the DAC and filter can be challenging for very high resolution because for a desired SNR the amount of noise power in the signal band must be
Pmax,in /SN R. For example,
2kT
;
(73)
OSR C
OSR = fs /(2fB ); a switched capacitor is equivalent to a resistance Req = 1/(Cfs )
2
Vn,R
= 4kT RfB ,

2
Vn,R
= 4kT RfB ,

2
Vn,SC
=

2
Vn,SC
= 4kT Req fB .

(74)

There is an upper limit to the value of R or Req .


Suppose = 1/(16 fB ); fB = 10 kHz; OSR = 128; SNR 100 dB. Rmax = 7.5 k,
C = 266 pF .

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Leading to th following ... ......................

Obvious Note
The noise contributed by the reconstruction filter must be lower than
the quantization noise falling in the
signal band. For high-resolution
this constrain requires to use large
area-consuming capacitances!

63

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

64

Possible reconstruction filters


C1
IB /2

C2

IB /2

R1
Vout+

_
R1

R2

D
C1

R3
_

C1

D
R2

R1

R3

C2

R1
_

Vout-

IB
(a)

(b)

The key limit can be (again) the clock jitter.


Pn,ji =

2
Vref
tr

2
ji

2 OSR

Ts2

(75)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

65

HIGH-ORDER CT SD AND SD DAC

Example 7.5
Reference voltage 1 V ; signal band 22 kHz; 128 OSR. SNR=110 dB with 99.9% yield.
tr = 0.25.
-

tr

2
ji

Ts2

= 1011

4 OSR
fck = fs = 2 128 22 kHz = 5.63 M Hz leading to Ts = 0.18 s.
The jitter power must be 110 dB below the power of the full scale signal.

(76)

ji < 25.7 ps. For a 0.999 yield it is necessary that 25.7 ps is 3.3 ji < 7.8 ps.

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

Return-to-zero DAC
Sensitivity to the difference in rise and fall times.
Use of return to zero
0

Ideal
DAC
Real
DAC
Ideal RTZ
DAC
Real RTZ
DAC

tr

tf

66

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

67

Double Return-to-zero DAC


f r
) = Vref pT (1 + p )
(77)
2
The error is linear but he spectrum is not optimum because tones fall closer to the signal
band.
ADAC (p) = Vref (pT +

2fck
RTZ1

RTZ2 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0
Out
S

1-bit
DAC

(a)

RTZ1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0

1-bit
DAC

2fck
RTZ1

IN

(b)

F. Maloberti
DATA CONVERTERS
Springer
2007

Chapter 7

HIGH-ORDER CT SD AND SD DAC

68

Wrap-up
Techniques useful for improving the modulator performances have been studied.
A shaping with order higher than 2 has been analyzed, also considering the problems
caused by stability (that, remember, is a more complex issue than a linear filter).
The cascade scheme (called MASH) resolves the problem of stability but relies on the
accuracy of the analog response of integrators that give rise to accurate NTF and STF.
Continuous-time modulators offer benefits with respect to the sampled-data counterpart, especially when low power and high sampling rate are required. For high resolutions
the sampled-data version is preferred.
Band-pass modulators are used in many applications for reducing the power. Various
scheme and solutions have been discussed.
The DAC is finally studied.

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