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Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
EE3CL4:
Introduction to Linear Control Systems
Section 6: Design of Lead and Lag Controllers using
Root Locus
Tim Davidson
McMaster University
Insights
Winter 2013
EE 3CL4, 6
2 / 50
Outline
Tim Davidson
Compensators
Lead
compensation
1 Compensators
Cascade
compensation
and
steady-state
errors
Lag
Compensation
2 Lead compensation
Insights
4 Lag Compensation
EE 3CL4, 6
4 / 50
Compensators
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
that we want
Ask whether we can change the system,
process
EE 3CL4, 6
5 / 50
Tim Davidson
Cascade compensation
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
Q
Kc M
(s + zi )
Gc (s) = Qn i=1
j=1 (s + pj )
Therefore, the cascade compensator adds open loop
EE 3CL4, 6
6 / 50
Tim Davidson
Compensator design
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
8 / 50
Lead compensation
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Kc (s + z)
(s + p)
with |z| < |p|. That is, zero closer to origin than pole
Gc (s) =
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
c (1 + lead p s)
K
Kc (s + z)
=
(s + p)
(1 + p s)
EE 3CL4, 6
9 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lead compensation
Kc (s+z)
(s+p)
Kc (1+lead p s)
(1+p s)
Frequency response:
Gc (j) =
c (1 + jlead p )
K
(1 + jp )
c )
Bode diagram (in the figure, K1 = K
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
c lead p
Between = z and = p, |Gc (j)| K
What kind of operator has a frequency response with
magnitude proportional to ? Differentiator
Note that the phase is positive. Hence phase lead
EE 3CL4, 6
10 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
V2 (s)
V1 (s)
EE 3CL4, 6
11 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
12 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
13 / 50
Tim Davidson
Compensators
Lead
compensation
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
and Gc =
Kc (s+z)
(s+p) ,
we have P(s) =
Q
(s+zi )
KG M
Qn i=1
j=1 (s+pj )
QM
(s+z) Qi=1 (s+zi )
n
(s+p)
j=1 (s+pj )
and
(angle from zi to s0 )
i=1
n
X
(angle from pj to s0 )
j=1
Insights
= 180 + k 360
Mag. cond. If s0 satisfies phase condition, the gain that puts
a closed-loop pole at s0 is K = 1/|P(s0 )|:
Qn
(dist from p to s0 )
j=1 (dist from pj to s0 )
K = QM
EE 3CL4, 6
14 / 50
Tim Davidson
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Insights
EE 3CL4, 6
15 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
1
Consider a case with G(s) = s(s+2)
and H(s) = 1.
Design a lead compensator to achieve:
Insights
What to do?
Can we achieve this with proportional control?
If not we will attempt lead control
EE 3CL4, 6
16 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
1
s(s+2)
1
EE 3CL4, 6
17 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
18 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
19 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
20 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
97.1
8
Hence compensated open loop: Gc (s)G(s) =
97.1(s+4)
s(s+2)(s+10.86)
EE 3CL4, 6
21 / 50
What to do now?
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
thumb
Can we do better?
EE 3CL4, 6
22 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
Centroid denoted ca
EE 3CL4, 6
23 / 50
Tim Davidson
Prop.-contr.
Lead contr.
125(s+4.47)
(s+12.5)
OL TF, GC (s)G(s)
5
s(s+2)
125(s+4.47)
1
(s+12.5) s(s+2)
Y (s)
R(s)
5
s(s+2)+5
125(s+4.47)
s(s+2)(s+12.5)+125(s+4.47)
CL poles
1 j2
CL zeros
4.47, ,
Compensators
Lead
compensation
Controller, GC (s)
Cascade
compensation
and
steady-state
errors
Lag
Compensation
CL TF,
CL TF, again
5
s2 +2s+5
131(1+0.013s)
s2 +8.94s+100
1.71
s+5.59
Insights
EE 3CL4, 6
24 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
25 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
26 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
27 / 50
Tim Davidson
Outcomes
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
29 / 50
Tim Davidson
Cascade compensation
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
K (s + z)
(s + p)
with the pole, p, and the zero, z, both in the left half plane
when |z| < |p|: phase lead network
when |z| > |p|: phase lag network
EE 3CL4, 6
30 / 50
Steady-state errors
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
Let G(s) =
Q
KG i (s+zi )
Q
j (s+pj )
s0
R(s)
1 + GC (s)G(s)
KC (s+z)
(s+p)
EE 3CL4, 6
31 / 50
Steady-state error
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
system, G(s) =
KGQ i (s+zi )
s j (s+pj )
EE 3CL4, 6
33 / 50
Lag compensation
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Kc (s + z)
(s + p)
with |z| > |p|. That is, pole closer to origin than zero
Gc (s) =
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
c (1 + z s)
K
Kc (s + z)
=
(s + p)
(1 + lag z s)
EE 3CL4, 6
34 / 50
Frequency response
Tim Davidson
Compensators
Gc (j) =
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
C (1 + jz )
K
(1 + jlag z )
Magnitude
C
Low frequency gain: K
Corner freq. in denominator at p = p = 1/(lag z )
Corner freq. in numerator at z = z = 1/z
p < z
C /lag = KC
High frequency gain: K
Phase
() = atan(z ) atan(lag z )
At low frequency: () = 0
At high frequency: () = 0
In between: negative, with max. lag at =
zp
EE 3CL4, 6
35 / 50
Tim Davidson
c = 1
Bode Diagram, with K
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
36 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
37 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
38 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
s+z
s+p .
Lag compensator
example
Insights
Design Principles
We dont try to reshape the uncompensated root locus.
We just try to increase the value of the desired error constant
by a factor lag = z/p without moving the poles (well not
much)
Reshaping was the goal of lead compensator design
EE 3CL4, 6
39 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
Design principles:
Dont reshape the root locus
Adding the open loop pole and zero from the
EE 3CL4, 6
40 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
1
2
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Insights
EE 3CL4, 6
41 / 50
Tim Davidson
Example
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
1
Lets consider, again, the case with G(s) = s(s+2)
.
Design a lag compensator to achieve damping coefficient
= 0.5 and velocity error constant Kv > 20
EE 3CL4, 6
42 / 50
Example
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
43 / 50
Tim Davidson
Example
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
44 / 50
Example
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
KC (s+0.1)
(s+1/80)
EE 3CL4, 6
45 / 50
Example
Tim Davidson
Prop.-contr.
Lag contr.
5(s+0.1)
(s+0.9)
OL TF, GC (s)G(s)
5
s(s+2)
5(s+0.1)
1
(s+1/80) s(s+2)
Y (s)
R(s)
5
s(s+2)+5
5(s+0.1)
s(s+2)(s+1/80)+5(s+0.1)
CL poles
1 j2
CL zeros
0.1, ,
Compensators
Lead
compensation
Controller, GC (s)
Cascade
compensation
and
steady-state
errors
Lag
Compensation
CL TF,
CL TF, again
5
s2 +2s+5
4.999(1+7104 s)
s2 +1.909s+4.827
0.004
s+0.104
Insights
EE 3CL4, 6
46 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
Ramp response
EE 3CL4, 6
47 / 50
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
48 / 50
Tim Davidson
Step response
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
EE 3CL4, 6
50 / 50
Insights
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Insights
a closed loop
We can try to place the dominant closed-loop poles in
desired positions
One approach to doing that is lead compensator design
However, that typically requires the use of an amplifier
response
These insights also have frequency domain