2006-12-06 Page 1 of 25

Compensation of Dead Time in PID

Controllers

Advanced
Application Note

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.
 Compensation of Dead Time in PID Controllers
2006-12-06 Page 2 of 25

Table of Contents:
1 OVERVIEW............................................................................................................................................ 3

2 RECOMMENDATIONS ......................................................................................................................... 6

3 CONFIGURATION................................................................................................................................. 7

4 TEST RESULTS .................................................................................................................................. 11

5 REFERENCES .................................................................................................................................... 25

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 Compensation of Dead Time in PID Controllers
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1 Overview

PID controllers with dead time compensation are reported to eliminate dead time in terms of a controller
seeing the effect of changes in its controller output. For set point changes where all the controller needs
to be concerned with is how its output responds to a new set point, the results are impressive for an exact
knowledge of the process dead time. However, for unmeasured load disturbances at the process input,
the ultimate performance is set by the total dead time from the process equipment, piping, control valves,
instrumentation, and digital devices. This application note shows that a dead time compensator can offer
some improvement in load rejection by facilitating more aggressive tuning of the PID but with a
considerable risk of oscillations from an inaccurate dead time.

The ultimate performance achievable in terms of load disturbance rejection depends upon the dead time.
In the “Theory” section of Chapter 2 of Advanced Control Unleashed equations are developed that show
the minimum peak error is proportional to the dead time and the minimum integrated error is proportional
to the dead time squared for unmeasured load upsets. How close the actual performance of a control
loop comes to this ultimate performance depends upon PID structure, tuning, and enhancements. This
blog focuses on the effect of variations in dead time on the performance and robustness of dead time
compensation as an enhancement and Lambda as a tuning rule for disturbance rejection. The two
predominant methods of dead time compensation studied here are the Smith Predictor PID and the PID
with a delayed external reset.

The Smith Predictor was extensively documented in the 1970s. It provides a new controlled variable that
is the response of the process variable to its controller output without dead time. It requires entry of three
parameters commonly known as process gain, dead time, and time constant. The Smith Predictor uses
these parameters to create models of the process from the controller output. In its most documented
form, the Smith predictor subtracts a model of the process with dead time from a model of the process
without dead time and adds the net result to the measured process variable to create a new controlled
variable. If the model is perfect, the new controlled variable has zero dead time in terms of the controller
seeing the effect of its own controller output. Since the maximum allowable controller gain is inversely
proportional to dead time, the controller gain can theoretically increased without limit for a perfect model
provided you ignore extenuating circumstances, such as loop interaction, measurement noise, and final
element dead band and resolution. One of the practical issues with the Smith Predictor is that the new
controlled variable of the PID is no longer the actual process variable. The original process variable must
be restored for the operator interface to the PID. Also, performance monitoring or trending must look at
the original process variable rather than the new controlled variable used by the PID. Terry Blevins
proposed in the 1979 ISA paper “Modifying the Smith Predictor for an Application Software Package” a
multiplicative and additive correction of the process variable to deal with changes in the slope (gain) and
intercept (bias), respectively in the process model.

The PID with a delayed external reset was informally presented in the 1980s and published in the early
1990s. It simply consists of putting a dead time (DT) block in the external reset. This method only requires
that a single parameter commonly known as process dead time be entered as the dead time in the DT
block. Terry Blevins documented in the early 1990s how the Smith Predictor for a particular Lambda
tuning reduces to this PID with a delayed external reset.

The delayed external reset method of dead time compensation has several advantages readily evident.
The user is not required to identify or estimate the process gain or process time constant. Also, the actual
process variable is left intact. Other possibilities also exist for a more informative external reset signal
than just the Analog Output (AO) block BKCAL_OUT, such as the use of read back actual valve position
from a Digital Valve Controller (DVC) or a secondary loop’s process variable for a cascade control loop.
These alternative external reset (ER) signals may potentially be able to compensate for dynamics and
disturbances of control valves or secondary loops. These ER signals can additionally protect the primary
controller from outrunning the slewing rate of the control valve or the response of the secondary loop and
prevent the walk off of override controllers. However, if a feedforward multiplier or split range block is

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.
 Compensation of Dead Time in PID Controllers
2006-12-06 Page 4 of 25

used, the signal used for external reset must be converted back to its original basis as the controller
output (e.g. divided by feedforward multiplier). For more details on the value and use of external reset,
see the article “The Power of External Reset Feedback” in the May 2006 issue of Control magazine.

The results presented here show that for a perfect model and the same controller tuning the PID with a
delayed external reset performed better for processes with a small dead time to time constant ratio (time
constant dominant), whereas the Smith Predictor performed better for processes with a large dead time to
time constant ratio (dead time dominant). The Smith Predictor did not do as well for small dead time to
time constant ratios because the control error seen in the controlled variable by the PID is much smaller
than the actual control error in the process variable. In both cases, the improvement was not as
impressive as the improvement gained from setting Lambda equal to the dead time rather than the time
constant. Surprisingly the improvement in load disturbance rejection from dead time compensation was
greater for processes with small dead time to time constant ratios. This goes against the conventional
wisdom that the best opportunity for dead time compensation is for dead time dominant loops. The results
can be explained in terms of the ultimate limit for performance of dead time dominant loops being lower.
The reduction in the peak excursion from more aggressive tuning settings is negligible for dead time
dominant processes because the peak error is essentially the open loop error.

Another startling result was how quickly a Smith Predictor erupted into rapidly growing oscillations in the
controller output when the model dead time was more than twice the actual process dead time. The fast
full scale oscillations in the controller output resembled on-off control. While it is relatively well known that
dead time compensators are sensitive to model mismatch, the effect was expected to be gradual and
thought to be more in terms of a model dead time being too small. The concern for rapid deterioration for
a model dead time being too large was raised in Good Tuning – a Pocket Guide and was documented for
model predictive control in Models Unleashed. While a PID with delayed external reset is also adversely
affected by a dead time mismatch in both directions, this PID develops a small amplitude high frequency
dither rather than a full scale oscillation in controller output for an excessively high model dead time. The
consequence is less severe and may be adequately handled by the addition of a small dither filter
inserted in the PID controller output, but this was not tested.

Another major point here is that PID controller tuning for self-regulating processes without extenuating
circumstances can only initiate oscillations for an identified (modeled) process dead time or gain that is
too small or an identified time constant that is too large. For PID controllers with dead time compensation
or model predictive controllers, high and low identified (model) values can cause oscillations.

In order to get the performance benefit from dead time compensation, the PID must be tuned more
aggressively. In other words, a PID with dead time compensation will perform the same as a PID without
dead time compensation if they are tuned the same. While the improvement in integrated absolute error
(IAE) for load upsets from more aggressive tuning (higher controller gain and lower reset time) can be
accurately estimated for a regular PID, the equation does not work well for a dead time compensator.
Furthermore, a dead time compensator soon reaches a point of diminishing returns. For example, the
improvement in load rejection of a Smith Predictor from a controller gain that is quadrupled may not be
noticeable whereas for a regular PID, it normally results in a four fold reduction in IAE. It is important to
remember there is a tradeoff between performance and robustness for any feedback controller in that as
you make controller tuning more aggressive to improve load rejection you make the controller more
sensitive to changes in the process gain, dead time, or time constant.

A nonlinear gain from the installed characteristic of a control valve has been widely discussed. However,
the nonlinearity of the process gain of the temperature or composition response is the inverse and
consequently the combined effect is less than documented when these loops directly manipulate a control
valve. The variability of dead time is often larger than the variability of the process gain or time constant
because the dead time is inversely proportional to a rate (e.g. flow rate or pumping rate or rate of change
of a signal) and has many different sources (e.g. valve deadband or resolution, piping transportation
delay, mixing delay, process lags in series, sensor lags, signal filters, and discrete communication or scan
intervals). Thus, it is problematic to compute the dead time accurately enough to get the benefit of a dead
time compensator.

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 Compensation of Dead Time in PID Controllers
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The calculation of process dead times and the role of PID structure will be addressed will be detailed in
Advanced Application Notes 004 and 005, respectively.

Only a small portion of the test results are included here as figures. A more complete compilation of test
results is posted on the web site under the category of “Continuous Control.” Information on disturbances,
dead time, and controller tuning is also posted on the this website under the categories of “Plant Design”
and “Tuning and Control System Performance”.

http://ModelingandControl.com

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 Compensation of Dead Time in PID Controllers
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2 Recommendations

To improve the performance of a PID controller for load disturbances at the process input:

(1) First improve the PID controller tuning before even considering dead time compensation. Setting
Lambda equal to the maximum dead time (Lambda factor equal to the maximum dead time to time
constant ratio) is effective for load disturbances at the process input if there are no extenuating
circumstances.

(2) Add feedforward control whenever it is possible to measure or infer load disturbances at the process
input.

(3) If there is economic justification for further improvement and the dead time can be updated within 25%
accuracy for varying operating conditions, trial test and closely monitor a PID with delayed external reset
for low dead time to time constant ratios.

(4) For loops with high dead time to time constant ratios, multiple manipulated variables, interactions, or
constraints, consider model predictive control.

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 Compensation of Dead Time in PID Controllers
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3 Configuration

A DeltaV library module template titled PID_DEADTIME is available for implementing the Smith Predictor
in DeltaV. It provides additional features such as a bias or process gain correction to the process model
for major load disturbances. This study used a simple Smith Predictor of the form commonly documented
in the literature.

Figure 3-1a shows the module used for testing the AC2 PID with a Smith Predictor. It includes a simple
process simulation that consists of an actuator and a first order plus dead time process. The three
process parameters are PROCESS_GAIN, PROCESS_DELAY, and PROCESS_LAG. The actuator can
simulate stroking lags, delay, deadband, and stick-slip but these were all set to zero or negligible values
for this study. The module also includes noise added to the AT2 block output and a periodic load upset
added to the process input. The load upset goes through a filter block whose filter time is the upset lag
(UPSET_LAG). If the upset lag is zero, the upset is a step change at the process input.

The Smith Predictor is a composite block shown in Figure 3-1a. The output of the AV2 block is the input
signal to the Smith Predictor. The three parameters provided to the Smith Predictor are MODEL_GAIN,
MODEL_DELAY, and MODEL_LAG. For a perfect model, these parameter values are equal to their
corresponding process parameter values. A DITHER_FILTER block was inserted between the AC2 OUT
and the AV2 block CAS_IN but it did nothing in these tests (filter time constant was kept at zero).

Note that in control literature, different nomenclature is often used for the three dynamic parameters of a
first order plus dead process or model. For each parameter below, the first name is the most common and
the last name is most specific.

process gain = plant gain = open loop gain

process dead time = plant delay = total loop dead time

process time constant = plant lag = open loop time constant

Figure 3-1b shows the drill down into the composite block. The Smith Predictor input signal is multiplied
by the model gain in the MLTY1 block and then goes through a filtered with a process lag in the FLTR1
block. The output of FILTR1 block is delayed via the DT1 block and subtracted in the SUB1 block from its
undelayed output. The Smith Predictor output is added in the main module via the SUM2 block to the
output of the PV2 block, which has added noise to the AT2 block output. If the model is perfect and there
are no disturbances or noise, the model with the delay cancels out the measured process variable from
the AI block. What is left is the process model without any dead time (delay). Any loop without dead time
and extenuating circumstances can have its controller gain increased without limit and still be stable.

A common mistake is to forget that the process variable used by PID as the controlled variable is no
longer the actual process variable but a model of the process response without dead time based solely on
the controller output. Trends of the AC2 PID PV will show a much smaller deviation from the set point and
a false sense of actual control loop performance.

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 Compensation of Dead Time in PID Controllers
2006-12-06 Page 8 of 25

Smith Predictor
Output

Figure 3-1a Test Module with Embedded Smith Predictor Composite Block

Smith Predictor
Embedded Composite

Figure 3-1b Drill Down of Embedded Smith Predictor Composite Block

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 Compensation of Dead Time in PID Controllers
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Figure 3-2a shows the test module for AC2 PID with delayed external reset. A dead time block
DELAY_COMP was inserted between the BKCAL_OUT of the AV2 block and the BKCAL_IN of the AC2
block. This method of dead time compensation requires just one parameter, which is the model dead time
(MODEL_DELAY). A DITHER_FILTER block was inserted between the AC2 OUT and the AV2 block
CAS_IN but it did nothing in these tests (filter time constant was kept at zero). This test module employs
the same type of process simulation used in the test module for the Smith Predictor.

Figure 3-2b shows that in order for external reset signal to be used, the Dynamic Reset Limit box must be
checked in FRSPID_OPTS for the AC2 PID.

This method dead time compensation has several advantages readily evident. The user is not required to
identify or estimate the process gain or process time constant. Also, the actual process variable is left
intact. Other possibilities also exist for a more informative external reset signal than just the Analog
Output (AO) block BKCAL_OUT, such as the use of read back actual valve position from a Digital Valve
Controller (DVC) or a secondary loop’s process variable for a cascade control loop. These alternative
external reset (ER) signals may potentially be able to compensate for dynamics and disturbances of
control valves or secondary loops. These ER signals can additionally protect the primary controller from
outrunning the slewing rate of the control valve or the response of the secondary loop and prevent the
walk off of override controllers. However, if a feedforward multiplier or split range block is used, the signal
used for external reset must be converted back to the original basis of the controller output (e.g. divided
by feedforward multiplier).

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 Compensation of Dead Time in PID Controllers
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Delayed
External
Reset

Figure 3-2a Test Model for PID with Delayed External Reset

Figure 3-2b Enabling of Dynamic Reset Limit in FRSPID_OPTS for PID with Delayed External Reset

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4 Test Results

In all of the test results the AC1 used for comparison purposes is always an uncompensated PID with
Lambda equal to the process time constant (lag), which is equivalent to a Lambda factor of one. All tests
have an unmeasured load disturbance at the process input. The first upset in each figure is for a step
disturbance. The second upset in each figure is for a disturbance that has been slowed down by a time
constant (upset lag) that is twice the original process dead time.

The first set of test results in Figure 4-1a through 4-1f illustrates the effect of different tuning for different
model accuracies for a low and high dead time to time constant ratio. Here AC2 is an uncompensated
PID with Lambda equal plant delay (process dead time) which is equivalent to a Lambda factor set equal
to the delay/lag ratio (dead time to time constant ratio).
Figures 4-1a through Figure 4-1c is for a control loop with a 0.2 delay/lag (dead time to time constant)
ratio. This ratio of 0.2 is seen in concentration and temperature control of columns and vessels where
there is a low degree of back mixing. Single large gas pressure volumes and highly agitated vessels with
a low turnover time can have a much lower delay/lag ratio if there is no significant additional dead time
associated with an analyzer, sensor, or wireless communication time. The improvement in the integrated
absolute error (IAE) is about 66% from setting the Lambda equal to the process dead time instead of the
process time constant and matches well the improvement predicted by Equations 2-2a and 2-2b in the
book New Directions in Bioprocess Modeling and Control. This IAE improvement holds up even for the
50% increase in plant delay in Figure 4-1b. For the 50% decrease in plant delay in Figure 4-1c, the IAE is
slightly less for both AC1 and AC2 but the per cent improvement is basically the same.
Figure 4-1d through Figure 4-1f is for a control loop with a 4.0 delay/lag (dead time to time constant) ratio.
This ratio of 4.0 is seen in concentration and temperature control of plug flow pipelines and exchanger
volumes where there is essentially no back mixing. This high ratio also occurs when chromatographs with
a cycle time and sample transportation delay much larger than the residence time of an agitated volume.
Even higher ratios occur for sheet thickness control. The improvement in the IAE is negligible but the AC2
controller is less oscillatory for the original plant delay and a 50% increase in plant delay (process dead
time). An upset lag makes both loops less oscillatory. For a decrease in plant delay both controllers have
a very smooth responses but the return to set point is noticeably faster for AC1.

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 Compensation of Dead Time in PID Controllers
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Load Upset IAE

Improvement (%)

AC2
AC1
AC2

AC1

Original Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = standard PI
(Lambda = Delay and Reset = Lag)

Figure 4-1a Uncompensated PID for 0.2 Delay/Lag Ratio and Original Plant Delay

Load Upset IAE

Improvement (%)

AC2
AC1
AC2

AC1

50% Increase in Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = standard PI
(Lambda = Delay and Reset = Lag)

Figure 4-1b Uncompensated PID for 0.2 Delay/Lag Ratio and 50% Increase in Plant Delay

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Load Upset IAE

Improvement (%)

AC2
AC1
AC2

AC1

50% Decrease in Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = standard PI
(Lambda = Delay and Reset = Lag)

Figure 4-1c Uncompensated PID for 0.2 Delay/Lag Ratio and 50% Decrease in Plant Delay

AC2
AC1 AC1

AC2

Original Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = standard PI
(Lambda = Delay and Reset = Lag)

Figure 4-1d Uncompensated PID for 4.0 Delay/Lag Ratio and Original Plant Delay

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AC1 AC2

AC1

AC2

50% Increase in Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = standard PI
(Lambda = Delay and Reset = Lag)

Figure 4-1e Uncompensated PID for 4.0 Delay/Lag Ratio and 50% Increase in Plant Delay

AC2
AC1
AC1

AC2

50% Decrease in Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = standard PI
(Lambda = Delay and Reset = Lag)

Figure 4-1f Uncompensated PID for 4.0 Delay/Lag Ratio and 50% Decrease in Plant Delay

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The second set of test results shows how well a Smith Predictor can do. Here AC2 is a Smith Predictor
PID with the gain doubled and the reset time halved after Lambda has again been set equal to the plant
delay (process dead time). In other words, this AC2 has twice the proportional and integral action of the
uncompensated AC2 in the first set of test results.

Figures 4-2a through Figure 4-2d is for a control loop with a 0.2 delay/lag ratio. The improvement in the
integrated absolute error (IAE) in Figure 4-2a is about 76% over the uncompensated conservatively tuned
AC1, which is about 10% better than an uncompensated more aggressively tuned AC2 in the first set of
test results. This improvement holds up for 50% changes in the plant delay as illustrated by Figure 4-2b
and Figure 4-2c. However, if the model delay is more than 100% higher than the plant delay, the Smith
Predictor breaks out into growing oscillations in the controller output as shown in Figure 4-2d. The risk of
essentially on-off control from a high model dead time may be an unacceptable risk.
Figures 4-2e through Figure 4-2h is for a control loop with a 4.0 delay/lag ratio. The Smith Predictor is
less oscillatory than the uncompensated conservatively tuned AC1 for the original plant delay and a
increase in plant delay shown in Figures 4-2e and Figure 4-2f. However, for an decrease in plant delay
shown in Figure 4-2g, which is normally thought of as a more stable condition, high frequency oscillations
start to appear. If the model delay is more than 100% higher than the plant delay, the Smith Predictor
breaks out into growing oscillations in the controller output as shown in Figure 4-2h.

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Load Upset IAE

Improvement (%)

AC2 AC1
AC2

AC1

Original Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2a Smith Predictor PID for 0.2 Delay/Lag Ratio and Original Plant Delay

Load Upset IAE

Improvement (%)

AC2
AC1
AC2

AC1

50% Increase in Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2b Smith Predictor PID for 0.2 Delay/Lag Ratio and 50% Increase in Plant Delay

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Figure 4-2c Smith Predictor PID for 0.2 Delay/Lag Ratio and 50% Decrease in Plant Delay

110% Increase in Model Delay

AC2
AC1

Original Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2d Smith Predictor PID for 0.2 Delay/Lag Ratio and 110% Increase in Model Delay

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AC2
AC1
AC1
AC2

Original Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2e Smith Predictor PID for 4.0 Delay/Lag Ratio and Original Plant Delay

AC2
AC1
AC1

AC2

50% Increase in Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2f Smith Predictor PID for 4.0 Delay/Lag Ratio and 50% Increase in Plant Delay

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AC2
AC1 AC1

AC2

50% Decrease in Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2g Smith Predictor PID for 4.0 Delay/Lag Ratio and 50% Decrease in Plant Delay

110% Increase in Model Delay

AC2

AC1

Original Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 (AT2/PV)= Smith Predictor PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-2h Smith Predictor PID for 4.0 Delay/Lag Ratio and 110% Increase in Model Delay

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 Compensation of Dead Time in PID Controllers
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The third set of test results shows how well a simpler type of dead time compensated PID reset can do.
Here AC2 is a PID with a delayed external reset. Like the Smith Predictor the gain is doubled and the
reset time halved after Lambda has again been set equal to the plant delay (process dead time). In other
words, this AC2 like the Smith predictor has twice the proportional and integral action of the
uncompensated AC2 in the first set of test results.

Figures 4-3a through Figure 4-3d is for a control loop with a 0.2 delay/lag ratio. The improvement in the
integrated absolute error (IAE) in Figure 4-3a is about 88% over the uncompensated conservatively tuned
AC1, which is about 22% better than an uncompensated more aggressively tuned AC2 in the first set of
test results. It is anticipated that the improvement increases as the delay/lag ratio decreases. The
improvement is large enough for this dead time compensator to be considered for low delay/lag
applications where the plant delay is accurately known. The improvement deteriorates and the response
becomes oscillatory for a 50% increase in the plant delay as illustrated by Figure 4-3b. A decrease in
plant delay has little as shown in Figure 4-3c. However, if the model delay is more than 100% higher than
the plant delay, the PID with a delayed external reset exhibits some decaying oscillations in the controller
output as shown in Figure 4-3d.
Figures 4-3e through Figure 4-3h is for a control loop with a 4.0 delay/lag ratio. The PID with a delayed
external reset does not have the slow oscillations seen in the uncompensated conservatively tuned AC1
for the original plant delay and 50% changes plant delay shown in Figures 4-3f through Figure 4-3g.
However, there is a persistent high frequency dither in the controller output. The a time constant could
have been set in the DITHER_FILTER block to help smooth this out. Control valve dead band and
resolution limits in the control valve may help prevent these oscillations from affecting the process. If the
model delay is more than 100% higher than the actual plant delay, the dither amplitude gets larger and
slower as shown in Figure 4-3h.

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Load Upset IAE

Improvement (%)

AC2 AC1
AC2

AC1

Original Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3a PID with Delayed External Reset for 0.2 Delay/Lag Ratio and Original Plant Delay

Load Upset IAE

Improvement (%)

AC2AC1
AC2

AC1

50% Increase in Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3b PID with Delayed External Reset for 0.2 Delay/Lag Ratio and 50% Increase in Plant Delay

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.
 Compensation of Dead Time in PID Controllers
2006-12-06 Page 22 of 25

Load Upset IAE

Improvement (%)

AC2 AC1
AC2

AC1

50% Decrease in Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3c PID with Delayed External Reset for 0.2 Delay/Lag Ratio and 50% Decrease in Plant Delay

110% Increase in Model Delay

AC2 AC1

Original Plant Delay

Original Delay/Lag Ratio = 0.2

Step Upset

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3d PID with Delayed External Reset for 0.2 Delay/Lag Ratio and 110% Increase in Model Delay

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.
 Compensation of Dead Time in PID Controllers
2006-12-06 Page 23 of 25

AC2
AC1 AC1

AC2

Original Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3e PID with Delayed External Reset for 4.0 Delay/Lag Ratio and Original Model Delay

AC2

AC1 AC1

AC2

50% Increase in Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3f PID with Delayed External Reset for 4.0 Delay/Lag Ratio and 50% Increase in Plant Delay

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.
 Compensation of Dead Time in PID Controllers
2006-12-06 Page 24 of 25

AC2

AC1
AC1

AC2

50% Decrease in Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset Slow Upset

Upset Lag = 2 ∗ Delay
AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3g PID with Delayed External Reset for 4.0 Delay/Lag Ratio and 50% Decrease in Plant Delay

110% Increase in Model Delay

AC2

AC1

Original Plant Delay

Original Delay/Lag Ratio = 4.0

Step Upset

AC1 = standard PI
(Lambda = Lag and Reset = Lag)
AC2 = dead time compensated PI
(Lambda = Delay and Reset = Lag
but with controller Gain increased
and Reset decreased by factor of 2)

Figure 4-3h PID with Delayed External Reset for 4.0 Delay/Lag Ratio and 110% Increase in Model Delay

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.
 Compensation of Dead Time in PID Controllers
2006-12-06 Page 25 of 25

5 References

1-1 Boudreau, Michael, A. and McMillan, Gregory K., New Directions in Bioprocess Modeling and Control –
Maximizing Process Analytical technology Benefits, Instrumentation, Automations, and Systems (ISA), 2006.
1-2 McMillan, Gregory, Good Tuning – a Pocket Guide, 2nd edition, Instrumentation, Automations, and Systems
(ISA), 2005.
1-3 McMillan, Gregory and Cameron, Robert, Models Unleashed – Virtual Plant and Model Predictive Control
Applications, Instrumentation, Automations, and Systems (ISA), 2004.
1-4 Blevins, Terrence L., McMillan, Gregory K., Wojsznis, Willy K., and Brown, Michael W., Advanced Control
Unleashed – Plant Performance Management for Optimum Benefits, Instrumentation, Automations, and
Systems (ISA), 2003.

Advanced Application Note 003 Rev A © Fisher–Rosemount Systems, 2007. All Rights Reserved.