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Definitions:
String of bits: b1 b2 b3 bn
MSB LSB
D b1 2 1 b2 2 2 b3 2 3 ... bn 2 n
where bi 0 or 1 based on some " switch"
position in the circuit
e.g. DAC:
vO kVREF D1
where k scale factor
b1 and VREF Reference voltage
b2 vO
D1 . DAC
b3
.
.
bn VFSR kVREF Full Scale Factor/Range
vO VFSR D1
VREF
VFSV 1 2 n VFSR vO MAX
Full Scale Value/Outp ut
MSB contribution to vO is VFSR/2
LSB contribution to vO is VFSR/2n
DR Dynamic Range 20 log10 2 n 20n log10 2 6n dB
Example
Consider n=3, VREF=1 and k=1.
Vomin= 0 2 0 2 0 2 0
1 2 3
7
Vomax= 1 2 1 1 2 2 1 2 3
8
Converters:Factors to consider
Speed
Accuracy
Resolution
Noise
Cost
Size
Specifications/Parameters:
Absolute (and relative) accuracy
Offset and gain errors
(non-)Linearity
Differential (non-)Linearity
Monotonicity (DAC) / Missing codes (ADC)
Conversion time & sampling rate (ADC)
Settling time & sampling rate (DAC)
Dynamic range
Ideal characteristics
vO
0.5 VFSR
111
110
101
100
011
010
001
vi
000
0.5 VFSR
Absolute accuracy:
refers to the inaccuracy due to all sources of error
maximum deviation of actual output from ideal
(design) output, consisting of,
Zero (Offset) error
Gain error
Linearity errors
Hysteresis errors ( usually small and due to
comparators)
Most easily expressed in fractions of 1 LSB
sometimes in terms of the LSB voltage output
(for DAC) or LSB voltage input (for ADC)
100
011
Zero 010
Error 001
000
000 010 100
001 011
Zero
Error
The Zero error is nulled by adjustment then gain
error is assessed.
DAC
Gain error: Deviation from design output voltage
for full-scale (FS) input code
ADC:
Gain error: Deviation from design input voltage
for FS output code
due to errors in reference voltage, resistors,
amplifier gains etc.
Gain
Gain error
error
111
110
101
100
011
010
001
000
000 010 100 110
001 011 101 0 111
Gain error is nulled by adjustment then:
Differential non-linearity:
DAC: Difference between actual output change
and ideal output voltage ( i.e. 1 LSB voltage)
change for a 1 LSB input code change.
Non-monotonicity occurs Vo starts to decrease
rather than increase with the increasing input code
transitions .
ADC: Difference between actual input voltage
change and ideal input voltage change ( 1LSB
voltage) for a 1 LSB output code change. If greater
than 1 LSB (+ or ) missing codes occur
Non-
monotonic
100
011
Missing
010
code
001
000
Solution:
VFSR 3.2
Ideally: 1 LSB = 3 0 .4 V
2n 2
1
Offset Error = v O (000) 0.2 V = +
2
LSB
1
Gain Error = 0.1 V =
4
LSB
Eliminate gain error by using scale factor: multiply all new values of vO by
2.8/2.7 (see table below)
Calculate INLk and DNLk for each value of code k
Note:
INLk = (Vk)actual (Vk)ideal where (Vk)actual is the
corrected(for zero and gain) output voltage at code
k, k = 0, 1, , 2n1 (in binary)
= Quantization interval
Model:
Quantizer
v(kT) vQ(kT)
vQ
Q
Q/2 Q/2 v
Quantizer characteristic
Q = vQ v
Q/2
Q/2 Q v
Q Q/2 3Q/2
Q/2
Quantization error
0.5R R
S3
vo
S2 0.25R
0.125R
S1
S S2 S 3 S 4
vo R 1
VREF where S i is up or down
R R R R
8 4 2
or in general
vO kV REF b1 2 1 b2 2 2 b3 2 3 b4 2 4 kVREF D
where bi 0 or 1 based on " switch" position
D b1 2 1 b2 2 2 b3 2 3 b4 2 4
and k 16
2R
2R
2R
2R
2R
v1
vk+1
R
R
vk
v2
vn
i1 i1
ik
ik+1
ik
in
i2
in
2R
VREF
2R
2R
2R
2R
2R
RHS LHS:
The equivalent resistance to the right of each
labelled node equals 2R
the current downward from each node = the
current to the right of the same node
twice that current enters node from the left
currents and node voltages are binary-weighted
1 1
i k 1 i v k 1 v k 1,2 ,... , n 1
2 k 2 k
2R
R
R
2 iS
i2
2 i3
2 i1
i4
i4
i1
i2
R
R
R
R
2
i3
VREF
RF
SW1
SW4
SW3
SW2
iO
vo
b3
b4
b1
b2
R1 RF
vo
2R
R
R
v1
2R
2R
2R
2R
W1
W4
W3
W2
S
S
S
S
VL
VH
b3
b4
b1
b2
2R
R
R
v1
R
2
R
2
R
2
R
2
VL
u1
u2
u4
u3
Thevenin Equiv.
R
R
R
v1
R
2
R
2
R
2
1
u 4 VL
u1
u2
u3
2
V L , when bi 0
ui
V H , when bi 1
bi V H V L V L
2R
1
voc voc 2 if u4 were removed, and voc 2 VL
2
By Superposition Principle :
R
2
1
voc voc 1 voc 2 u4 VL
2
VL
u4
2R
R
R
v1
R
2
R
2
R
2
1
u4 VL
u1
u2
u3
2
Similarly:
1 1
u1 u 2 u 3 u 4 V L
1 1
v1
2 2 2 2
1 2 3 4
u1 2 u 2 2 u3 2 u 4 2 VL 2 4
v1 (0000) 2 2 2 2 3 2 4 2 4 V L V L
1
v (0001) 2
1
1
2 2
2 3
2 4
V V
L H V L V L 2 4 V L V H V L 2 4
And so on
Scaled current source D/A
VCC
RREF S1 S2 S3
IREF
I1 I2 I3
Q1 Q2 Q3
QD
VBE
I out kI REF b1 2 1 b2 2 2 b3 2 3
For example :
I out kI REF
4 0 1 5 kI
REF
16 16
Types of A/D Converter (ADC)
Several types but we shall look at three
DAC-Based ADC
Flash converters
DAC-Based ADC
vi
CMP
vD/A
Osc/ Up-down
Clock Counter
D/A
VREF
Worst-case conversion time = (V) S1
where V is the voltage increment of the D/A and S
is the maximum slew rate of the input voltage
Dual-slope ADC inherently slow
R C
b1
b2 Counter Control Clock
Logic
bn
START EOC
A1 : unity gain buffer
A2 & RC : precision integrator
CMP : voltage comparator
v x Slope Slope
= vi /RC =VREF/RC
Integrate Integrate
vi VREF
Accumulated count, N
VREF 2n
v 2 NTCLK N bn ...b2 b1 vi
RC V REF
0.5R
CMP1
B0
R
CMP2
vi Logic
Control
R B1
CMP3
CMP4
0.5R