Subtractors

Half subtractors

Half subtractors represent the smallest block for subtraction in digital computers. What
they do is very simple: they subtract two bits, producing a difference and a borrow.

The logic is straightforward. Subtracting two 0s or two 1s results in 0. Subtracting 0 from

1 results in 1. Subtracting 1 from 0 results in a borrow where 1 is the borrow bit and 0 is
the difference bit.

0 - 0 = 0
0 - 1 = -1
1 - 0 = 1
1 - 1 = 0

The operation can be tabulated as follows:

Inputs Outputs
A B Bout D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Truth table for a half subtractor

The expressions for the borrow and difference bits are B A B and D A B .

The circuit for the half subtractor is the following:

OFFTIME = .5uS B U1A

ONTIME = .5uS CLK 1 B
DELAY = 5nS U3A 3
STARTVAL = 1 V
1 2 2
OPPVAL = 0 V
74LS04 74LS08

U2A
1 D
OFFTIME = 1uS A 3
ONTIME = 1uS CLK 2
DELAY = 5nS
V
STARTVAL = 1 V
74LS386A
OPPVAL = 0

Circuit for a half subtractor

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The half subtractor consists of an AND gate that provides the carry bit and an XOR gate
that provides the difference bit. An additional NOT gate is used to invert A and provide
the correct logic for the borrow bit.
In high-level schematics, the half subtractor is often shown as a block:

Half subtractor block

The waveforms for the half subtractor reflect the logic previously outlined:

A:1
B:1
U1A:Y
U2A:Y

0s 0.5us 1.0us 1.5us 2.0us

Time
Waveforms for a half subtractor

The half subtractor produces a borrow bit only when A is 0 and B is 1 and it produces a
difference bit only if one of the input bits is 1.

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Full subtractors

Full subtractors are the next step after half subtractors. What they do is very simple:
they subtract three bits and they produce a difference and a borrow.

The logic is not so straightforward.

The operation can be tabulated as follows:

Inputs Outputs
A B Bin Bout D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Truth table for a full subtractor

One of the bits is a borrow-in bit that comes from a previous stage. That bit is shown in
the third column. The borrow-out bit that results from the operation is passed on to a
higher level within the subtractor.

The expressions for the borrow and difference bits are:

Bout A B Bin A B D A B Bin

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The circuit for the full subtractor is the following:

OFFTIME = .5uS C U1A

ONTIME = .5uS CLK 1 U2A
DELAY = 5nS 3 1 D
STARTVAL = 1 V
2 3
OPPVAL = 0 2
74LS386A V
OFFTIME = 1uS B 74LS386A
ONTIME = 1uS CLK
DELAY = 5nS
STARTVAL = 1 V
OPPVAL = 0

OFFTIME = 2uS A
ONTIME = 2uS CLK
DELAY = 5nS
STARTVAL = 1 VCC
V U3A
OPPVAL = 0
U6A
2
1 3
3 1 U5A
VCC 2 1 B
3
74LS266 74LS08 2
R1 U4A
V
1 74LS32
U7A 3
1k 1 2 2

V1 74LS04 74LS08

5Vdc

Circuit for a full subtractor

The full subtractor is a little more complex than the previous circuits. It consists of 7
gates: 2 XOR, 1 XNOR, 2 AND, 1 NOT and 1 OR. The XOR gates provide the
difference bit while the rest of the gates provides the borrow bit. The 74LS266 XNOR
gate requires a pull-up resistor because it has an open collector.

In high-level schematics, the full subtractor is often shown as a block:

Block for a full subtractor

The waveforms for the full subtractor reflect the logic previously outlined:

A:1
B:1
C:1
U2A:Y
U5A:Y

0s 0.5us 1.0us 1.5us 2.0us 2.5us 3.0us 3.5us 4.0us

Time
Waveforms for a full subtractor

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