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4 nm
70 nm
High-k Gate Dielectrics
Made in 2002
by Durga Misra, Hiroshi Iwai, and Hei Wong
X 500
M
to the total oxide width) that any TM oxides have poor thermal stability
icroelectronics has been the most
nonuniformity in chemical composition and poor interface quality with the
important driving force for almost
and even the surface roughness can silicon substrate. In addition, the
all kinds of technology evolutions
cause pronounced fluctuations of the interface and oxide trap densities are
in the past four decades.1,2 The size
device characteristics. If we allow the one to three orders of magnitude larger
of the metal-oxide-semiconductor
oxide thickness to fluctuate with a half- than those in silicon oxide. Recently,
(MOS) transistor, which underpins Si
monolayer, which means 5% of the TM silicates such as HfSiOx have been
microelectronics, has been reduced to
oxide thickness, then the smallest oxide preferred because they have better
a factor of 1,000 (Fig. 1). Silicon MOS
film thickness to meet this tolerance is thermal stability compared to their
technology has now been developed
1.6 nm (Fig. 3), which is very close to oxides. The dielectric constant of TM
into two extremes: as fine as nanometer
the oxide thickness used in our current silicates is less than TM oxides but
size in the device structures and as
complementary (C)MOS technology. higher than silicon oxide.
large as gigascale in terms of number of
transistors in a chip. The downsizing If one could relax the fluctuation to The underlying physics for these
rate of the MOS component is really 8%, then the minimum thickness undesirable properties is governed
impressive; now, we have sub-100 nm would be 1 nm and could be used in primarily by the ionic nature of the TM-
gate length transistors in production the 80 nm technology node in these oxygen bonds. TM oxides are formed
and R&D for 5 nm gate length devices years. Introducing physically thicker by transferring the d-state and s-state
is also on the way.2 The technology high-k materials, while maintaining valence electrons of the metal into the
is expected to continue its historical the same value of the capacitance oxygen 3s or 3p empty orbitals. The
advancing rate with Moores law for required for controlling the current metal-oxygen bonds are more or less
a couple of decades although there flow in the channel, can resolve all the ionic. Because metal oxidation can take
are many constraints ahead (Fig.2).3 aforementioned problems. place easily, the oxide film would have
[Editorial Note: This topic has been a large amount of oxygen vacancies
addressed recently in these magazine High-k: The Hope of Next and would be easier to be partly
pages, see Interface, Spring 2005.] With Generation Gate Dielectrics crystallized. These mechanisms give
this trend, the silicon gate oxide will rise to the high trap density in metal
Introducing higher dielectric constant oxides. Because the TM elements can
be scaled down to its physical limit4
(k > 10) insulators [mainly transition also react with the substrate Si atoms at
to keep the proper functioning of the
metal (TM) oxides] is therefore low energy, they produce silicate and
transistors in the sub-10 nm technology
indispensable for the 70 nm technology silicide bonds.5 The interfacial metallic
node.
node and beyond, despite the fact that silicide bonds, working as interface
most of the high-k materials have much traps,5 can also lower the conduction
Physical and Technological poorer properties than the conventional band offset energy. The ionic or
Limits of Silicon Oxide silicon oxide which has been used as polarized metal-oxygen bonds are also
The gate oxide is the first device gate dielectric material for over 40 years. the reason for high-k values and the
dimension reaching the atomic scale There are many problems associated existence of soft optical phonons, which
(~10 ). The atomic scale gate dielectric with the ionic high-k materials. High k
has become the most critical constraint
for further downscaling of the MOS
Drain
transistors. Thirty years ago, the gate Gate
oxide thickness was 120 nm and now Source
tox= 12 nm
it is 1.2 nm in production, which is
much thinner than the direct tunneling
limit for SiO2 (about 3 nm). Power
consumption is a primary concern N+ Lg= N+
for high-performance logic integrated
10,000 nm
circuits with the tunneling gate oxide.
For 1.2 nm thick silicon oxide, the P substrate Made in 1972
gate leakage current density reaches
100 A/cm2 at 1 V (see Fig. 3). Such
large currents would not be acceptable
Gate
Gate Length:
Length:
in most applications. In the 70 nm
1.4 nm
technology node, the required gate LLgg(02)
(02) == 0.007xL
0.007xLgg(72)
(72)
oxide thickness is about 0.7 nm, which
is only two atomic layers of silicon
Gate
Gate Oxide:
Oxide:
70 nm
oxide and is the ultimate limit of bulk ttox(02) = 0.0012xt ox(72)
ox(02) = 0.0012xtox (72)
silicon oxide.4 However the actual Made in 2002
high-k materials, the properties of the
high-k/Si interfaces, the origins of the
defects, and the reliability issues of
the future gate dielectric materials are
discussed below.
10 nm
Deposition Techniques 3 nm
TM-based high-k dielectric materials 0.3 nm
are typically deposited on crystalline
silicon rather than thermally grown. To
achieve desired electrical characteristics
the deposited dielectric must have
excellent interfacial and bulk properties
in addition to good uniformity.
Appropriate processing reactors with
matching chemical precursors are
FIG. 2. Trend in MOS device parameter scaling and the prediction made in the 2003
therefore required such that many
International Technology Roadmap for Semiconductor (ITRS 2003).3
properties of the deposited dielectric
film can be optimized. Various
technologies such as (i) chemical
vapor deposition (CVD), (ii) plasma
enhanced chemical vapor deposition
(PECVD), (iii) metallorganic CVD
(MOCVD), (iv) atomic layer deposition
(ALD), (v) plasma enhanced atomic
layer deposition (PEALD), (vi) physical
and disadvantages, manufacturability
and production of excellent quality
metal oxides in CMOS devices is
their charge trapping characteristics.
Charge trapping can alter the threshold
voltage of transistors over time and
subsequently affect the defect nature
of the dielectrics. In addition to charge
trapping in the bulk high-k layer, the
contribution from the interface traps
present in between the high-k layer and
the interfacial layer and in between
the substrate and the interfacial layer,
is significant. As far as the deposition
method is concerned, charge trapping
in high-k dielectrics is almost identical
in both ALD and MOCVD deposited
HfO2 due to the large number of
FIG. 4. X-ray photoelectron spectra recorded for MOCVD HfO2 preexisting traps. As described earlier,
layers deposited at 485C (60 s deposition time) on different starting the origin of the preexisting traps is tied
surfaces. As a reference, a 1 nm rapid thermal oxide (RTO) and to the way these dielectrics are formed.
a Hf-silicate film are added. After deposition, a Hf-silicate like The energy levels of the traps in the
interfacial is formed for all starting surfaces.8 high-k dielectric bandgap are deep and
help in trap assisted tunneling. These
deep traps can be annealed but an
HfCl 4 Saturated Adsorption
increase in shallow traps may appear
due to crystallization of the high-k film.
Defects or leakage current have
Purge always been at the forefront with
Substrate the evolution of new technologies
or introduction of new materials in
CMOS technology. To match the
HCl properties of high-k dielectrics with
H2O those of conventional silicon oxide,
the existence of various defects and
HfO 2 how they affect the reliability through
Purge trapping of charge at the defect sites
must be looked at. In bulk high-k
devices, shallow electron traps at
the conduction bandedge have been
found to be inherent in the most
recent studies. These traps are closely
- HfO2(s) + 4HCl(g)
HfCl4(ad.) + 2H2O(g) -> related to charge transport and charge
redistribution during stress. The shallow
FIG. 5. Schematic of ALD process with alternating HfCl and H2O exposure9 to deposit HfO2 on traps, considered to be the root cause
silicon. of trapping, especially for low voltage
poststress leakage current is typically
slightly higher than the prestress
leakage at low positive and negative
gate biases, i.e., within the range of
trap-assisted tunneling regime. But at
comparatively high positive/negative
gate bias, poststress leakage current can
be lower than the prestress value. This
is a typical example of stress-induced
leakage current, which is attributed to
neutral trap generation. But, one must
be careful with high-k dielectrics as
shallow traps with energy levels lying
within 0.3-0.8 eV below the conduction
bandedge give rise to extensive electron
trapping during stress, which distorts
the internal electric eld. Signicant
relaxation induced detrapping takes FIG. 6. Transistor characteristics of different n-channel devices with high-k dielectrics as
place after the stress. Detrapping from gate materials and with similar EOT.
shallow traps may also occur during
poststress current-voltage measurement,
which increases poststress leakage even
in the trap-assisted tunneling regime.
Therefore, adequate time for relaxation
must be provided before a poststress
October 29-
November 2, 2006
Cancun, Mexico
Te c h n i c a l