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Abstract: The purpose of this work is to present the design flow and the
implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High
Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded
system architectures. The implemented control algorithm is a Sugeno model based
Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using
the HLS tool and the designing of the interfaces for the IP core are presented.
1. Introduction
For the control engineering, the neuro-fuzzy system has many favorable
features. First of all it combines both the neural network structures and the
fuzzy inference systems advantages. The neural network structure gives the
adaptability of the system, and the fuzzy logic part makes it possible to use a
linguistic rule base to describe the ideal behavior of the controlled system.
Beside the advantages of this kind of systems, there are some difficulties with
the real time implementation, because the algorithm requires complex
operations under time constrains. The sequential implementations in most of the
cases cannot work in real time, but a parallelized structure of the operations
could be a solution. There are many related works to the implementations of
neuro-fuzzy models, using different techniques [1], [2], [3]. The best platform
to realize embedded systems with parallel architectures is the Field
Programmable Gate Array (FPGA). With the flexibility of these devices it is
possible to create an efficient hardware implemented neuro-fuzzy controller.
The FPGA devices can be programmed using Hardware Description Languages
(HDL), this is an efficient way to create embedded hardware, but also requires
183 10.1515/macro-2015-0018
the main function, the inputs are the two inputs of the controller (X, Y) and the
third layers parameters (L3_par), and the outputs are the calculated control
signal (U), and the Ret parameter structure which contains data for the learning
algorithm. The Fuzzification function (L1) calculates the membership values for
each input value and returns to the main function the indices of the active
membership functions and the corresponding membership values.
255*|a|2b
(x) = (8)
|a|2b +|x-c|2b
We can see, that only 21% of the available DSP-s, 6% of the available flip-flops
and 10% of the available LUTs were utilized to generate the ANFIS IP core.
There are many training algorithms for this kind of systems [6], [7], [10]. The
learning algorithm implemented also in C language is running on the processor.
The Ret structure contains the indices of the active rules and the weights of the
second layer (w) for each active rule. The processors software refreshes the
parameters with the following formulas:
pindexX[i],indexY[i] = pindexX[i],indexY[i] + *error*X*w
[i] (9)
qindexX[i],indexY[i] = qindexX[i],indexY[i] + *error*Y*w
[i] (10)
rindexX[i],indexY[i] = rindexX[i],indexY[i] + *error*w
[i] (11)
Where indexX and indexY contains the indices of the active membership
functions on the two inputs, is the learning coefficient,
is the normalized
weight of the second layer.
4. Interfaces
The ANFIS IP core has two types of interfaces, AXI4Lite slave [8] interface
and BRAM interface. The whole architecture, containing the ANFIS IP core,
and the processor can be seen on the Figure 4. The X and Y inputs and the U
control signal, and the Rett data structure outputs of the ANFIS IP core are
using the AXI4Lite interface.
from the control signal values calculated according to the input values from the
X and Y axis.
Y
Figure 5: Reference surface
On the Figure 6 the surface generated from the simulations made with the
ANFIS IP core can be seen. We can see the evolution of the surface during the
training cycles. These plots are made after 5, 50, 75 and 100 training cycles.
There are used five membership functions for each input space with the
parameters shown in 2. Table. The reference surface contains 60 x 60 samples.
2. Table: Parameters of the membership functions
a - dispersion b - steepness c - center
MF1 128 1.5 0
MF2 128 1.5 256
MF3 128 1.5 512
MF4 128 1.5 768
MF5 128 1.5 1024
6. Conclusion
We have presented the hardware implementation of a neuro-fuzzy system
with high level synthesis tool. We proved the usability of the high level
synthesis tools in creation of efficient hardware architectures. The hardware
implemented with HLS requires less design time then other techniques, there
are many optimizing possibilities and a simple method to create interfaces.
Reasoning from the low latency, from the acceptable resource utilization and
the measurement results we can conclude that the ANFIS IP core can be used in
real-time control applications.
Acknowledgements
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