Integrated ICS86004-01

Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
GENERAL DESCRIPTION FEATURES
The ICS86004-01 is a high performance 1-to-4 4 LVCMOS/LVTTL outputs, 7 typical output impedance
ICS LVCMOS/LVTTL Clock Buffer and a member of
HiPerClockS the HiPerClockS family of High Performance
Single LVCMOS/LVTTL clock input
Clock Solutions from ICS. The ICS86004-01 has CLK accepts the following input levels: LVCMOS or LVTTL
a fully integrated PLL and can be configured as Output frequency range: 62.5MHz to 250MHz
zero delay buffer and has an input and output frequency range
of 62.5MHz to 250MHz. The external feedback allows the Input frequency range: 62.5MHz to 250MHz
device to achieve zero delay between the input clock and External feedback for zero delay clock regeneration
the output clocks. The PLL_SEL pin can be used to bypass with configurable frequencies
the PLL for system test and debug purposes. In bypass mode,
the reference clock is routed around the PLL and into the Fully integrated PLL
internal output divider. Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)
Output skew: 60ps (maximum)
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
5V tolerant input
Lead-Free package available
0C to 70C ambient operating temperature

CONTROL INPUT FUNCTION TABLE

Input/Output
Input
Frequency Range (MHz)
F_SEL Minimum Maximum
0 1 25 250
1 62.5 125

BLOCK DIAGRAM PIN ASSIGNMENT

PLL_SEL
Q0 Q1 1 16 VDDO
GND 2 15 Q2
8 0
Q0 3 14 GND
Q1 F_SEL 4 13 Q3
CLK 1 VDD 5 12 VDDO
CLK 6 11 MR
PLL Q2 GND 7 10 FB_IN
VDDA 8 9 PLL_SEL

1:1 Q3
FB_IN ICS86004-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View

MR

F_SEL

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

1
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 3, Q1, Q0,
Output Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels.
13, 15 Q3, Q2
2, 7, 14 GND Power Power supply ground.
Frequency range select input. When LOW, I/O frequency range is from
4 F_SEL Input Pulldown 125MHz to 250Mz. When HIGH, I/O frequency range is from
62.5MHz to 125MHz. LVCMOS/LVTTL interface levels.
5 VDD Power Core supply pin.
6 CLK Input Pulldown LVCMOS/LVTTL clock input.
8 VDDA Power Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
9 PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with "zero delay".
10 FB_IN Input Pulldown
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
11 MR Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
12, 16 VDDO Power Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input Pullup Resistor 51 K
RPULLDOWN Input Pulldown Resistor 51 K
CPD Power Dissipation Capacitance VDD, VDDA, VDDO = 3.465V 23 pF
(per output) VDD, VDDA, VDDO = 2.625V 17 pF
ROUT Output Impedance 3 .3 V 5 % 5 7 12

TABLE 3. CONTROL INPUT FUNCTION TABLE

Input/Output
Input
Frequency Range (MHz)
F_SEL Minimum Maximum
0 125 250
1 62.5 125

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

2
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
Inputs, VI -0.5V to VDD + 0.5 V
device. These ratings are stress specifications only. Functional
Outputs, VO -0.5V to VDDO + 0.5V operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
Package Thermal Impedance, JA 89C/W (0 lfpm)
istics is not implied. Exposure to absolute maximum rating
Storage Temperature, TSTG -65C to 150C conditions for extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 100 mA
IDDA Analog Supply Current 16 mA
IDDO Output Supply Current 6 mA

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
FB_IN, MR,
2 VDD + 0.3 V
VIH Input High Voltage PLL_SEL, F_SEL
CLK 2 VDD + 0.3 V
FB_IN, MR,
-0.3 0.8 V
VIL Input Low Voltage PLL_SEL, F_SEL
CLK -0.3 1.3 V
CLK, MR,
VDD = VIN = 3.465V 150 A
IIH Input High Current FB_IN, F_SEL
PLL_SEL VDD = VIN = 3.465V 5 A
CLK, MR,
VDD = 3.465V, VIN = 0V -5 A
IIL Input Low Current FB_IN, F_SEL
PLL_SEL VDD = 3.465V, VIN = 0V -150 A
VDDO = 3.465V 2 .6 V
VOH Output High Voltage; NOTE 1
VDDO = 2.625V 1.8 V
VOL Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V 0.5 V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagrams.

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

3
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 100 mA
IDDA Analog Supply Current 16 mA
IDDO Output Supply Current 6 mA

TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 2.375 2.5 2.625 V
VDDA Analog Supply Voltage 2.375 2.5 2.625 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 96 mA
IDDA Analog Supply Current 15 mA
IDDO Output Supply Current 6 mA

TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C

Symbol Parameter Test Conditions Minimum Typical Maximum Units
F_SEL = 0 125 25 0 MHz
fMAX Output Frequency
F_SEL = 1 62.5 125 MHz
PLL_SEL = 0V,
tpLH Propagation Delay, Low-to-High; NOTE 1 4.1 5.1 6.1 ns
Bypass Mode
t() Static Phase Offset; NOTE 2, 4 PLL_SEL = 3.3V -75 50 175 ps
tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 60 ps
F_SEL = 0 65 ps
tjit(cc) Cycle-to-Cycle Jitter ; NOTE 4
F_SEL = 1 45 ps
tL PLL Lock Time 1 mS
tR / tF Output Rise/Fall Time 30 0 750 ps
F_SEL = 0 44 50 56 %
odc Output Duty Cycle
F_SEL = 1 47 50 53 %
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

4
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
F_SEL = 0 12 5 25 0 MHz
fMAX Output Frequency
F_SEL = 1 62.5 125 MHz
PLL_SEL = 0V,
tpLH Propagation Delay, Low-to-High; NOTE 1 4.25 5.25 6.25 ns
Bypass Mode
t() Static Phase Offset; NOTE 2, 4 PLL_SEL = 3.3V -300 0 ps
tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 60 ps
F_SEL = 0 65 ps
tjit(cc) Cycle-to-Cycle Jitter ; NOTE 4
F_SEL = 1 45 ps
tL PLL Lock Time 1 mS
tR / tF Output Rise/Fall Time 300 700 ps
od c Output Duty Cycle 45 50 55 %
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C

Symbol Parameter Test Conditions Minimum Typical Maximum Units
F_SEL = 0 12 5 25 0 MHz
fMAX Output Frequency
F_SEL = 1 62.5 125 MHz
PLL_SEL = 0V,
tpLH Propagation Delay, Low-to-High; NOTE 1 4. 5 5.5 6. 5 ns
Bypass Mode
t() Static Phase Offset; NOTE 2, 4 PLL_SEL = 3.3V -100 250 ps
tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 55 ps
F_SEL = 0 65 ps
tjit(cc) Cycle-to-Cycle Jitter ; NOTE 4
F_SEL = 1 45 ps
tL PLL Lock Time 1 mS
tR / tF Output Rise/Fall Time 300 700 ps
od c Output Duty Cycle 45 50 55 %
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

5
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
PARAMETER MEASUREMENT INFORMATION

1.65V5% 2.05V5% 1.25V5%

VDD,
SCOPE VDD,
SCOPE
VDDA, VDDO VDDA
VDDO
Qx Qx
LVCMOS LVCMOS
GND
GND

-1.65V5% -1.25V5%

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

1.25V5%

VDD,
SCOPE V
DDO
V
DDO
V
DDO
Q0:Q3 2 2 2
VDDA, VDDO
Qx
LVCMOS tcycle n tcycle n+1

GND t jit(cc) = tcycle n tcycle n+1

1000 Cycles

-1.25V5%

2.5VCORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER

VDD
CLK 2
V
DDO
Qx 2
VDD
FB_IN 2
V
DDO t ()
Qy 2
t sk(o)
t () mean = Static Phase Offset
(where t () is any random sample, and t () mean is the average
of the sampled cycles measured on controlled edges)

OUTPUT SKEW STATIC PHASE OFFSET

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

6
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER

VDDO VDDO VDDO

80% 80%
Q0:Q3 2 2 2
t PW
20% 20%
t PERIOD Clock
Outputs tR tF

t PW
odc =
t PERIOD

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME

VDD
CLK 2

VDDO
Q0:Q3 2
tpLH

PROPAGATION DELAY

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

7
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS86004-01 provides 3.3V
separate power supplies to isolate any high switching VDD
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO .01F 10
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
VDDA
used for each pin. To achieve optimum jitter performance,
.01F 10F
power supply isolation is required. Figure 1 illustrates how
a 10 resistor along with a 10F and a .01F bypass
capacitor should be connected to each VDDA. FIGURE 1. POWER SUPPLY FILTERING

SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of using an ICS86004-01. possible to the power pin. The low pass filter R7, C11 and C16 for
It is recommended to have one decouple capacitor per power clean analog supply should also be located as close to the VDDA
pin. Each decoupling capacitor should be located as close as pin as possible.

R1 43

VDD Zo = 50

Serial Termination

R3
1K
VDD

U1 R2 43
VDD
1 16 Zo = 50
2 Q1 VDDO 15
3 GND Q2 14
4 Q0 GND 13
Ro ~ 7 Ohm 5 F_SEL Q3 12
6 VDD VDDO 11
Zo = 50 7 CLK MR 10
R8 43 8 GND FB_IN 9
VDD VDDA PLL_SEL R11 43
LVCMOS
ICS86004-01 Zo = 50
R7
10 VDD R6

1K
C16 C11 VDD
10u 0.01u Parallel Termination
(U1-5) (U1-12) (U1-16)
VDD
R4
100
C1 C2 C3
0.1uF 0.1uF 0.1uF Zo = 50
VDD=3.3V
R5
100

FIGURE 2. ICS86004-01 SCHEMATIC EXAMPLE

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

8
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
RELIABILITY INFORMATION

TABLE 5. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP

JA by Velocity (Linear Feet per Minute)

0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 137.1C/W 118.2C/W 106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards 89.0C/W 81.8C/W 78.1C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT
The transistor count for ICS86004-01 is: 2496

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

9
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP

TABLE 6. PACKAGE DIMENSIONS

Millimeters
SYMBOL
Minimum Maximum
N 16
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 4.90 5.10
E 6.40 BASIC
E1 4.30 4.50
e 0.65 BASIC
L 0.45 0.75
0 8
aaa -- 0.10
Reference Document: JEDEC Publication 95, MO-153

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

10
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number Marking Package Count Temperature
ICS86004BG-01 86004B01 16 Lead TSSOP 94 per tube 0C to 70C
ICS86004BG-01T 86004B01 16 Lead TSSOP on Tape and Reel 2500 0C to 70C
ICS86004BG-01LF 6004B01L 16 Lead "Lead-Free" TSSOP 94 per tube 0C to 70C
16 Lead "Lead-Free" TSSOP
ICS86004BG-01LFT 6004B01L 2500 0C to 70C
on Tape and Reel

The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

11
 Integrated ICS86004-01
Circuit
Systems, Inc.
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL
ZERO DELAY CLOCK BUFFER
REVISION HISTORY SHEET

Rev Table Page Description of Change Date

Throughout data sheet, changed par t number from ICS86004I-01 to
A 12/16/03
ICS86004-01.
1 Features section - added Lead-Free bullet.
A 9/7/04
T7 11 Ordering Information table - added Lead Free par t number.
Changed temperature range throughout the data sheet from "-40C - 85C" to
A 11/2/04
"0C - 70C".

86004BG-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 2, 2004

12
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

 Texas Instruments
http://www.ti.com

This file is the datasheet for the following electronic components:

ICS86004-01 - http://www.ti.com/product/ics86004-01?HQS=TI-null-null-dscatalog-df-pf-null-wwe