Overview of DUT and Project

Chapter 2
Project Overview
In this part of the course, you develop a verification environment for
the YAPP router design using the OVM class library.
The environment is developed from scratch through a series of
exercises.
You build one Open Verification Component (OVC).

The second OVC is provided for you later in the project.

YAPP stands for Yet Another Packet Protocol

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DUT: YAPP Router (Yet Another Packet Protocol)

YAPP Packet Router

8
8 data_0
in_data
data_vld_0
in_data_vld
suspend_0
in_suspend
8
data_1
DUT data_vld_1
suspend_1
registers
8
reset data_2
clock MAXPKTSIZE data_vld_2
8 ROUTER_EN
hdata suspend_2
8
haddr
hen Host I/F error
hwr_rd

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Packet Router DUT Specification
The packet router accepts data packets on a
single input port, in_port, and routes the
packets to one of three output channels:
channel0, channel1, or channel2. It has
a host interface for programming registers Packet Structure
that are described on the next page 7 6 5 4 3 2 1 0
A packet is a sequence of bytes with the first length
length addr byte 0 Header
byte containing a header, the next variable
set of bytes containing payload, and the last payload[0] byte 1
byte containing parity.
payload[1]
The header consists of a 2-bit address field Payload
and a 6-bit length field. The address field is
used to determine which output channel the
packet is routed to (address 3 is illegal). payload[N-1] byte N
The length field specifies the number of data
bytes (payload). parity byte N+1 Parity
A packet has a payload minimum size of 1
byte and a maximum size of 63 bytes.
The parity should be a byte of even, bitwise
parity, calculated over the header and
payload bytes of the packet.

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 YAPP Input Port Protocol
clock
delay
data_vld
data H D D D P H D D D P

suspend

sent packet Packet 1 Packet 2

H = Header, D = Data, P = Parity

All input signals are active high and are to be driven on the falling edge of the clock.
data_vld must be asserted on the same clock when the first byte of a packet (the header
byte), is driven onto the data bus. Because the header byte contains the address, this tells
the router to which output channel the packet should be routed.
Each subsequent byte of data will be driven on the data bus with each new falling clock.
After the last payload byte has been driven, on the next falling clock, the data_vld signal
must be deasserted, and the packet parity byte should be driven.
The input data cannot change while suspend signal is active (indicating FIFO full).

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Packet Router DUT Registers Specification
Registers
7 6 5 4 3 2 1 0
length
MAXPKTSIZE addr 0 address
ROUTER_ENABLE 1

There are two registers accessed through the host interface port as follows:
1. MAXPKTSIZE 8 bits, address 0
R/W reset value = 3F
2. ROUTER_ENABLE bit 0, address 1
R/W reset value = 1

If input packet length is greater than value of MAXPKTSIZE register, the router
drops the entire packet.
The ROUTER_ENABLE register provides control of disabling the routing feature.
Enabling/Disabling the router during packet transmission will yield to unpredictable
behavior

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Host Protocol
The host port provides synchronous read/write access to program the router.
clock

hen

hwr_rd

hdata D D
haddr A A

transaction write read

A = Address, D = Data
write takes one clock cycle as follows:
hwr_rd and hen need to be 1. On next rising edge of clock, data on hdata is read
into the register given by haddr. hen can be driven to 0 in the next cycle
read takes two clock cycles as follows:
hwr_rd needs to be 0 and hen needs to be 1 in first cycle. Address on haddr is
read on rising edge of clock and hdata is driven by the DUT in cycle 2. hen can be
driven low after cycle 2 ends. This will cause the DUT to tri-state hdata bus.

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