Chapter 7 Exercise 1 - SOLUTION

Word
Assume main memory contains the following: 000 00 00 14 0
000 01 00 26 1
000 10 00 102 2
000 11 00 54 3
001 00 00 63 4
001 01 00 18 5
001 10 00 53 6
001 11 00 265 7
010 00 00 31 8

You have a 4-word, direct-mapped cache:

valid tag data

00 Y 000 001 010 14 63 31

01 N
10 Y 000 102
11 N

a) How many bits are needed for the index? cache size = 4, log2 4 = 2 (22 = 4)

b) How many bits are needed for the tag? Assume 32-bit addresses, even though
only the last seven bits are shown. 32 - 2 bits index - 2 bits byte offset = 28

c) Show how the following address references would be stored in cache:

000 00 00
000 10 00
001 00 00
000 10 00
010 00 00

d) Were there any hits? Is there competition? One hit: second reference to word 2.
Three addresses are competing for cache location 0.
 Chapter 7 Exercise 2 - SOLUTION

Draw the layout, including valid, tag and data fields, for:
a) 4-word cache, direct-mapped with one-word blocks
b) 4-word cache, direct-mapped with two-word blocks.

Indicate how many index and tag bit for each organization

Now show hits, misses, and final cache contents for the following address references:
0,1,3,5,4,8,5,9

Note: Leave the addresses in decimalyou don't need to show bit patterns.

Main Memory Block

a) 4-word cache, direct-mapped, 1-word block 0 0 0
2 index bits, 32-2 (index) - 2 (byte offset) = 28 tag 1 1
2 2 1
3 3
valid tag data 4 4
0%4=0 2
5 5
00 0 4 8 1%4=1 6 6 3
01 1 5 9 3%4=3 7 7
10 5%4=1 8 8 4
11 3 9 9
4%4=0
8%4=0
5 % 4 = 1 HIT
9%4=1

b) 4-word cache, direct-mapped with two-word blocks.

1 index bit, 32 - 1(index) - 2 (byte offset) - 1 (block offset) = 28 tag
valid tag data data 0/2=0%2=0
1 / 2 = 0 % 2 = 0 HIT
00 Y 0 4848 15959 3/2=1%2=1
01 Y 2 3 5/2=2%2=0
4 / 2 = 2 % 2 = 0 HIT
8/2=4%2=0
5/2=2%2=0
What's the advantage of 2-word blocks? 9/2=4%2=0
Preload when sequential access

What's the disadvantage?

If same amount of cache, may have more competition
 Chapter 7 Exercise 3 - SOLUTION

Miss penalty 30 cycles

Instruction miss rate of 2%
Data cache miss rate of 5%
Memory access (loads and stores) 30%
CPI 2 if no memory stalls

What is CPI?

.02 * 30 cycles = .6
.05 * .3 * 30 cycles = .45
.6 + .45 + 2 = 3.05 CPI

What if data cache miss rate is 2%?

.02 * .3 * 30 = .18 + .6 + 2 = 2.78 CPI

Chapter 7 Exercise 5 SOLUTION

Assume cache of 16K words, 8-word block size, 32-bit address. Determine the byte
offset/index/tag bits and total cache size (can leave as formula) for:
8-word block size = 3 bit block offset (23 = 8), 2 bit byte offset = 5 bits
OR can think of as
8-word block size * 4 bytes/block = 32 byte block size = 5 bits (25 = 32)

a) Direct-mapped (16K words/8 words/block = 2K cache locations)

2K cache blocks = 11 index bits (211 = 2048)
32 - 11 - 5 = 16 tag bits. Total size: 2K * (1 + 16 + (8 * 32))
b) Two-way set associative
1K sets = 10 index bits (210 = 1024)
32 - 10 - 5 = 17 tag bits. Total size: 1K * 2 * (1 + 17 + (8 * 32))
c) Four-way set associative
512 sets = 9 index bits (29 = 512)
32 - 9 - 5 = 18 tag bits. Total size: 512 * 4 * (1 + 18 + (8 * 32))
d) Fully associative
2K cache blocks, no index bits
32 - 5 = 27 tag. Total size: 2K * (1 + 27 + (8 * 32))