Catalogo - ON - Semiconductors 23.88

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DL131/D
Rev. 4, Mar-2000
CMOS Logic Data
ON Semiconductor
ON Semiconductor
CMOS Logic Data

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
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SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by
customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
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DL131/D 03/00
DL131
REV 4
CMOS Logic Data
This book presents technical data for the broad line of CMOS logic integrated circuits and demonstrates ON Semicon-
ductors continued commitment to MetalGate CMOS. Complete specifications are provided in the form of data sheets.
In addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been included to familiarize
the user with these circuits.
DL131/D
Rev. 4, March2000
SCILLC, 2000
Previous Edition 1991
All Rights Reserved
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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Table of Contents
Page
Chapter 1 Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Alphanumeric Listing of All CMOS Part Numbers with Function and Page Number Information Provided
Chapter 2 Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CMOS Selection Guide Sorted by Product Function
Chapter 3 Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Explanation of On Semiconductors Outgoing Product Performance Audit Program
Chapter 4 B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Explanation of Standardized Specifications for the Product Family
Chapter 5 CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Propagation Delay and Rise Time versus Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 6 CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

See the Master Index for Page Numbering Information
Chapter 7 CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Optimizing the Long Term Reliability of Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Chapter 8 Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Chapter 9 Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
ON Semiconductor Major Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
ON Semiconductor Standard Document Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
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CHAPTER 1
Master Index
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5
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6
MASTER INDEX
Device Function Page

MC14001B Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14001UB Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MC14008B 4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MC14011B Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14011UB Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14013B Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
MC14014B 8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MC14015B Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MC14018B Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC14020B 14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC14023B Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14024B 7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MC14025B Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14027B Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MC14028B BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MC14040B 12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
MC14043B Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14044B Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14046B PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14051B 8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14052B Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14053B Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14060B 14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
MC14067B 16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC14071B Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14073B Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14076B Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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MC14081B Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14082B Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14093B Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
MC14094B 8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
MC14099B 8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
MC14174B Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MC14175B Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
MC14503B Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
MC14511B BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
MC14512B 8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
MC14513B BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259
MC14514B 4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14515B 4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
MC14517B Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14521B 24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
MC14526B Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
MC14532B 8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
MC14543B BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354
MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
MC14551B Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
MC14553B 3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
MC14555B Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383
MC14556B Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
MC14557B 1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
MC14562B 128Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
MC14569B Programmable Dual 4Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 399
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
MC14585B 4Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
MC14598B 8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
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CHAPTER 2
Product Selection Guide
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CMOS Selection Guide by Function
NAND Gates
MC14011B Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14011UB Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14023B Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
NOR Gates
MC14001B Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14001UB Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14025B Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AND Gates
MC14081B Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14073B Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14082B Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Complex Gates
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Inverters/Buffers/Level Translator
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
MC14503B Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Decoders/Encoders
MC14028B BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MC14511B BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
MC14513B BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259
MC14543B BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354
MC14514B 4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14515B 4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14532B 8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
MC14555B Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383
MC14556B Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Multiplexers/Demultiplexers/Bilateral Switches
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
MC14551B Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
MC14053B Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14052B Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14067B 16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MC14051B 8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14512B 8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Schmitt Triggers
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OR Gates
MC14071B Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FlipFlops/Latches
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
MC14043B Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14044B Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14076B Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
MC14175B Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MC14013B Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
MC14027B Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MC14174B Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MC14099B 8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
MC14598B 8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Shift Registers
MC14015B Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MC14517B Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
MC14562B 128Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
MC14557B 1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
MC14094B 8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Counters
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MC14018B Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC14020B 14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC14024B 7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MC14040B 12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MC14060B 14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14526B Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
MC14553B 3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
MC14569B Programmable Dual 4Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Oscillators/Timers
MC14521B 24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Multivibrators
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Adders/Comparators
MC14008B 4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MC14585B 4Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Other Complex Functions
MC14046B PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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CHAPTER 3
Reliability Audit Program
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RAP"
Reliability Audit Program
For Logic Integrated Circuits
1.0 INTRODUCTION
The Reliability Audit Program developed in March 1977 Reliability and Quality Handbook which contains data for
is the ON Semiconductor internal reliability audit which is all ON Semiconductor devices (HBD851/D).
designed to assess outgoing product performance under RAP is a system of environmental and electrical tests
accelerated stress conditions. Logic Reliability Engineering performed periodically on randomly selected samples of
has overall responsibility for RAP, including updating its standard products. Each sample receives the tests specified
requirements, interpreting its results, administration at in section 2.0. Frequency of testing is specified per internal
offshore locations, and monthly reporting of results. These document 12MRM15301A.
reports are available at all sales offices. Also available is the
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2.0 RAP TEST FLOW
Pull 500* piece sample from lot following Group A

acceptance.
45* 340 100
INITIAL
SEAL**
OP LIFE
40 HOURS
PTHB PTH*** TEMP CYCLES
48 HRS 48 HRS 40 CYCLES
INTERIM
ELECTRICAL
INTERIM
TEST
OP LIFE
210 HRS (ADDITIONAL)
INTERIM ADD 460 CYCLES
ELECTRICAL FINAL
INTERIM INTERIM #
TEST ELECTRICAL
ADD 500 CYCLES

FINAL
PTH INTERIM*
48 HRS TEST
(ADDITIONAL)
OP LIFE #
750 HRS
TEMP CYCLES #
(ADDITIONAL)
1000 CYCLES
(ADDITIONAL)
FINAL FINAL
ELECTRICAL ELECTRICAL
(48 HRS) (96 HRS) FINAL #
FINAL
ELECTRICAL
ELECTRICAL
(1000 HRS)
& SEAL**
(2000 CYCLES)
SCRAP SCRAP SCRAP
#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.
* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.
** Seal (Fine & Gross Leak) required only for hermetic products.
*** PTH to be used when sockets for PTHB are not available.
3.0 TEST CONDITIONS AND COMMENTS

PTHB 15 psig/121C/100% RH at rated VCC or VEE 3. Sampling to include all package types routinely.
to be performed on plastic encapsulated devices 4. Device types sampled will be by generic type within each
only. logic I/C product family (CMOS, TTL, etc.) and will
TEMP CYCLING MILSTD883, Method 1010, include all assembly locations (Korea, Philippines,
Condition C, 65C/+ 150C. Malaysia, etc.).
OP LIFE MILSTD883, Method 1005, Condition C
v
5. 16 hrs. PTHB is equivalent to approximately 800 hours
(Power plus Reverse Bias), TA = 145C. of 85C/85% RH THB for VCC 15 V.
NOTES: 6. Only moisture related failures (like corrosion) are criteria
1. All standard 25C dc and functional parameters will be for failure on PTHB test.
measured Go/No/Go at each readout. 7. Special device specifications (48As) for logic products
2. Any indicated failure is first verified and then submitted will reference 12MRM15301A as source of generic data
to the Product Analysis Lab for detailed analysis. for any customer required monthly audit reports.
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CHAPTER 4
B and UB Series Family Data
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B AND UB SERIES FAMILY DATA
The CMOS Devices in this volume which have a B or UB Devices with specialized inputs, such as oscillator
suffix meet the minimum values for the industry inputs, have unique input specifications.
standardized* family specification. These standardized
values are shown in the Maximum Ratings and Electrical Input Voltage
Characteristics Tables. In addition to a standard minimum The input voltage specification is interpreted as the
specification for characteristics the B/UB devices feature: worstcase input voltage to produce an output level of 1 or
0. This 1 or 0 output level is defined as a deviation
318 volt operational limits
from the supply (VDD) and ground (VSS) levels. For a 5.0 V
Capable of driving two lowpower TTL loads or one
supply, this deviation is 0.5 V; for a 10 V supply, 1.0 V; and
lowpower Schottky TTL load over the rated
for 15 V, 1.5 V. As an example, in a device operating at a 5.0
temperature range
V supply, the device with the input starting at ground is
Direct Interface to HighSpeed CMOS guaranteed to switch on or before 3.5 V and not to switch up
Maximum input current of 1 A at 15 volt power to 1.5 V. Switching and not switching are defined as within
supply over the temperature range 0.5 V of the ideal output level for the example with a 5.0 V
Parameters specified at 5.0, 10, and 15 volt supply supply. The actual switching level referred to the input is
Noise margins: B Series between 1.5 V and 3.5 V.
1.0 V min @ 5.0 V supply
2.0 V min @ 10 V supply Noise Margin
2.5 V min @ 15 V supply The values for input voltages and the defined output
deviations lead to the calculated noise margins. Noise
UB Series margin is defined as the difference between VIL or VIH and
0.5 V min @ 5.0 V supply Vout (output deviation). As an example, for a noninverting
1.0 V min @ 10 V supply buffer at VDD = 5.0 volts: VIL = 1.5 volts and Vout = 0.5
1.0 V min @ 15 V supply volts. Therefore, Noise Margin equals VIL Vout = 1.0 volt.
The industrystandardized maximum ratings are shown at This figure is useful while cascading stages (See Figure 1).
the bottom of this page. Limits for the static characteristics With the input to the first stage at a worstcase voltage level
are shown in two formats: Table 1 is in the industry format (VIL = 1.5 V), the output is guaranteed to be no greater than
and Table 2 is in the equivalent ON Semiconductor format. 0.5 volts with a 5.0 volt supply. Since the maximum
The ON Semiconductor format is used throughout this data allowable logic 0 for the second stage is 1.5 volts, this 0.5
book. Additional specification values are shown on the volt output provides a 1.0 volt margin for noise to the next
individual data sheets. stage.
Switching characteristics for the B and UB series devices
are specified under the following conditions: Output Drive Current
Load Capacitance, CL, of 50 pF Devices in the B Series are capable of sinking a minimum
Input Voltage equal to VSS VDD (RailtoRail of 0.36 mA over the temperature range with a 5.0 V supply.
swing) This value guarantees that these CMOS devices will drive
Input pulse rise and fall times of 20 ns one lowpower Schottky TTL input.
Propagation Delay times measured from 50% point of
B Series vs UB CMOS
input voltage to 50% point of output voltage
The primary difference between B series and UB series
Three different supply voltages: 5, 10, and 15 V
devices is that UB series gates and inverters are constructed
Exceptions to the B and UB Series Family with a single inverting stage between input and output. The
Specification decreased gain caused by using a single stage results in less
There are a number of devices which have a B or UB suffix noise immunity and a transfer characteristic that is less ideal.
whose inputs and/or outputs vary somewhat from the family The decreased gain is quite useful when CMOS Gates and
specification because of functional requirements. Some inverters are used in a Linear mode to form oscillators,
categories of notable exceptions are: monostables, or amplifiers. The decreased gain results in
increased stability and a cleaner output waveform. In
Devices with specialized outputs on the chip, such as
addition to linear operation, the UB gates and inverters offer
NPN emitterfollower drivers or transmission gates,
an increase in speed, since only a single stage is involved.
do not meet output specifications.
The B and UB series, and devices with no suffix can be
used interchangeably in digital circuits that interface to other
CMOS devices, such as HighSpeed CMOS Logic.
* Specifications coordinated by EIA/JEDEC SolidState Products Council.
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MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol

Parameters Value Unit

VDD DC Supply Voltage 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V
10

Iin, lout Input or Output Current (DC or Transient), per Pin mA

PD Power Dissipation, per Package 500 mW
Tstg Storage Temperature 65 to + 150 _C

TL

Lead Temperature (8Second Soldering)
* Maximum Ratings are those values values beyond which damage to the device may occur.
Temperature Derating:
260 _C
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C

Ceramic L Packages: 12 mW/_C From 100_C To 125_C
5.0 V
VIL = 1.5 V Vout = 0.5 V Vout
FIRST STAGE VIL = 1.5 V SECOND STAGE

(NONINVERTING BUFFER) (NONINVERTING BUFFER)
Figure 1.

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications
ELECTRICAL CHARACTERISTICS

Limits

TLOW* + 25_C THIGH*
Temp VDD
Parameter Range (Vdc) Conditions Min Max Min Max Min Max Units

IDD

Quiescent

Device Current

Mil 5
10
15
Vin = VSS or VDD
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
Adc

GATES

Comm 5
10
All valid input
combinations
1.0
2.0
1.0
2.0
7.5
15
Adc

15 4.0 4.0 30
Adc

Mil 5 1.0 1.0 30
10 VIN = VSS or VDD 2.0 2.0 60

15 4.0 4.0 120

BUFFERS, Comm 5 All valid input 4 4.0 30 Adc

FLIPFLOPS 10 combinations 8 8.0 60
15 16 16.0 120

Mil 5
10
15
VIN = VSS or VDD
5
10
20
5
10
20
150
300
600
Adc

MSI

Comm 5
10
All valid input
combinations
20
40
20
40
150
300
Adc

15 80 80 600

VOL LowLevel All 5 0.05 0.05 0.05 Vdc
Output Voltage 10 VIN = VSS or VDD 0.05 0.05 0.05

15 |IO| < 1 A 0.05 0.05 0.05

VOH HighLevel All 5 4.95 4.95 4.95 Vdc

Output Voltage

10

VIN = VSS or VDD

9.95

9.95

9.95

15 |IO| < 1 A 14.95 14.95 14.95
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Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)

Temp VDD TLOW*
Limits
+ 25_C THIGH*

Parameter Range (Vdc) Conditions Min Max Min Max Min Max Units

VIL Input All 5 VO = 0.5V or 4.5V 1.5 1.5 1.5 Vdc
Low Voltage#

10 VO = 1.0V or 9.0V 3.0 3.0 3.0
B Types 15 VO = 1.5V or 13.5V 4.0 4.0 4.0

|IO| < 1 A

VIL Input All 5 VO = 0.5V or 4.5V 1.0 1.0 1.0
Low Voltage# 10 VO = 1.0V or 9.0V 2.0 2.0 2.0

UB Types

15 VO = 1.5V or 13.5V
|IO| < 1 A
2.5 2.5 2.5

VIH Input All 5 VO = 0.5V or 4.5V 3.5 3.5 3.5 Vdc
High Voltage# 10 VO = 1.0V or 9.0V 7.0 7.0 7.0

B Types 15 VO = 1.5V or 13.5V 11.0 11.0 11.0
|IO| < 1 A

VIH

Input

High Voltage#

All 5
10
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
4.0
8.0
4.0
8.0
4.0
8.0
Vdc

UB Types 15 VO = 1.5V or 13.5V 12.5 12.5 12.5
|IO| < 1 A

IOL

Output Low

(Sink) Current

Mil 5 VO = 0.4V,
VIN = 0 or 5V 0.64 0.51 0.36
mAdc

10 VO = 0.5V,
VIN = 0 or 10V 1.6 1.3 0.9

15 VO = 1.5V,

VIN = 0 or 15V 4.2 3.4 2.4

Com 5 VO = 0.4V, mAdc
VIN = 0 or 5V 0.52 0.44 0.36

10 VO = 0.5V,
VIN = 0 or 10V 1.3 1.1 0.9

15 VO = 1.5V,
VIN = 0 or 15V 3.6 3.0 2.4

IOH Output High Mil VO = 4.6V, mAdc
(Source) Current 5 VIN = 0 or 5V 0.25 0.2 0.14

VO = 9.5V,

10 VIN = 0 or 10V 0.62 0.5 0.35
VO = 13.5V,

15 VIN = 0 or 15V 1.8 1.5 1.1

Com VO = 4.6V, mAdc

5 VIN = 0 or 5V 0.2 0.16 0.12
VO = 9.5V,

10 VIN = 0 or 10V 0.5 0.4 0.3
VO = 13.5V
IIN

Input Current

Mil
15
15
VIN = 0 or 15V
VIN = 0 or 15V
1.4
0.1
1.2
0.1
1.0
1.0 Adc

Comm 15 VIN = 0 or 15V 0.3 0.3 1.0 Adc

Ioz 3State Output Mil 15 VIN = 0 or 15V 0.4 0.4 12 Adc
Leakage Current Comm 15 VIN = 0 or 15V 1.6 1.6 12 Adc

CIN

per unit load
Input Capacitance

All Any Input 7.5
* TLOW = 55_C for Military temperature range device, 40C for Commercial temperature range device.
pF
THIGH = + 125_C for Military temperature range device, + 85_C for Commercial temperature range device.
#Applies for Worst Case input combinations.
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Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specifications

VDD 55_C 25_C + 125_C

Characteristic Symbol Vdc Min Max Min Max Min Max Unit

Output Voltage 0 Level VOL 5.0 0.05 0.05 0.05 Vdc
Vin = VDD or 0 10 0.05 0.05 0.05

15 0.05 0.05 0.05

1 Level VOH 5.0 4.95 4.95 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 9.95

15 14.95 14.95 14.95

Input Voltage B Types 0 Level VIL Vdc

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 11
Input Voltage UB Types 0 Level VIL Vdc

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

5.0
10
15

1.0
2.0
2.5

1.0
2.0
2.5

1.0
2.0
2.5

(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)

1 Level VIH
5.0
10
4.0
8.0

4.0
8.0

4.0
8.0

Vdc

(VO = 1.5 or 13.5 Vdc)

Output Drive Current B Gates

IOH
15 12.5 12.5 12.5
mAdc

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3

0.36
0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 2.4
Output Drive Current UB Gates IOH mAdc

(VOH = 2.5 Vdc)

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)

Source 5.0
5.0
10
1.2
0.25
0.62

1.0
0.2
0.5

0.7
0.14
0.35

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc)

Sink IOL
15
5.0
1.8
0.64

1.5
0.51

1.1
0.36

(VOL = 0.5 Vdc) 10 1.6 1.3 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 2.4

Output Drive Current Other Devices IOH mAdc

(VOH = 4.6 Vdc) Source 5.0 0.64 0.51 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 2.4

(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 0.51 0.36
(VOL = 0.5 Vdc) 10 1.6 1.3 0.9

Input Current
(VOL = 1.5 Vdc)

Iin
15
15
4.2

0.1
3.4

0.1
2.4

1.0 Adc

Input Capacitance (Vin = 0) Cin 7.5 pF
Adc

Gate Quiescent Current IDD 5.0 0.25 0.25 7.5
(Per Package) 10 0.5 0.5 15

15 1.0 1.0 30

FlipFlop and Buffer Quiescent Current IDD 5.0 1.0 1.0 30 Adc
(Per Package) 10 2.0 2.0 60

15 4.0 4.0 120

MSI Quiescent Current IDD 5.0 5.0 5.0 150 Adc
(Per Package) 10 10 10 300

15 20 20 600

LSI Quiescent Current IDD See Individual Data Sheets.
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CHAPTER 5
CMOS Handling and Design Guidelines
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HANDLING AND DESIGN GUIDELINES
HANDLING PRECAUTIONS a CMOS device, a resistor should be used in series
with the input. This resistor helps limit accidental
All MOS devices have insulated gates that are subject to
damage if the PC board is removed and brought into
voltage breakdown. The gate oxide for ON Semiconductor
contact with static generating materials. The limiting
CMOS devices is about 900 thick and breaks down at a
factor for the series resistor is the added delay. This is
gatesource potential of about 100 volts. To guard against
caused by the time constant formed by the series
such a breakdown from static discharge or other voltage
resistor and input capacitance. Note that the maximum
transients, the protection networks shown in Figures 1A and
input rise and fall times should not be exceeded. In
1B are used on each input to the CMOS device.
Figure 2, two possible networks are shown using a
Static damaged devices behave in various ways,
series resistor to reduce ESD (Electrostatic
depending on the severity of the damage. The most severely
Discharge) damage. For convenience, an equation for
damaged inputs are the easiest to detect because the input
added propagation delay and rise time effects due to
has been completely destroyed and is either shorted to VDD,
series resistance size is given.
shorted to VSS, or opencircuited. The effect is that the
5. All CMOS devices should be stored or transported in
device no longer responds to signals present at the damaged
materials that are antistatic. CMOS devices must not
input. Less severe cases are more difficult to detect because
be inserted into conventional plastic snow,
they show up as intermittent failures or as degraded
styrofoam, or plastic trays, but should be left in their
performance. Another effect of static damage is that the
original container until ready for use.
inputs generally have increased leakage currents.
6. All CMOS devices should be placed on a grounded
Although the input protection network does provide a
bench surface and operators should ground
great deal of protection, CMOS devices are not immune to
themselves prior to handling devices, since a worker
large static voltage discharges that can be generated during
can be statically charged with respect to the bench
handling. For example, static voltages generated by a person
surface. Wrist straps in contact with skin are strongly
walking across a waxed floor have been measured in the
recommended. See Figure 3 for an example of a
4 15 kV range (depending on humidity, surface conditions,
typical work station.
etc.). Therefore, the following precautions should be
7. Nylon or other static generating materials should not
observed:
come in contact with CMOS devices.
1. Do not exceed the Maximum Ratings specified by the
8. If automatic handlers are being used, high levels of
data sheet.
static electricity may be generated by the movement
2. All unused device inputs should be connected to VDD
of the device, the belts, or the boards. Reduce static
or VSS.
buildup by using ionized air blowers or room
3. All lowimpedance equipment (pulse generators,
humidifiers. All parts of machines which come into
etc.) should be connected to CMOS inputs only after
contact with the top, bottom, or sides of IC packages
the device is powered up. Similarly, this type of
must be grounded to metal or other conductive
equipment should be disconnected before power is
material.
turned off.
9. Cold chambers using CO2 for cooling should be
4. Circuit boards containing CMOS devices are merely
equipped with baffles, and the CMOS devices must be
extensions of the devices, and the same handling
contained on or in conductive material.
precautions apply. Contacting edge connectors wired
10. When leadstraightening or handsoldering is
directly to device inputs can cause damage. Plastic
necessary, provide ground straps for the apparatus
wrapping should be avoided. When external
used and be sure that soldering ties are grounded.
connections to a PC board are connected to an input of
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INPUT PROTECTION NETWORK
VDD VDD
CMOS CMOS
TO CIRCUIT
INPUT INPUT
< 1500 300
VSS VSS
Figure 1a. Input Protection Network Figure 1b. Input Protection Network
Double Diode Triple Diode
11. The following steps should be observed during wave 13. The use of static detection meters for production line
solder operations: surveillance is highly recommended.
a. The solder pot and conductive conveyor system of 14. Equipment specifications should alert users to the
the wave soldering machine must be grounded to presence of CMOS devices and require
an earth ground. familiarization with this specification prior to
b. The loading and unloading work benches should performing any kind of maintenance or replacement
have conductive tops which are grounded to an of devices or modules.
earth ground. 15. Do not insert or remove CMOS devices from test
c. Operators must comply with precautions sockets with power applied. Check all power supplies
previously explained. to be used for testing devices to be certain there are no
d. Completed assemblies should be placed in voltage transients present.
antistatic containers prior to being moved to 16. Double check test equipment setup for proper polarity
subsequent stations. of VDD and VSS before conducting parametric or
12. The following steps should be observed during functional testing.
boardcleaning operations: 17. Do not recycle shipping rails or trays. Repeated use
a. Vapor degreasers and baskets must be grounded to causes deterioration of their antistatic coating.
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor RECOMMENDED FOR READING:
degreaser immediately upon removal from the
antistatic container. Total Control of the Static in Your Business
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the Available by writing to:
cleaning basket. 3M Company
e. High velocity air movement or application of Static Control Systems
solvents and coatings should be employed only P.O. Box 2963
when assembled printed circuit boards are Austin, Texas 787692963
grounded and a static eliminator is directed at the Or by Calling:
board. 18003281368
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VDD
CMOS D1 CMOS
TO OFFBOARD R1 INPUT TO OFFBOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT OUTPUT
D2
Advantage: Requires minimal board area Advantage: R2 < R1 for the same VSS
level of protection.
Disadvantage: R1 > R2 for the same level of Impact on ac and dc
protection, therefore rise and fall characteristics is minimized
times, propagation delays, and output
drives are severely affected. Disadvantage: More board area, higher initial cost
Note: These networks are useful for protecting the following
A digital inputs and outputs C 3state outputs
B analog inputs and outputs D bidirectional (I/O) ports
PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
where: C@k
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven devices
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations
Figure 2. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility
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4 NOTES: 1. 1/16 inch conductive sheet stock covering bench
top work area.
2. Ground strap.
1 3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
2
5. Room humidifier. Primarily for use in areas where
5 the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
3 buildings to be less than outside humidity.
RESISTOR =
1 MEGAOHM
Figure 3. Typical Manufacturing Work Station
POWER SUPPLIES the possibility of latchup related failures. This system

protection can be provided by the power supply filter and/or
CMOS devices have low power requirements and the voltage regulator.
ability to operate over a wide range of supply voltages. CMOS devices can be used with battery or battery backup
These two characteristics allow CMOS designs to be systems. A few precautions should be taken when designing
implemented using inexpensive, conventional power batteryoperated systems:
supplies, instead of switching power supplies and power 1. The recommended power supply voltage should be
supplies with cooling fans. In addition, batteries may be used observed. For battery backup systems such as the one
as either a primary power source or for emergency backup. in Figure 5, the battery voltage must be at least 3.7
The absolute maximum power supply voltage for 14000 Volts (3 Volts from the minimum power supply
Series Metalgate CMOS is 18.0 Vdc. Figure 4 offers some voltage and 0.7 Volts to account for the voltage drop
insight as to how this specification was derived. In the across the series diode).
figure, VS is the maximum power supply voltage and IS is 2. Inputs that might go above the battery backup voltage
the sustaining current of the latchup mode. The value of VS should either use a series resistor to limit the input
was chosen so that the secondary breakdown effect may be current to less than 10 mA or use the MC14049UB or
avoided. MC14050B hightolow voltage translators.
In an ideal system design, a power supply should be 3. Outputs that are subject to voltage levels above VDD
designed to deliver only enough current to insure proper or below VSS should be protected with a series resistor
operation of all devices. The obvious benefit of this type to limit the current to less than 10 mA or with
design is cost savings; an added benefit is protection against clamping diodes.
IDD
LATCH
UP MODE
SECONDARY
BREAKDOWN
LOW CURRENT
JUNCTION
IS
AVALANCHE
VS VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING
Figure 4. Secondary Breakdown Characteristics
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POWER SUPPLY
BATTERY BACKUP
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM
MC14049UB
CMOS CMOS
MC14050B
SYSTEM SYSTEM
MC14049UB
MC14050B
Figure 5. Battery Backup Interface
INPUTS VDD = 5.0 Vdc
All inputs, while in the recommended operating range

(VSS < Vin < VDD) can be modeled as shown in Figure 6. For
Vout , OUTPUT VOLTAGE (V)

input voltages in this range, diodes D1 and D2 are modeled SINGLE INPUT NAND, AND
as resistors, representing the reverse bias impedance of the MULTIPLE INPUT NOR, OR
5.0
diodes. The maximum input current is worst case, 1 A,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This 4.0 SINGLE INPUT NOR, OR
model does not apply to inputs with pullup or pulldown MULTIPLE INPUT NAND, AND
3.0
resistors.
2.0
1.0
VDD 0
0 1.0 2.0 3.0 4.0 5.0
R1 = R2 = HIGH Z
Vin, INPUT VOLTAGE (V)
R1
Figure 7. Typical Transfer Characteristics
for Buffered Devices
R2 7.5 pF For these reasons, all unused inputs should be connected

either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
Figure 6. Input Model for VSS vV vVin DD
used, as well as a series resistor for static protection and
current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
When left opencircuited, the inputs may selfbias at or
near the typical switchpoint, where both the Pchannel and FROM RS CMOS
Nchannel transistors are conducting, causing excessive EDGE
DEVICE
current drain. Due to the high gain of the inverters (see CONNECTOR
Figure 7), the device may also go into oscillation from any 100 k
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching. Figure 8. External Protection
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For input voltages outside of the recommended operating lout = 0 A. The output drives for all buffered CMOS devices
range, the CMOS input is modeled as in Figure 9. The are such that 1 LSTTL load can be driven across the full
resistordiode protection network allows the user greater temperature range.
v v
freedom when designing a worst case system. The device CMOS outputs are limited to externally forced output
inputs are guaranteed to withstand voltages from VSS 0.5 voltages of VSS 0.5 V Vout VDD + 0.5 V. When
V to VDD + 0.5 V and a maximum current of 10 mA. With voltages are forced outside of this range, a silicon controlled
the above input ratings, most designs will require no special rectifier (SCR) formed by parasitic transistors can be
terminations or design considerations. triggered, causing the device to latch up. For more
information on this, see the explanation of CMOS Latch Up
in this section.
The maximum rated output current for most outputs is
D1 10 mA. The output shortcircuit currents of these devices
1.5 k typically exceed these limits. Care must be taken not to
exceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
D2 7.5 pF
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
Figure 9. Input Model for Vin > VDD or Vin < VSS
CMOS LATCH UP
Other specifications that should be noted are the Latch up will not be a problem for most designs, but the
maximum input rise and fall times. Figure 10 shows the designer should be aware of it, what causes it, and how to
oscillations that may result from exceeding the 15 s prevent it.
maximum rise and fall time at VDD = 5.0 V, 5 s at 10 V, or Figure 11 shows the crosssection of a typical CMOS
4 s at 15 V. As the voltage passes through the switching inverter and Figure 12 shows the parasitic bipolar devices.
threshold region with a slow rise time, any noise that is on The circuit formed by the parasitic transistors and resistors
the input is amplified, and passed through to the output, is the basic configuration of a silicon controlled rectifier, or
causing oscillations. The oscillation may have a low enough SCR. In the latch up condition, transistors Q1 and Q2 are
frequency to cause succeeding stages to switch, giving turned ON, each providing the base current necessary for the
unexpected results. If input rise or fall times are expected to other to remain in saturation, thereby latching the devices in
exceed 15 s at 5.0 V, 5 s at 10 V, or 4 s at 15 V, the ON state. Unlike a conventional SCR, where the device
Schmitttrigger devices such as the MC14093B, is turned ON by applying a voltage to the base of the NPN
MC14584B, MC14106B, HC14, or HC132 are transistor, the parasitic SCR is turned ON by applying a
recommended for squaringup these slow transitions. voltage to the emitter of either transistor. The two emitters
that trigger the SCR are the same point, the CMOS output.
Therefore, to latch up the CMOS device, the output voltage
VDD must be greater than VDD + 0.5 V or less than VSS 0.5 V
and have sufficient current to trigger the SCR. The latchup
Vin
mechanism is similar for the inputs.
VSS
Once a CMOS device is latched up, if the supply current
is not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
VOH 1. Insure that inputs and outputs are limited to the
v
maximum rated values, as follows:
Vout 0.5 V Vin or Vout
v
VDD + 0.5 V (referenced to
VSS) |Iin or Iout| 10 mA (unless otherwise indicated
VOL
on the data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
Figure 10. Maximum Rise and Fall Time Violations protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
OUTPUTS to limit the expected worst case current to the
All CMOS BSeries outputs are buffered to insure maximum rating of 10 mA. (See Figure 2).
consistent output voltage and current performance. All 3. Sequence power supplies so that the inputs or outputs
buffered outputs have guaranteed output voltages of VOL = of CMOS devices are not active before the supply pins
0.05 V and VOH = VDD 0.05 V for Vin = VDD or VSS and are powered up (e.g., recessed edge connectors and/or
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series resistors may be used in plugin board 5. Limit the available power supply current to the
applications). devices that are subject to latchup conditions. This
4. Voltage regulating or filtering should be used in board can be accomplished with the power supply filtering
design and layout to insure that powersupply lines network or with a currentlimiting regulator.
are free of excessive noise.
PCHANNEL NCHANNEL
INPUT
VDD VDD PCHANNEL NCHANNEL VSS

OUTPUT
OUTPUT OUTPUT
N+
FIELD OXIDE
P+ P+
FIELD OXIDE
N+
N+ P+
FIELD OXIDE
N SUBSTRATE P WELL
Figure 11. CMOS Wafer Cross Section
Q1
NCHANNEL OUTPUT
N+ N+ N NSUBSTRATE RESISTANCE
VDD
VSS N
P
P+
VDD
VSS P
PWELL RESISTANCE P+
Q2 PCHANNEL OUTPUT
Figure 12. Latch Up Circuit Schematic
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CHAPTER 6
CMOS Logic Data Sheets
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MC14001B Series
B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
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The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure MARKING
(Complementary MOS). Their primary use is where low power DIAGRAMS
dissipation and/or high noise immunity is desired. 14
Supply Voltage Range = 3.0 Vdc to 18 Vdc PDIP14
MC140XXBCP
All Outputs Buffered P SUFFIX
CASE 646 AWLYYWW
Capable of Driving Two Lowpower TTL Loads or One Lowpower 1
Schottky TTL Load Over the Rated Temperature Range. 14
Double Diode Protection on All Inputs Except: Triple Diode SOIC14
140XXB
Protection on MC14011B and MC14081B D SUFFIX AWLYWW
PinforPin Replacements for Corresponding CD4000 Series B
CASE 751A
1
Suffix Devices 14
TSSOP14 14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
DT SUFFIX 0XXB
Symbol Parameter Value Unit CASE 948G ALYW
VDD DC Supply Voltage Range 0.5 to +18.0 V 1
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V 14
(DC or Transient) SOEIAJ14
F SUFFIX MC140XXB
Iin, Iout Input or Output Current 10 mA AWLYWW
CASE 965
(DC or Transient) per Pin
1
PD Power Dissipation, 500 mW
per Package (Note 2.) XX = Specific Device Code
A = Assembly Location
TA Ambient Temperature Range 55 to +125 C WL or L = Wafer Lot
Tstg Storage Temperature Range 65 to +150 C YY or Y = Year
WW or W = Work Week
TL Lead Temperature 260 C
(8Second Soldering)
DEVICE INFORMATION
1. Maximum Ratings are those values beyond which damage to the device
may occur. Device Description
2. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14001B Quad 2Input NOR Gate
This device contains protection circuitry to guard against damage due to high MC14011B Quad 2Input NAND Gate
static voltages or electric fields. However, precautions must be taken to avoid
MC14023B Triple 3Input NAND Gate
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
MC14025B Triple 3Input NOR Gate
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14071B Quad 2Input OR Gate
either VSS or VDD). Unused outputs must be left open.
MC14073B Triple 3Input AND Gate
MC14081B Quad 2Input AND Gate
MC14082B Dual 4Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 39 of this data sheet.
Semiconductor Components Industries, LLC, 2000 32 Publication Order Number:

March, 2000 Rev. 1 MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR NAND OR AND
MC14001B MC14011B MC14071B MC14081B

Quad 2Input NOR Gate Quad 2Input NAND Gate Quad 2Input OR Gate Quad 2Input AND Gate
1 1 1 1
3 3 3 3
2 2 2 2
5 5 5 5
2 INPUT
4 4 4 4
6 6 6 6
8 8 8 8
10 10 10 10
9 9 9 9
12 12 12 12
11 11 11 11
13 13 13 13
MC14025B MC14023B MC14073B MC14082B

Triple 3Input NOR Gate Triple 3Input NAND Gate Triple 3Input AND Gate Dual 4Input AND Gate
1 1 1 2
2 9 2 9 2 9
3 1
8 8 8
4
3 INPUT
3 3 3 5
4 6 4 6 4 6 9
5 5 5
10 13
11 11 11 11
12 10 12 10 12 10 12
13 13 13 NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001B MC14011B MC14023B MC14025B
Quad 2Input NOR Gate Quad 2Input NAND Gate Triple 3Input NAND Gate Triple 3Input NOR Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C
OUTA 3 12 IN 1D OUTA 3 12 IN 1D IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C
OUTB 4 11 OUTD OUTB 4 11 OUTD IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C
IN 1B 5 10 OUTC IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 3B 5 10 OUTC
IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C OUTB 6 9 OUTA OUTB 6 9 OUTA
VSS 7 8 IN 1C VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 3A
MC14071B MC14073B MC14081B MC14082B

Quad 2Input OR Gate Triple 3Input AND Gate Quad 2Input AND Gate Dual 4Input AND Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD
IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 1B 3 12 IN 2C OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 2B 4 11 IN 1C OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C OUTB 6 9 OUTA IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 1C VSS 7 8 NC
NC = NO CONNECTION
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33
MC14001B Series
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
55_C 25_C 125_C

Characteristic Symbol Vdc Min Max Min Typ (3.) Max Min Max Unit

Output Voltage 0 Level VOL 5.0 0.05 0 0.05 0.05 Vdc

Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

Input Voltage 0 Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc)

Sink IOL
15
5.0
4.2
0.64

3.4
0.51
8.8
0.88

2.4
0.36

mAdc

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4

Input Current

Iin 15 0.1 0.00001 0.1 1.0 Adc

(Vin = 0)
Input Capacitance

Cin 5.0 7.5 pF

Quiescent Current

(Per Package)

IDD 5.0
10
15

0.25
0.5
1.0

0.0005
0.0010
0.0015
0.25
0.5
1.0

7.5
15
30
Adc

Total Supply Current (4.) (5.)

(Dynamic plus Quiescent,

IT 5.0
10
IT = (0.3 A/kHz) f + IDD/N
IT = (0.6 A/kHz) f + IDD/N
Adc

Per Gate, CL = 50 pF) 15 IT = (0.9 A/kHz) f + IDD/N
3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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34
MC14001B Series
BSERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min Typ (7.) Max Unit

Output Rise Time, All BSeries Gates

tTLH = (1.35 ns/pF) CL + 33 ns
tTLH
5.0 100 200
ns

tTLH = (0.60 ns/pF) CL + 20 ns 10 50 100
tTLH = (0.40 ns/PF) CL + 20 ns 15 40 80

Output Fall Time, All BSeries Gates

tTHL = (1.35 ns/pF) CL + 33 ns
tTHL
5.0 100 200
ns

tTHL = (0.60 ns/pF) CL + 20 ns 10 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 40 80

Propagation Delay Time

MC14001B, MC14011B only

tPLH, tPHL ns

tPLH, tPHL = (0.90 ns/pF) CL + 80 ns 5.0 125 250
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns 10 50 100


All Other 2, 3, and 4 Input Gates


8Input Gates (MC14068B, MC14078B)


14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR
CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NONINVERTING 50%
*All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL
Figure 1. Switching Time Test Circuit and Waveforms
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35
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B MC14025B

One of Four Gates Shown One of Three Gates Shown
VDD VDD
14 VDD
1, 6, 8, 13 1, 3, 11
*
2, 5, 9, 12 2, 4, 12
14 VDD
3, 4, 10, 11
VSS
7 VSS 9, 6, 10
VSS
VDD
*Inverter omitted in MC14001B
8, 5, 13
7 VSS
VSS
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14023B, MC14073B MC14011B, MC14081B

One of Three Gates Shown One of Four Gates Shown
VDD 14 VDD
3, 4, 10, 11
2, 4, 12 14 VDD 2, 5, 9, 12
1, 3, 11 1, 6, 8, 13
VSS 7 VSS
* *Inverter omitted in MC14011B
VDD
9, 6, 10
8, 5, 13
7 VSS
VSS
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MC14001B Series
TYPICAL BSERIES GATE CHARACTERISTICS
NCHANNEL DRAIN CURRENT (SINK) PCHANNEL DRAIN CURRENT (SOURCE)

5.0 10
9.0
4.0 8.0 TA = 55C
ID , DRAIN CURRENT (mA)

7.0
TA = 55C 40C
3.0 6.0
40C
5.0
+ 85C + 25C + 25C
2.0 4.0 + 85C
+ 125C
3.0 + 125C
1.0 2.0
1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 1.0 2.0 3.0 4.0 5.0
VDS, DRAINTOSOURCE VOLTAGE (Vdc) VDS, DRAINTOSOURCE VOLTAGE (Vdc)
Figure 2. VGS = 5.0 Vdc Figure 3. VGS = 5.0 Vdc
20 50
18 45
TA = 55C
16 40
14 40C 35
12 + 25C 30 TA = 55C
+ 85C
10 25 40C
8.0 + 125C 20 + 25C
+ 85C
6.0 15
4.0 10 + 125C
2.0 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
Figure 4. VGS = 10 Vdc Figure 5. VGS = 10 Vdc
50 100
45 90
40 80
35 TA = 55C 70
30 40C 60
TA = 55C
25 + 25C 50 40C
20 + 85C 40 + 25C
+ 125C + 85C
15 30
+ 125C
10 20
5.0 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
Figure 6. VGS = 15 Vdc Figure 7. VGS = 15 Vdc

These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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MC14001B Series
TYPICAL BSERIES GATE CHARACTERISTICS (contd)
VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR MULTIPLE INPUT NOR, OR
10
4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0
1.0 2.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc
16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
12 from an ideal 1 or 0 input level which does not produce

SINGLE INPUT NOR, OR output state change(s). The typical and guaranteed limit
10 MULTIPLE INPUT NAND, AND values of the input values VIL and VIH for the output(s) to
8.0
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
6.0 in Figure 11.
Guaranteed minimum noise margins for both the 1 and
4.0
0 levels =
2.0 1.0 V with a 5.0 V supply
0 2.0 V with a 10.0 V supply
0 2.0 4.0 6.0 8.0 10
2.5 V with a 15.0 V supply
Vin, INPUT VOLTAGE (Vdc)
Figure 10. VDD = 15 Vdc
Vout VDD Vout VDD
VO VO
VO VO
VDD VDD
0 Vin 0 Vin
VIL VIH VIL VIH

VSS = 0 VOLTS DC
(a) Inverting Function (b) NonInverting Function
Figure 11. DC Noise Immunity
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38
MC14001B Series
ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMATION:

Device Package Shipping Device Package Shipping
MC14001BCP PDIP14 2000 Units per Box MC14071BCP PDIP14 2000 Units per Box
MC14001BD SOIC14 2750 Units per Box MC14071BD SOIC14 55 Units per Rail
MC14001BDR2 SOIC14 2500 Units / Tape & Reel MC14071BDR2 SOIC14 2500 Units / Tape & Reel
MC14001BDT TSSOP14 96 Units per Rail MC14071BDT TSSOP14 96 Units per Rail
MC14001BDTR2 TSSOP14 96 Units per Rail MC14071BDTR2 TSSOP14 96 Units per Rail
MC14011BCP PDIP14 2000 Units per Box MC14073BCP PDIP14 2000 Units per Box
MC14011BD SOIC14 2750 Units per Box MC14073BD SOIC14 55 Units per Rail
MC14011BDR2 SOIC14 2500 Units / Tape & Reel MC14073BDR2 SOIC14 2500 Units / Tape & Reel
MC14011BDT TSSOP14 96 Units per Rail
MC14011BDTEL TSSOP14 2000 Units / Tape & Reel MC14081BCP PDIP14 2000 Units per Box
MC14011BDTR2 TSSOP14 50 Units per Rail MC14081BD SOIC14 55 Units per Rail
MC14081BDR2 SOIC14 2500 Units / Tape & Reel
MC14023BCP PDIP14 2000 Units per Box MC14081BDT TSSOP14 96 Units per Rail
MC14023BD SOIC14 2750 Units per Box MC14081BDTR2 TSSOP14 2500 Units / Tape & Reel
MC14082BCP PDIP14 2000 Units per Box
MC14025BCP PDIP14 2000 Units per Box MC14082BD SOIC14 55 Units per Rail
MC14025BD SOIC14 2750 Units per Box MC14082BDR2 SOIC14 2500 Units / Tape & Reel
MC14025BDR2 SOIC14 2500 Units / Tape & Reel For ordering information on the EIAJ version of the SOIC pack-
ages, please contact your local ON Semiconductor representa-
tive.
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39
MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of http://onsemi.com
CMOS gates are inverting nonbuffered functions.
Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14001UB
Linear and Oscillator Applications Quad 2Input NOR Gate
Capable of Driving Two Lowpower TTL Loads or One Lowpower MC14011UB
Schottky TTL Load Over the Rated Temperature Range
Quad 2Input NAND Gate
Double Diode Protection on All Inputs
PinforPin Replacements for Corresponding CD4000 Series UB
Suffix Devices
MARKING
DIAGRAMS
14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) PDIP14
P SUFFIX MC140XXUBCP
Symbol Parameter Value Unit CASE 646 AWLYYWW
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V

(DC or Transient) 14
Iin, Iout Input or Output Current 10 mA SOIC14
140XXU
(DC or Transient) per Pin D SUFFIX AWLYWW
CASE 751A
PD Power Dissipation, 500 mW 1
per Package (Note 2.)
TA Ambient Temperature Range 55 to +125 C
Tstg Storage Temperature Range 65 to +150 C XX = Specific Device Code
WL or L = Wafer Lot
(8Second Soldering)
YY or Y = Year
1. Maximum Ratings are those values beyond which damage to the device WW or W = Work Week
may occur.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid Device Package Shipping
highimpedance circuit. For proper operation, Vin and Vout should be constrained MC14001UBCP PDIP14 2000/Box
MC14001UBD SOIC14 55/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open. MC14001UBDR2 SOIC14 2500/Tape & Reel
MC14011UBCP PDIP14 2000/Box
MC14011UBD SOIC14 55/Rail
MC14011UBDR2 SOIC14 2500/Tape & Reel

March, 2000 Rev. 3 MC14001UB/D
LOGIC DIAGRAMS
MC14001UB MC14011UB
Quad 2Input Quad 2Input
NOR Gate NAND Gate
1 1
3 3
2 2
5 5
4 4
6 6
8 8
10 10
9 9
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001UB MC14011UB
Quad 2Input NOR Gate Quad 2Input NAND Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD
IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D OUTA 3 12 IN 1D
OUTB 4 11 OUTD OUTB 4 11 OUTD
IN 1B 5 10 OUTC IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C
VSS 7 8 IN 1C VSS 7 8 IN 1C
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41

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 Vdc) 5.0 1.0 2.25 1.0 1.0

(VO = 9.0 Vdc) 10 2.0 4.50 2.0 2.0

(VO = 13.5 Vdc) 15 2.5 6.75 2.5 2.5

(VO = 0.5 Vdc) 1 Level IIH 5.0 4.0 4.0 2.75 4.0 Vdc
(VO = 1.0 Vdc) 10 8.0 8.0 5.50 8.0

(VO = 1.5 Vdc) 15 12.5 12.5 8.25 12.5


(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) 5.0 0.25 0.2 0.36 0.14

(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1

(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4

Input Current Iin 15 0.1 0.00001 0.1 1.0 Adc

Input Capacitance Cin 5.0 7.5 pF
(Vin = 0)

Quiescent Current
(Per Package)

IDD 5.0
10

0.25
0.5

0.0005
0.0010
0.25
0.5

7.5
15
Adc

15 1.0 0.0015 1.0 30

Total Supply Current (4.) (5.) IT 5.0 IT = (0.3 A/kHz) f + IDD/N Adc
(Dynamic plus Quiescent, 10 IT = (0.6 A/kHz) f + IDD/N

Per Gate CL = 50 pF)
15 IT = (0.8 A/kHz) f + IDD/N
where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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VDD

Characteristic Symbol Vdc Min Typ (7.) Max Unit

Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 180 360

tTLH = (1.5 ns/pF) CL + 15 ns 10 90 180

tTLH = (1.1 ns/pF) CL + 10 ns 15 65 130

Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 200

tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100

tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80

Propagation Delay Time tPLH, tPHL ns

20 ns 20 ns
VDD
14 INPUT VDD
90%
50%
PULSE INPUT OUTPUT 10% 0V
GENERATOR tPHL tPLH
* CL 90% VOH
OUTPUT 50%
INVERTING
10% VOL
7 VSS
*All unused inputs of AND, NAND gates must be tTHL tTLH
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.
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MC14001UB CIRCUIT SCHEMATIC MC14011UB CIRCUIT SCHEMATIC

(1/4 of Device Shown)
VDD
3 14 10
14 VDD
1 8
2 9
3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12
6 13 7 VSS
5 12
4 7 11
VSS
16 16
VDD = 15 Vdc TA = + 25C VDD = 15 Vdc Unused input
14 Unused input 14 connected to
b
Vout , OUTPUT VOLTAGE (Vdc)

connected to a VSS.
I D, DRAIN CURRENT (mAdc)
12 VSS. 12
10 Vdc a One input only 10 Vdc a TA = + 125C
10 b Both inputs 10
b TA = 55C
8.0 8.0 8.0
b a a b
6.0 6.0 6.0
5.0 Vdc 5.0 Vdc
15 Vdc
4.0 b a 4.0 4.0
a 10 Vdc a b
b
2.0 2.0 2.0
0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Figure 2. Typical Voltage and Figure 3. Typical Voltage Transfer

Current Transfer Characteristics Characteristics versus
Temperature
0 10
c a 15 Vdc
b a
VGS = 5.0 Vdc c
2.0 8.0
b VGS = 10 Vdc
a b
a TA = 55C
b TA = + 25C c
4.0 6.0
c TA = + 125C
a TA = 55C
c b TA = + 25C
6.0 4.0 c TA = + 125C
10 Vdc b
c a
8.0 b 15 Vdc 2.0
b 5.0 Vdc
c
a a
10 0
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)
Figure 4. Typical Output Source Figure 5. Typical Output Sink

Characteristics Characteristics
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44
MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multipurpose device consists of three
Nchannel and three Pchannel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulseshapers, linear amplifiers, high input http://onsemi.com
impedance amplifiers, threshold detectors, transmission gating, and
functional gating. MARKING
DIAGRAMS
Diode Protection on All Inputs 14
Capable of Driving Two Lowpower TTL Loads or One Lowpower P SUFFIX MC14007UBCP
AWLYYWW
CASE 646
PinforPin Replacement for CD4007A or CD4007UB
1
This device has 2 outputs without ESD Protection. Antistatic 14

SOIC14
precautions must be taken. 14007U
D SUFFIX AWLYWW
CASE 751A
1
14
TSSOP14 14
Symbol Parameter Value Unit
DT SUFFIX 007U
VDD DC Supply Voltage Range 0.5 to +18.0 V CASE 948G ALYW
(DC or Transient)
14
Iin, Iout Input or Output Current 10 mA SOEIAJ14
(DC or Transient) per Pin F SUFFIX MC14007U
CASE 965 AWLYWW
1
Tstg Storage Temperature Range 65 to +150 C WL or L = Wafer Lot
YY or Y = Year
TL Lead Temperature 260 C WW or W = Work Week
(8Second Soldering)
may occur. ORDERING INFORMATION
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C Device Package Shipping
This device contains protection circuitry to guard against damage due to high MC14007UBCP PDIP14 2000/Box
applications of any voltage higher than maximum rated voltages to this MC14007UBD SOIC14 55/Rail
to the range VSS v (Vin or Vout) vVDD. MC14007UBDR2 SOIC14 2500/Tape & Reel
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14007UBDT TSSOP14 96/Rail
MC14007UBF SOEIAJ14 See Note 1.
MC14007UBFEL SOEIAJ14 See Note 1.
1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

MC14007UB
PIN ASSIGNMENT
DPB 1 14 VDD
SPB 2 13 DPA
GATEB 3 12 OUTC
SNB 4 11 SPC
DNB 5 10 GATEC
GATEA 6 9 SNC
VSS 7 8 DNA
D = DRAIN
S = SOURCE
SCHEMATIC
14 13 2 1 11
6 12
7 8 3 4 5 10 9
VDD = PIN 14
VSS = PIN 7
A A
B 12 9
1 B
2
C 3
INPUT 4
VDD 5
14 C
11
13
INPUT OUTPUT CONDITION INPUT
6 8 10
1 A = C, B = OPEN
0 A = B, C = OPEN
7 VSS
Substrates of Pchannel devices internally
connected to VDD; substrates of Nchannel
devices internally connected to VSS.
Figure 1. Typical Application: 2Input Analog Multiplexer
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46
MC14007UB

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 Vdc) 5.0 1.0 2.25 1.0 1.0

(VO = 9.0 Vdc) 10 2.0 4.50 2.0 2.0

(VO = 13.5 Vdc) 15 2.5 6.75 2.5 2.5

(VO = 0.5 Vdc) 1 Level VIH 5.0 4.0 4.0 2.75 4.0 Vdc
(VO = 1.0 Vdc) 10 8.0 8.0 5.50 8.0

(VO = 1.5 Vdc) 15 12.5 12.5 8.25 12.5


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 5.0 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 1.0 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.5 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 10 2.4

(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 0.51 1.0 0.36 mAdc
(VOL = 0.5 Vdc) 10 1.6 1.3 2.5 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 10 2.4



(Vin = 0)
Adc

Quiescent Current IDD 5.0 0.25 0.0005 0.25 7.5
(Per Package) 10 0.5 0.0010 0.5 15

15 1.0 0.0015 1.0 30

Total Supply Current (5.) (6.) IT 5.0 IT = (0.7 A/kHz) f + IDD/6 Adc
IT = (1.4 A/kHz) f + IDD/6

(Dynamic plus Quiescent, 10
Per Gate) (CL = 50 pF) 15 IT = (2.2 A/kHz) f + IDD/6
where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.003.
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47
MC14007UB

VDD


tTLH = (1.2 ns/pF) CL + 30 ns 5.0 90 180


10
15

45
35
90
70


tTHL = (1.2 ns/pF) CL + 15 ns 5.0 75 150
tTHL = (0.5 ns/pF) CL + 15 ns 10 40 80

tTHL = (0.4 ns/pF) CL + 10 ns 15 30 60

TurnOff Delay Time

tPLH = (1.5 ns/pF) CL + 35 ns
tPLH
5.0

60 125
ns

tPLH = (0.2 ns/pF) CL + 20 ns 10 30 75
tPLH = (0.15 ns/pF) CL + 17.5 ns 15 25 55

TurnOn Delay Time

tPHL = (1.0 ns/pF) CL + 10 ns
tPHL
5.0 60 125
ns

tPHL = (0.3 ns/pF) CL + 15 ns 10 30 75
tPHL = (0.2 ns/pF) CL + 15 ns 15 25 55
7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
VDD = VGS VDD = VGS
14
IOH VDS = VOH VDD 14
IOL VDS = VOL
7 VSS
7 VSS
All unused inputs connected to ground. All unused inputs connected to ground.
0 20
a VGS = 15 Vdc
b
c
c
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)
4.0 16
VGS = 5.0 Vdc b a
10 Vdc
8.0 a TA = 55C a 12
b TA = + 25C b c
c TA = + 125C a TA = 55C
c b
12 8.0 b TA = + 25C
b c TA = + 125C
c
10 Vdc a 15 Vdc a
16 4.0
a b 5.0 Vdc
c
20 0
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10
Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
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48
MC14007UB
VDD
20 ns 20 ns
0.01 F VDD
90%
500 F ID CERAMIC Vin 50%
10% VSS
14 tPHL tPLH
PULSE Vin VOH
Vout 90%
GENERATOR Vout 50%
7 VSS CL 10%
VOL
tTHL tTLH
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
The MC14007UB dual pair plus inverter, which has VDD

14 OUT = A+BC
access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.
13
+ VDD 11 2
2
DISABLE 3
10 12 1
B OUTPUT
1 8
11
9 7
5
INPUT 10 12 OUTPUT
3
C
9 4
8
6
A
DISABLE 6
7
Substrates of Pchannel devices internally connected to VDD;
Substrates of Nchannel devices internally connected to VSS.
INPUT DISABLE OUTPUT
1 0 0 Figure 6. AOI Functions Using Tree Logic
0 0 1
X 1 OPEN
X = Dont Care
Figure 5. 3State Buffer
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49
MC14008B
4-Bit Full Adder

The MC14008B 4bit full adder is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This device consists of four full adders with fast
internal lookahead carry output. It is useful in binary addition and
other arithmetic applications. The fast parallel carry output bit allows
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highspeed operation when used with other adders in a system.
LookAhead Carry Output
Diode Protection on All Inputs MARKING
DIAGRAMS
All Outputs Buffered
16
Capable of Driving Two Lowpower TTL Loads or One Lowpower P SUFFIX MC14008BCP
AWLYYWW
Schottky TTL Load Over the Rated Temperature Range CASE 648
PinforPin Replacement for CD4008B 1
16
SOIC16
14008B
D SUFFIX AWLYWW
CASE 751B
Symbol Parameter Value Unit 1
VDD DC Supply Voltage Range 0.5 to +18.0 V
F SUFFIX MC14008B
(DC or Transient) per Pin CASE 966

TA Ambient Temperature Range 55 to +125 C A = Assembly Location
WL or L = Wafer Lot
WW or W = Work Week
(8Second Soldering)
This device contains protection circuitry to guard against damage due to high MC14008BCP PDIP16 2000/Box
applications of any voltage higher than maximum rated voltages to this MC14008BDR2 SOIC16 2500/Tape & Reel
to the range VSS v (Vin or Vout) vVDD. MC14008BF SOEIAJ16 See Note 1.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., 1. For ordering information on the EIAJ version of
either VSS or VDD). Unused outputs must be left open. the SOIC packages, please contact your local

MC14008B
TRUTH TABLE
(One Stage)
Cin B A Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
PIN ASSIGNMENT
A4 1 16 VDD
B3 2 15 B4
A3 3 14 Cout
B2 4 13 S4
A2 5 12 S3
B1 6 11 S2
A1 7 10 S1
VSS 8 9 Cin
BLOCK DIAGRAM
HIGHSPEED
14 Cout
PARALLEL CARRY
B4 15 ADDER
13 S4
A4 1 4
C4
B3 2 ADDER
12 S3
A3 3 3
C3
B2 4 ADDER
11 S2
A2 5 2
C2
B1 6 ADDER
10 S1
A1 7 1
VDD = PIN 16
Cin 9 VSS = PIN 8
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51
MC14008B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 0.5 or 4.5 Vdc) 1 Level VIH 5.0 3.5 3.5 2.75 3.5 Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

Quiescent Current IDD 5.0 5.0 0.005 5.0 150
(Per Package) 10 10 0.010 10 300

15 20 0.015 20 600

Total Supply Current (5.) (6.) IT 5.0 IT = (1.7 A/kHz) f + IDD Adc
IT = (3.4 A/kHz) f + IDD

Per Package) 15 IT = (5.0 A/kHz) f + IDD

(CL = 50 pF on all outputs, all
buffers switching)
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52
MC14008B

VDD


Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

10
15

50
40
100
80


Sum in to Sum Out


Sum In to Carry Out

tPLH, tPHL = (1.7 ns/pF) CL + 220 ns

5.0
10

305
145
610
290

Carry In to Sum Out



Carry In to Carry Out

tPLH, tPHL = (1.7 ns/pF) CL + 85 ns 5.0

170 340

15 55 110
VDD = VGS Vout VDD = VGS Vout
16 16
B4 S4 B4 S4
A4 A4
B3 S3 B3 S3
A3 A3
B2 S2 B2 S2
A2 A2
B1 S1 IOH B1 S1 IOL
A1 A1
Cin Cout Cin Cout
EXTERNAL EXTERNAL
8 VSS POWER 8 VSS POWER
SUPPLY SUPPLY
Figure 1. Typical Source Current Figure 2. Typical Sink Current

Characteristics Test Circuit Characteristics Test Circuit
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53
MC14008B
VDD
16
B4 S4
A4
B3 S3
20 ns 20 ns A3
B2 S2
VDD A2
90% CL
Vin B1 S1
10% VSS CL
A1
PULSE CL
Cin Cout
GENERATOR CL
CL
8 VSS
500 F IDD
Figure 3. Dynamic Power Dissipation Test Circuit and Waveform
VDD
16
B4 S4
A4
B3 S3
A3
B2 S2
A2
B1 S1 CL
A1 CL
PULSE CL
Cin Cout
GENERATOR CL
8 VSS CL
IDD
20 ns 20 ns
VDD
90%
Cin 50%
10% VSS
tPHL tPLH
90% VOH
S1 S4 50%
10% VOL
tTHL tTLH
VOH
Cout 50%
VOL
tPLH tPHL
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54
MC14008B
Cout
B4
S4
A4
B3
S3
A3
B2
S2
A2
B1
S1
A1
Cin
Figure 5. Logic Diagram
TYPICAL APPLICATION
WORD A + B INPUTS
A1 B4 A1 B4 A1 B4 A1 B4
CHIP CHIP CHIP CHIP

Cin Cout Cin Cout Cin Cout Cin Cout
1 2 3 4
S1 S4 S1 S4 S1 S4 S1 S4
SUM OUTPUTS
Calculation of 16bit adder speed:
tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16bit adder speed at 10 V, 25C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns
Figure 6. Using the MC14008B in a 16Bit Adder Configuration
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55
MC14013B
Dual Type D Flip-Flop

The MC14013B dual type D flipflop is constructed with MOS
monolithic structure. Each flipflop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
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elements or as type T flipflops for counter and toggle applications.
Static Operation MARKING
Diode Protection on All Inputs DIAGRAMS
Supply Voltage Range = 3.0 Vdc to 18 Vdc 14
Logic EdgeClocked FlipFlop Design

PDIP14
P SUFFIX MC14013BCP
Logic state is retained indefinitely with clock level either high or low; CASE 646 AWLYYWW
information is transferred to the output only on the positivegoing 1
edge of the clock pulse
14
Capable of Driving Two Lowpower TTL Loads or One Lowpower SOIC14
14013B
Schottky TTL Load Over the Rated Temperature Range D SUFFIX AWLYWW
PinforPin Replacement for CD4013B CASE 751A
1
14
TSSOP14 14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) DT SUFFIX 013B
Symbol Parameter Value Unit CASE 948G ALYW

F SUFFIX MC14013B
CASE 965
1
per Package (Note 3.) A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
Tstg Storage Temperature Range 65 to +150 C WW or W = Work Week
(8Second Soldering)
may occur. Device Package Shipping
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14013BCP PDIP14 2000/Box
This device contains protection circuitry to guard against damage due to high MC14013BD SOIC14 55/Rail
MC14013BDT TSSOP14 96/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14013BDTR2 TSSOP14 2500/Tape & Reel
MC14013BF SOEIAJ14 See Note 1.
MC14013BFEL SOEIAJ14 See Note 1.


MC14013B
TRUTH TABLE
Inputs Outputs
Clock Data Reset Set Q Q
0 0 0 0 1
1 0 0 1 0
X 0 0 Q Q No
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Dont Care
= Level Change
PIN ASSIGNMENT
QA 1 14 VDD
QA 2 13 QB
CA 3 12 QB
RA 4 11 CB
DA 5 10 RB
SA 6 9 DB
VSS 7 8 SB
BLOCK DIAGRAM
S
5 D Q 1
3 C Q 2
R
S
9 D Q 13
11 C Q 12
R
10
VDD = PIN 14
VSS = PIN 7
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57
MC14013B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

(Per Package) 10 2.0 0.004 2.0 60

15 4.0 0.006 4.0 120



buffers switching)
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58
MC14013B

Characteristic Symbol VDD Min Typ (8.) Max Unit



10
15

50
40
100
80

Propagation Delay Time tPLH ns
Clock to Q, Q tPHL


15 50 100

Set to Q, Q


5.0
10
15

175
75
50
350
150
100

Reset to Q, Q



Setup Times (9.)

tsu 5.0
10
40
20
20
10

ns

15 15 7.5
Hold Times (9.)

th 5.0 40 20 ns
10 20 10

15 15 7.5

Clock Pulse Width tWL, tWH 5.0 250 125 ns

10 100 50
15 70 35

Clock Pulse Frequency

fcl 5.0
10
15

4.0
10
14
2.0
5.0
7.0
MHz

Clock Pulse Rise and Fall Time

tTLH
tTHL
5.0
10

15
5.0
s

15 4.0

Set and Reset Pulse Width tWL, tWH 5.0 250 125 ns
10 100 50

15 70 35

Removal Times trem ns

Set 5 80 0
10 45 5

15 35 5

Reset 5 50 35

10 30 10
15 25 5
9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)

S
C C Q
C C Q
C C
C C
C C
C
R
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59
MC14013B
20 ns 20 ns
VDD
90%
D 50%
10% 20 ns 20 ns
tsu (L) VSS
tsu (H) 90% VDD
th 20 ns SET OR
VDD 50%
90% RESET 10%
C 50% VSS
10% tw trem
VSS 20 ns 20 ns
tWH tWL 90% VDD
CLOCK 50%
1 10%
VSS
fcl
tPLH tPHL tPLH tw
VOH tPHL
90%
Q 50% VOH
10% VOL Q OR Q 50%
VOL
tTLH tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(Data, Clock, and Output) (Set, Reset, Clock, and Output)
TYPICAL APPLICATIONS
nSTAGE SHIFT REGISTER

1 2 nth
D D Q D Q D Q Q
C Q C Q C Q
CLOCK
BINARY RIPPLE UPCOUNTER (Divideby2n)

1 2 nth
D Q D Q D Q Q
CLOCK C Q C Q C Q
T FLIPFLOP
MODIFIED RING COUNTER (Divideby(n+1))

1 2 nth
D Q D Q D Q Q
C Q C Q C Q
CLOCK
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60
MC14014B, MC14021B
8-Bit Static Shift Register

The MC14014B and MC14021B 8bit static shift registers are
constructed with MOS Pchannel and Nchannel enhancement mode
devices in a single monolithic structure. These shift registers find
primary use in paralleltoserial data conversion, synchronous and
asynchronous parallel input, serial output data queueing; and other
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general purpose register applications requiring low power and/or high
noise immunity.
MARKING
Synchronous Parallel Input/Serial Output (MC14014B) DIAGRAMS
Asynchronous Parallel Input/Serial Output (MC14021B) 16
Synchronous Serial Input/Serial Output

PDIP16
P SUFFIX MC140XXBCP
Full Static Operation CASE 648 AWLYYWW
Q Outputs from Sixth, Seventh, and Eighth Stages 1

Double Diode Input Protection 16
Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC16
140XXB
Capable of Driving Two Lowpower TTL Loads or One Lowpower D SUFFIX AWLYWW
CASE 751B
1
MC14014B PinforPin Replacement for CD4014B
MC14021B PinforPin Replacement for CD4021B 16
SOEIAJ16
F SUFFIX MC140XXB
CASE 966 AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) 1

Symbol Parameter Value Unit XX = Specific Device Code
VDD DC Supply Voltage Range 0.5 to +18.0 V A = Assembly Location
WL or L = Wafer Lot
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V YY or Y = Year
(DC or Transient) WW or W = Work Week
Iin, Iout Input or Output Current 10 mA
per Package (Note 3.) Device Package Shipping
TA Ambient Temperature Range 55 to +125 C MC14014BCP PDIP16 2000/Box
Tstg Storage Temperature Range 65 to +150 C
MC14014BD SOIC16 48/Rail
(8Second Soldering) MC14014BDR2 SOIC16 2500/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device MC14014BF SOEIAJ16 See Note 1.
may occur.
3. Temperature Derating: MC14014BFEL SOEIAJ16 See Note 1.
MC14021BCP PDIP16 2000/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14021BD SOIC16 48/Rail
MC14021BDR2 SOIC16 2500/Tape & Reel
either VSS or VDD). Unused outputs must be left open. MC14021BFEL SOEIAJ16 See Note 1.


MC14014B, MC14021B
TRUTH TABLE
SERIAL OPERATION:
Q6 Q7 Q8
t Clock DS P/S t=n+6 t=n+7 t=n+8
n 0 0 0 ? ?
n+1 1 0 1 0 ?
n+2 0 0 0 1 0
n+3 1 0 1 0 1
X 0 Q6 Q7 Q8
PARALLEL OPERATION:
Clock
MC14014B MC14021B DS P/S Pn *Qn
X X 1 0 0
X X 1 1 1
*Q6, Q7, & Q8 are available externally
X = Dont Care
PIN ASSIGNMENT
P8 1 16 VDD
Q6 2 15 P7
Q8 3 14 P6
P4 4 13 P5
P3 5 12 Q7
P2 6 11 DS
P1 7 10 C
VSS 8 9 P/S
LOGIC DIAGRAM
P1 P2 P3 P6 P7 P8
9 7 6 5 14 15 1
P/S
11
DS D Q D Q D Q D Q D Q D
C C C C Q C Q C Q
10
CLOCK
VDD = PIN 16 P4 = PIN 4

VSS = PIN 8 P5 = PIN 13 2 12 3
Q6 Q7 Q8
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62
MC14014B, MC14021B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

(Per Package) 10 10 0.010 10 300

15 15 0.015 15 600



buffers switching)
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63
MC14014B, MC14021B

VDD




10
15

50
40
100
80

Propagation Delay Time (Clock to Q, P/S to Q) tPLH, ns

tPHL, tPLH = (1.7 ns/pF) CL + 315 ns tPHL 5.0 400 800
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns 10 170 340


Clock Pulse Width tWH 5.0 400 150 ns

10 175 75
15 135 40

Clock Frequency

fcl 5.0
10

3.0
6.0
1.5
3.0
MHz

15 8.0 4.0

Parallel/Serial Control Pulse Width tWH 5.0 400 150 ns

10 175 75
15 135 40
Setup Time

P/S to Clock

tsu 5.0
10
200
100
100
50

ns

15 80 40

Hold Time th 5.0 20 2.5 ns

Clock to P/S 10 20 10
15 25 0
Setup Time

Data (Parallel or Serial) to
tsu 5.0
10
350
80
150
50

ns

Clock or P/S 15 60 30

Hold Time th 5.0 45 0 ns

Clock to Ds 10 35 0
15 35 5
Hold Time

Clock to Pn

th 5.0
10
50
45
25
20

ns

15 45 20

Input Clock Rise Time tr(cl) 5.0 15 s

10 5
15 4
VDD Vout VDD Vout
P/S Q6 P/S Q6
PULSE PULSE
C C
GENERATOR GENERATOR
P6 Q7 P6 Q7
P7 P7
P8 IOH P8 IOL
DS Q8 DS Q8
EXTERNAL EXTERNAL
POWER POWER
SUPPLY SUPPLY
Preset output under test to a logic 1 level.
Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit
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64
MC14014B, MC14021B
VDD
500 F ID
0.01 F
CERAMIC
P/S
PULSE
C Q6
GENERATOR 1
P1
P2 CL
P3
P4 Q7
P5
P6 CL
P7
PULSE P8 Q8
DS
GENERATOR 2
CL
VSS
1
f
CLOCK 50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveform
SW 1
VDD
PULSE 1 VDD
GENERATOR 1 20 ns 20 ns
PARALLEL OR VDD
2 90%
P/S SERIAL DATA
50%
C Q6 INPUT 10% VSS
P1 tsu
2 2 P2
PULSE tWH tTHL
P3
GENERATOR 2 VDD
1 1 P4 Q7 CLOCK OR P/S 90%
P5 INPUT 50%
10% VSS
P6 CL tWH tWL
P7 tPLH tPHL
P8 Q8 VOH
DS Q 90%
OUTPUT 50%
SWITCH POSITION 1 = PARALLEL IN 10% VOL
SWITCH POSITION 2 = SERIAL IN VSS
SW 2
tTLH tTHL
tWL = tWH = 50% DUTY CYCLE
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65
MC14015B
Dual 4-Bit Static

Shift Register
The MC14015B dual 4bit static shift register is constructed with
MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4state serialinput/paralleloutput registers. Each register has http://onsemi.com
independent Clock and Reset inputs with a single serial Data input.
The register states are type D masterslave flipflops. Data is shifted MARKING
from one stage to the next during the positivegoing clock transition. DIAGRAMS
Each register can be cleared when a high level is applied on the Reset 16
line. These complementary MOS shift registers find primary use in PDIP16
P SUFFIX MC14015BCP
buffer storage and serialtoparallel conversion where low power AWLYYWW
CASE 648
dissipation and/or noise immunity is desired.
1
Diode Protection on All Inputs
Logic EdgeClocked FlipFlop Design

SOIC16
14015B
D SUFFIX AWLYWW
Logic state is retained indefinitely with clock level either high or low; CASE 751B
information is transferred to the output only on the positive going 1
edge of the clock pulse.
16
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range. TSSOP16 14
DT SUFFIX 015B
CASE 948F ALYW
1
Symbol Parameter Value Unit SOEIAJ16
F SUFFIX MC14015B
VDD DC Supply Voltage Range 0.5 to +18.0 V AWLYWW
CASE 966
(DC or Transient) 1
Iin, Iout Input or Output Current 10 mA A = Assembly Location

(DC or Transient) per Pin WL or L = Wafer Lot
YY or Y = Year
PD Power Dissipation, 500 mW WW or W = Work Week
TL Lead Temperature 260 C Device Package Shipping
(8Second Soldering)
may occur. MC14015BD SOIC16 48/Rail
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14015BDR2 SOIC16 2500/Tape & Reel
This device contains protection circuitry to guard against damage due to high MC14015BDT TSSOP16 2000/Tape & Reel

MC14015B
TRUTH TABLE
C D R Q0 Qn
0 0 0 Qn1
1 0 1 Qn1
X 0 No Change No Change
X X 1 0 0
X = Dont Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn1 = Output of prior stage.
PIN ASSIGNMENT
CB 1 16 VDD
Q3B 2 15 DB
Q2A 3 14 RB
Q1A 4 13 Q0B
Q0A 5 12 Q1B
RA 6 11 Q2B
DA 7 10 Q3A
VSS 8 9 CA
BLOCK DIAGRAM
Q0 5
7 D
Q1 4
Q2 3
9 C
R Q3 10
Q0 13
15 D
Q1 12
Q2 11
1 C
R Q3 2
14
VDD = PIN 16
VSS = PIN 8
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67
MC14015B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or .05 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4


(Vin = 0)

Quiescent Current
(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

Total Supply Current (5.) (6.) IT 5.0 IT = (1.2 A/kHz)f + IDD Adc
(Dynamic plus Quiescent, 10 IT = (2.4 A/kHz)f + IDD

Per Package)

buffers switching)
15 IT = (3.6 A/kHz)f + IDD
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68
MC14015B



tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100


Propagation Delay Time tPLH, ns

Clock, Data to Q tPHL


Reset to Q


Clock Pulse Width


tWH
15
5.0

400
120
185
170
ns

10 175 85
15 135 55


fcl 5.0
10

2.0
6.0
1.5
3.0
MHz

15 7.5 3.75

Clock Pulse Rise and Fall Times tTLH, tTHL 5.0 15 s
10 5

Reset Pulse Width

tWH
15
5.0

400

200
4
ns

10 160 80
15 120 60
Setup Time

tsu 5.0
10
350
100
100
50

ns

15 75 40
7. The formulas given are for typical characteristics only at 25_C.
VDD
0.01 F
PULSE 500 F ID CERAMIC
GENERATOR VDD
2
D Q0
Q1 CL
PULSE Q2 CL
GENERATOR C Q3
CL
1 R CL
VSS
1
f
CLOCK 50%
DATA
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69
MC14015B
tTLH tTHL
DATA VDD
90%
INPUT 50%
10% 0V
tsu
VDD tTLH t tTHL
PULSE
GENERATOR D 90% VDD
Q0 CLOCK
2 CL 50%
Q1 INPUT 10%
SYNC CL 0V
PULSE Q2 tWH tWL
C Q3 CL tPLH tPHL
GENERATOR
1 R CL
90%
VSS 50%
Q0 10%
tWL = tWH = 50% Duty Cycle

tTLH = tTHL 20 ns tTLH tTHL
Figure 2. Switching Test Circuit and Waveforms
VDD
PULSE
CLOCK VDD
GENERATOR D Q0 50%
2 CL INPUT 0V
Q1 tsu
SYNC CL
PULSE Q2
C Q3 CL th
GENERATOR
1 R CL DATA VDD
50%
VSS INPUT 0V
Figure 3. Setup and Hold Time Test Circuit and Waveforms
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70
SINGLE BIT
VDD Q
RESET
CLOCK
DATA TO D OF
IN NEXT BIT
VSS
71
MC14015B
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CIRCUIT SCHEMATICS
DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER

VDD VDD
VDD
RESET CLOCK CLOCK

DATA DATA TO RESET
TO 4 BITS IN TO 4 BITS
IN FIRST BIT IN
VSS VSS
VSS
MC14015B
LOGIC DIAGRAMS
SINGLE BIT
C C Q
TO D OF
DATA NEXT BIT
C C C C
C C
RESET
C
C
C
COMPLETE DEVICE
5 4 3 10
Q0 Q1 Q2 Q3
DATA INPUT BUFFER

D
7 D Q D Q D Q D Q
C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
9
R
6
13 12 11 2
RESET INPUT BUFFER Q0 Q1 Q2 Q3
DATA INPUT BUFFER

D
15 D Q D Q D Q D Q
C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
1
VDD = PIN 16
R VSS = PIN 8
14
RESET INPUT BUFFER
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72
MC14016B
Quad Analog Switch/

Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS

monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The http://onsemi.com
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation. MARKING
PDIP14
Linearized Transfer Characteristics P SUFFIX MC14016BCP
Low Noise 12 nV/Cycle, f 1.0 kHz typical CASE 646 AWLYYWW
PinforPin Replacements for CD4016B, CD4066B (Note improved 1

transfer characteristic design causes more parasitic coupling 14
capacitance than CD4016) SOIC14
For Lower RON, Use The HC4016 HighSpeed CMOS Device or D SUFFIX
14016B
AWLYWW
The MC14066B CASE 751A
This Device Has Inputs and Outputs Which Do Not Have ESD 1
Protection. Antistatic Precautions Must Be Taken. 14

SOEIAJ14
F SUFFIX MC14016B
CASE 965 AWLYWW
1
VDD DC Supply Voltage Range 0.5 to +18.0 V WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(DC or Transient)
Iin Input Current (DC or Transient) 10 mA
per Control Pin
ISW Switch Through Current 25 mA
Device Package Shipping
per Package (Note 3.) MC14016BCP PDIP14 2000/Box
TA Ambient Temperature Range 55 to +125 C MC14016BD SOIC14 55/Rail
(8Second Soldering) MC14016BF SOEIAJ14 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device MC14016BFEL SOEIAJ14 See Note 1.
may occur.
3. Temperature Derating: 1. For ordering information on the EIAJ version of
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C the SOIC packages, please contact your local

MC14016B
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3
BLOCK DIAGRAM
13
CONTROL 1 2
1 OUT 1
IN 1
5
CONTROL 2 3
4 OUT 2
IN 2
6
CONTROL 3 9
OUT 3
8
IN 3
12
CONTROL 4 10
OUT 4
11
IN 4
VDD = PIN 14
VSS = PIN 7
Control Switch
0 = VSS Off
1 = VDD On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS IN

VSS Vin VDD
VSS Vout VDD
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74
MC14016B

VDD
55_C 25_C 125_C

Characteristic Figure Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit

Input Voltage 1 VIL 5.0 1.5 0.9 Vdc

Control Input 10 1.5 0.9
15 1.5 0.9

VIH 5.0 3.0 2.0 Vdc

10 8.0 6.0

15 13 11
0.1 0.00001 0.1 1.0 Adc

Input Current Control Iin 15

Input Capacitance Cin pF
Control 5.0

Switch Input 5.0

Switch Output 5.0
Feed Through 0.2

Quiescent Current

(Per Package) (5.)

2,3 IDD 5.0
10

0.25
0.5

0.0005
0.0010
0.25
0.5

7.5
15
Adc

15 1.0 0.0015 1.0 30

ON Resistance 4,5,6 RON Ohms
(VC = VDD, RL = 10 k)

(Vin = + 5.0 Vdc) 600 300 660 840

(Vin = 5.0 Vdc) VSS = 5.0 Vdc 600 300 660 840
(Vin = 0.25 Vdc) 5.0 600 280 660 840

(Vin = + 7.5 Vdc)

(Vin = 0.25 Vdc)

(Vin = 7.5 Vdc) VSS = 7.5 Vdc
7.5

360
360
360

240
240
180
400
400
400

520
520
520

(Vin = + 10 Vdc)

600 260 660 840

(Vin = + 0.25 Vdc) VSS = 0 Vdc 600 310 660 840

(Vin = + 5.6 Vdc) 10 600 310 660 840
(Vin = + 15 Vdc) 360 260 400 520

(Vin = + 0.25 Vdc) VSS = 0 Vdc

360 260 400 520

(Vin = + 9.3 Vdc) 15 360 300 400 520

ON Resistance RON Ohms
Between any 2 circuits in a common

package

(VC = VDD)
(Vin = 5.0 Vdc, VSS = 5.0 Vdc) 5.0 15

(Vin = 7.5 Vdc, VSS = 7.5 Vdc) 7.5 10

Input/Output Leakage Current

Adc

(VC = VSS)
(Vin = + 7.5, Vout = 7.5 Vdc) 7.5 0.1 0.0015 0.1 1.0

(Vin = 7.5, Vout = + 7.5 Vdc) 7.5 0.1 0.0015 0.1 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
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75
MC14016B
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)

VDD

Characteristic Figure Symbol Vdc Min Typ (7.) Max Unit

Propagation Delay Time (VSS = 0 Vdc) 7 tPLH, 5.0 15 45 ns
Vin to Vout tPHL 10 7.0 15

(VC = VDD, RL = 10 k) 15 6.0 12

Control to Output 8 tPHZ, ns
v

(Vin 10 Vdc, RL = 10 k) tPLZ, 5.0 34 90
tPZH, 10 20 45

tPZL 15 15 35

Crosstalk, Control to Output (VSS = 0 Vdc) 9 5.0 30 mV
(VC = VDD, Rin = 10 k, Rout = 10 k, 10 50

f = 1.0 kHz)

Crosstalk between any two switches (VSS = 0 Vdc)
15
5.0

100
80

dB

(RL = 1.0 k, f = 1.0 MHz,
+ V

crosstalk 20 log10 out1)
Vout2

Noise Voltage (VSS = 0 Vdc)

(VC = VDD, f = 100 Hz)

10,11 5.0
10
15

24
25
30

nV/Cycle

(VC = VDD, f = 100 kHz)

5.0
10

12
12

15 15

Second Harmonic Distortion (VSS = 5.0 Vdc) 5.0 0.16 %
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,

RL = 10 k, f = 1.0 kHz)

Insertion Loss (VC = VDD, Vin = 1.77 Vdc, 12 5.0 dB
VSS = 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
+Iloss

(RL = 1.0 k)

V

20 log10 out)

Vin

2.3
0.2

(RL = 10 k)

(RL = 100 k)
(RL = 1.0 M)

0.1
0.05

Bandwidth ( 3.0 dB)

(VC = VDD, Vin = 1.77 Vdc, VSS = 5.0 Vdc,
12,13 BW 5.0 MHz

RMS centered @ 0.0 Vdc)
(RL = 1.0 k) 54

(RL = 10 k) 40

(RL = 100 k) 38
(RL = 1.0 M) 37

(VSS = 5.0 Vdc)
+

Vout

OFF Channel Feedthrough Attenuation

5.0 kHz

(VC = VSS, 20 log10 50 dB)
Vin 1250
(RL = 1.0 k)

140
(RL = 10 k)
18

(RL = 100 k)
2.0
(RL = 1.0 M)
6. The formulas given are for typical characteristics only at 25_C.
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76
MC14016B
VC IS
Vin Vout
VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000
VDD = 15 Vdc 10 Vdc
PD , POWER DISSIPATION (W)

VDD TA = 25C
5.0 Vdc
1000
ID
100
VDD Vout
TO ALL
10 k 10
PULSE 4 CIRCUITS CONTROL
GENERATOR INPUT
fc
VSS Vin 1.0

PD = VDD x ID 5.0 k 10 k 100 k 1.0 M 10 M 50 M
fc, FREQUENCY (Hz)
Figure 2. Quiescent Power Dissipation Figure 3. Typical Power Dissipation per Circuit
Test Circuit (1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE
700 700
RL = 10 k VSS = 0 Vdc
600 TA = 25C 600 RL = 10 k
R ON, ON RESISTANCE (OHMS)
R ON, ON RESISTANCE (OHMS)
TA = 25C
500 500
400 VC = VDD = 5.0 Vdc 400

VSS = 5.0 Vdc VC = VDD = 10 Vdc
300 300
200 200 VC = VDD = 15 Vdc

VC = VDD = 7.5 Vdc
100 VSS = 7.5 Vdc 100
0 0
10 8.0 4.0 0 4.0 8.0 10 0 2.0 6.0 10 14 18 20
Figure 4. VSS = 5.0 V and 7.5 V Figure 5. VSS = 0 V
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77
MC14016B
Vout
RL CL
Vin
Vout 20 ns 20 ns
RL VDD
Vin 90%
VC 50% 10%
VSS
tPLH tPHL
Vout 50%
Vin
Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit

Test Circuit and Waveforms
Vout
VC RL CL
Vin VX
20 ns
VDD Vout
90%
VC 50%
10% VC 10 k 15 pF
VSS
tPZH tPHZ
Vin = VDD
90% Vx = VSS
Vout 10% Vin
tPZL tPLZ
90% 1k
Vout Vin = VSS
10%
Vx = VDD
Figure 8. TurnOn Delay Time Test Circuit Figure 9. Crosstalk Test Circuit
and Waveforms
35
30
VDD = 15 Vdc
NOISE VOLTAGE (nV/ CYCLE)
25
10 Vdc
20
5.0 Vdc
15
OUT QUANTECH 10
MODEL
VC = VDD
2283
5.0
IN OR EQUIV
0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)
Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics
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78
MC14016B
2.0
RL = 1 M AND 100 k
0
TYPICAL INSERTION LOSS (dB)
10 k
2.0
1.0 k
4.0 3.0 dB (RL = 1.0 M )
Vout
6.0 3.0 dB (RL = 10 k ) RL
VC
3.0 dB (RL = 1.0 k )
8.0
10 + 2.5 Vdc
Vin 0.0 Vdc
12 2.5 Vdc
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)
Figure 12. Typical Insertion Loss/Bandwidth Figure 13. Frequency Response Test Circuit
Characteristics
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. V Across Switch
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79
MC14016B
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0to5 The example shows a 5 Vpp signal which allows no
V Digital Control signal is used to directly control a 5 Vpp margin at either peak. If voltage transients above VDD
analog signal. and/or below VSS are anticipated on the analog channels,
The digital control logic levels are determined by VDD external diodes (Dx) are recommended as shown in Figure
and VSS. The VDD voltage is the logic high voltage; the VSS B. These diodes should be small signal types able to absorb
voltage is logic low. For the example, VDD = + 5 V logic high the maximum anticipated current surges during clipping.
at the control inputs; VSS = GND = 0 V logic low. The absolute maximum potential difference between
The maximum analog signal level is determined by VDD VDD and VSS is 18.0 V. Most parameters are specified up to
and VSS. The analog voltage must not swing higher than 15 V which is the recommended maximum difference
VDD or lower than VSS. between VDD and V SS.
+5 V
VDD VSS
+ 5.0 V
+5 V 5 Vpp SWITCH
ANALOG SIGNAL IN
SWITCH 5 Vpp
+ 2.5 V
OUT ANALOG SIGNAL
EXTERNAL
CMOS 0TO5 V DIGITAL
GND
DIGITAL CONTROL SIGNALS MC14016B
CIRCUITRY
Figure A. Application Example
VDD VDD
Dx Dx
SWITCH SWITCH
IN OUT
Dx Dx
VSS VSS
Figure B. External Germanium or Schottky Clipping Diodes
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80
MC14017B
Decade Counter
The MC14017B is a fivestage Johnson decade counter with
builtin code converter. High speed operation and spikefree outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
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positivegoing edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications. MARKING
DIAGRAMS
Fully Static Operation
16
DC Clock Input Circuit Allows Slow Rise Times PDIP16
Carry Out Output for Cascading P SUFFIX MC14017BCP
AWLYYWW
DividebyN Counting
CASE 648
1
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Schottky TTL Load Over the Rated Temperature Range SOIC16
14017B
PinforPin Replacement for CD4017B D SUFFIX AWLYWW
Triple Diode Protection on All Inputs
CASE 751B
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOEIAJ16
F SUFFIX MC14017B
Symbol Parameter Value Unit CASE 966 AWLYWW
1
(DC or Transient)
WL or L = Wafer Lot
Iin, Iout Input or Output Current 10 mA YY or Y = Year
(DC or Transient) per Pin WW or W = Work Week

Tstg Storage Temperature Range 65 to +150 C Device Package Shipping
TL Lead Temperature 260 C MC14017BCP PDIP16 2000/Box

(8Second Soldering)
may occur. MC14017BDR2 SOIC16 2500/Tape & Reel
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14017BF SOEIAJ16 See Note 1.
This device contains protection circuitry to guard against damage due to high MC14017BFEL SOEIAJ16 See Note 1.
applications of any voltage higher than maximum rated voltages to this 1. For ordering information on the EIAJ version of the
highimpedance circuit. For proper operation, Vin and Vout should be constrained SOIC packages, please contact your local ON
Semiconductor representative.

MC14017B
PIN ASSIGNMENT
Q5 1 16 VDD
Q1 2 15 RESET
Q0 3 14 CLOCK
Q2 4 13 CE
Q6 5 12 Cout
Q7 6 11 Q9
Q3 7 10 Q4
VSS 8 9 Q8
FUNCTIONAL TRUTH TABLE BLOCK DIAGRAM

(Positive Logic)
CLOCK 14 Q0 3
Clock Decode Q1 2
Clock Enable Reset Output=n Q2 4
0 X 0 n Q3 7
X 1 0 n Q4 10
CLOCK
X X 1 Q0 13 Q5 1
ENABLE
0 0 n+1 Q6 5
X 0 n Q7 6
X 0 n Q8 9
1 0 n+1 Q9 11
X = Dont Care. If n < 5 Carry = 1, RESET 15 Cout 12
Otherwise = 0.
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAM
Q5 Q1 Q7 Q3 Q9
1 2 6 7 11
14
CLOCK
CLOCK 12
ENABLE C Q C Q C Q C Q C Q CARRY
13
C C C C C
D Q D Q D Q D Q D Q
R R R R R R R R R R
15
RESET
3 5 4 9 10
Q0 Q6 Q2 Q3 Q4
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82
MC14017B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc

Input Current Iin 15

(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600
Total Supply Current (5.) (6.) IT = (0.27 A/kHz) f + IDD Adc

IT 5.0
(Dynamic plus Quiescent, 10 IT = (0.55 A/kHz) f + IDD


buffers switching)
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83
MC14017B

VDD





Reset to Decode Output tPHL


tPLH, tPHL = (0.66 ns/PF) CL + 197 ns 10 230 460

Clock to Cout

tPLH,
tPHL
ns




Clock to Decode Output tPHL


TurnOff Delay Time
Reset to Cout

tPLH ns

tPLH = (1.7 ns/pF) CL + 315 ns 5.0 400 800
tPLH = (0.66 ns/pF) CL + 142 ns 10 175 350

Clock Pulse Width


tw(H)
15
5.0

250
125
125
250
ns

10 100 50
15 75 35

Clock Frequency

fcl 5.0
10

5.0
12
2.0
5.0
MHz

15 16 6.7

Reset Pulse Width tw(H) 5.0 500 250 ns
10 250 125

Reset Removal Time

trem
15
5.0
190
750
95
375

ns

10 275 135
15 210 105

Clock Input Rise and Fall Time

tTLH,
tTHL
5.0
10 No Limit

15

Clock Enable Setup Time tsu 5.0 350 175 ns
10 150 75

15 115 52

Clock Enable Removal Time trem 5.0 420 260 ns

10 200 100
15 140 70
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84
MC14017B
VDD
Vout Output Output

VSS CLOCK Q0
Sink Drive Source Drive
ENABLE
Q1
Clock to
Q2 Decode desired
Q3 (S1 to A)
Outputs outputs
A Q4 (S1 to B)
VDD S1 ID
RESET Q5 Clock to 5
B Q6
VSS S1 Carry thru 9 S1 to A
Q7 (S1 to B)
Q8
VGS = VDD VDD
Q9 EXTERNAL
CLOCK Cout POWER VDS = Vout Vout VDD
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
0.01 F
500 F ID
CERAMIC
Q0
Q1
CLOCK Q2
ENABLE Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Q8
GENERATOR
Q9
Cout
VSS CL CL CL CL CL CL CL CL CL CL CL
Figure 2. Typical Power Dissipation Test Circuit
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85
MC14017B
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET RESET RESET

CLOCK CLOCK CLOCK
CE MC14017B CE MC14017B CE MC14017B
Q0 Q1 Q8 Q9 Q0Q1 Q8 Q9 Q1 Q8 Q9
8 DECODED
9 DECODED 8 DECODED
OUTPUTS
OUTPUTS OUTPUTS
CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE
Figure 3. Counter Expansion
Pcp Ncp 90% VDD

CLOCK 50%
10% VSS
trem tsu 20 ns 20 ns
CLOCK VDD
ENABLE VSS
trem 20 ns 20 ns 20 ns
RESET VDD
20 ns VSS
tPHL tPLH tPLH
Q0 VOH
tTLH VOL
tPLH tPHL
90% VOH
10% 50%
Q1 VOL
tPLH tPHL tTLH tTHL
VOH
Q2 VOL
tPLH tPHL tTLH tTHL
VOH
50%
Q3 VOL
tPLH tPHL tTLH tTHL
VOH
Q4 tTHL VOL
tPLH tPHL tTLH
tPHL
VOH
Q5 VOL
tPLH tPHL tTLH tTHL
90% VOH
Q6 10% VOL
tTHL tTHL
tPLH tPHL VOH
Q7 VOL
tTHL
tPLH VOH
Q8 VOL
tTLH tTHL
tPLH tPHL
VOH
Q9 VOL
tPHL tTLH tTHL tPHL
Cout tPLH VOH
VOL
tTHL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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86
MC14018B
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. http://onsemi.com
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs MARKING
to go to a logic 1 state. DIAGRAMS
Division by any number from 2 to 10 can be accomplished by 16
connecting appropriate Q outputs to the data input, as shown in the PDIP16
Function Selection table. Antilock gating is included in the P SUFFIX MC14018BCP
CASE 648 AWLYYWW
MC14018B to assure proper counting sequence.
1
Schmitt Trigger on Clock Input 16

Capable of Driving Two Lowpower TTL Loads or One Lowpower SOIC16
14018B
Schottky TTL Load Over the Rated Temperature Range D SUFFIX AWLYWW
PinforPin Replacement for CD4018B
CASE 751B
1
16
F SUFFIX MC14018B
1
(DC or Transient)
WL or L = Wafer Lot

TA Ambient Temperature Range 55 to +125 C ORDERING INFORMATION
Tstg Storage Temperature Range 65 to +150 C Device Package Shipping

(8Second Soldering)
applications of any voltage higher than maximum rated voltages to this 1. For ordering information on the EIAJ version of
highimpedance circuit. For proper operation, Vin and Vout should be constrained the SOIC packages, please contact your local
to the range VSS v (Vin or Vout) vVDD. ON Semiconductor representative.

MC14018B
PIN ASSIGNMENT
Din 1 16 VDD
JAM 1 2 15 R
JAM 2 3 14 C
Q2 4 13 Q5
Q1 5 12 JAM 5
Q3 6 11 Q4
JAM 3 7 10 PE
VSS 8 9 JAM 4
FUNCTIONAL TRUTH TABLE

Preset Jam
Clock Reset Enable Input Qn
0 0 X Qn
0 0 X Dn *
X 0 1 0 1
X 0 1 1 0
X 1 X X 1
*Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
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88
MC14018B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

(Per Package) 10 10 0.010 10 300

15 20 0.015 20 600



buffers switching)
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89
MC14018B

VDD
All Types


Output Rise and Fall Time tTLH, tTHL ns

tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 50 100



Clock to Q tPHL



Reset to Q ns
tPLH = (0.90 ns/pF) CL + 325 ns 5.0 370 740

tPLH = (0.36 ns/pF) CL + 132 ns 10 150 300

tPLH = (0.26 ns/pF) CL + 81 ns 15 100 200

Preset Enable to Q ns

Setup Time

Data (Pin 1) to Clock

tsu
5.0 200 0
ns

10 100 0
15 80 0

Jam Inputs to Preset Enable

5.0
10
200
100
0
0

ns

15 80 0

Data (Jam Inputs)toPreset th 5.0 540 270 ns
Enable Hold Time 10 500 250

15 480 240


10 200 100
15 160 80
Pulse Width

Reset or Preset Enable

tWH 5.0
10
290
130
145
65

ns

15 110 55

Clock Rise and Fall Time tTLH, tTHL 5.0 ns
10 No Limit

15

Clock Pulse Frequency fcl 5.0 2.5 1.25 MHz

10 6.5 3.25
15 8.0 4.0
20 ns 20 ns
VDD
90%
ANY INPUT 50%
10% VSS
tPLH tPHL
VOH
90%
ANY OUTPUT 50%
10% VOL
tTLH tTHL
Figure 1. Switching Time Waveforms
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90
MC14018B
1
CLOCK
0
1
RESET
0
1
PRESET ENABLE
0
1
JAM 1
0
JAM 2 1
0
1
TIMING DIAGRAM JAM 3 DONT CARE
UNTIL PRESET ENABLE 0
(Q5 Connected to Data Input) 1
GOES HIGH
JAM 4 0
1
JAM 5 0
1
Q1
0
1
Q2
0
1
Q3
0
1
Q4 0
1
Q5
0
FUNCTION SELECTION
Connect
Counter Data Input
Mode (Pin 1) to: Comments
Divide by 10 Q5
Divide by 8 Q4
No external
Divide by 6 Q3
components needed.
Divide by 4 Q2
Divide by 2 Q1 LOGIC DIAGRAM
Divide by 9 Q5 Q4 Gate package needed
Divide by 7 Q4 Q3 to provide AND JAM 1 JAM 2 JAM 3 JAM 4 JAM 5
Divide by 5 Q3 Q2 function. Counter 2 3 7 9 12
Divide by 3 Q2 Q1 Skips all 1s state
CLOCK
CLOCK 14
SHAPER
S S S S S
DATA 1 D Q D Q D Q D Q D Q
C C C C C
Q
R P R P R P R P R P
RESET 15
PRESET ENABLE 10
VDD = PIN 16
VSS = PIN 8
5 4 6 11 13
Q1 Q2 Q3 Q4 Q5
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91
MC14020B
14-Bit Binary Counter

The MC14020B 14stage binary counter is constructed with MOS
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
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Applications include time delay circuits, counter controls, and
frequencydividing circuits. MARKING
Fully Static Operation DIAGRAMS
MC14020BCP
P SUFFIX
Capable of Driving Two Lowpower TTL Loads or One Lowpower CASE 648 AWLYYWW
Schottky TTL Load Over the Rated Temperature Range 1
Buffered Outputs Available from stages 1 and 4 thru 14
Common Reset Line 16
SOIC16
PinforPin Replacement for CD4020B D SUFFIX
14020B
AWLYWW
CASE 751B
1
16
Symbol Parameter Value Unit TSSOP16 14
DT SUFFIX 020B
VDD DC Supply Voltage Range 0.5 to +18.0 V CASE 948F ALYW
1
(DC or Transient)
16
(DC or Transient) per Pin SOEIAJ16
F SUFFIX MC14020B
PD Power Dissipation, 500 mW CASE 966 AWLYWW
1
YY or Y = Year
WW or W = Work Week
(8Second Soldering)
may occur.
3. Temperature Derating: ORDERING INFORMATION
static voltages or electric fields. However, precautions must be taken to avoid MC14020BCP PDIP16 2000/Box
to the range VSS v (Vin or Vout) vVDD. MC14020BDR2 SOIC16 2500/Tape & Reel
either VSS or VDD). Unused outputs must be left open. MC14020BDT TSSOP16 96/Rail


MC14020B
PIN ASSIGNMENT
Q12 1 16 VDD
Q13 2 15 Q11
Q14 3 14 Q10
Q6 4 13 Q8
Q5 5 12 Q9
Q7 6 11 R
Q4 7 10 C
VSS 8 9 Q1
TRUTH TABLE
Clock Reset Output State
0 No Change
0 Advance to Next State
X 1 All Outputs are Low
X = Dont Care
LOGIC DIAGRAM
Q1 Q4 Q5 Q12 Q13 Q14

9 7 5 1 2 3
CLOCK
10 C Q C Q C Q C Q C Q C Q
C Q C Q C Q C Q C Q C
R R R R R R
RESET
11
Q6 = PIN 4 Q9 = PIN 12 VDD = PIN 16

Q7 = PIN 6 Q10 = PIN 14 VSS = PIN 8
Q8 = PIN 13 Q11 = PIN 15
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93
MC14020B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600
Total Supply Current (5.) (6.) IT = (0.42 A/kHz)f + IDD Adc

IT 5.0

Per Package) 15 IT = (1.43 A/kHz)f + IDD

buffers switching)
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94
MC14020B

VDD





Clock to Q1 tPHL

tPHL, tPLH = (1.7 ns/pF) CL + 175 ns 5.0 260 520

Clock to Q14

tPHL, tPLH (1.7 ns/pF) CL + 1735 ns 5.0 1820 3900
ns


Reset to Qn

tPHL
5.0 370 740

ns

tPHL = (0.66 ns/pF) CL + 122 ns

10
15

155
115
310
230

10 165 55


fcl
15
5.0
125

38
2.0

1.0 MHz

10 6.0 3.0
15 8.0 4.0

Clock Rise and Fall Time

tTLH, tTHL 5.0
10 No Limit

15

Reset Pulse Width tWL 5.0 3000 320 ns
10 550 120

Reset Removal Time

trem
15
5.0
420
130
80
65

ns

10 50 25
15 30 15
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95
MC14020B
VDD VDD
0.01 F
500 F ID CERAMIC PULSE
C Q1
GENERATOR
Q4
Q CL
PULSE R n
C Q1 CL
GENERATOR CL
Q4 VSS
Qn CL
R
CL
CL 20 ns 20 ns
VSS
CLOCK 90%
50%
10%
20 ns 20 ns
VDD tWH
90% tPLH tPHL
CLOCK 50%
10% VSS Q 90%
50%
50% DUTY CYCLE 10%
tTLH tTHL
Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384

CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Figure 3. Timing Diagram
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96
MC14022B
Octal Counter
The MC14022B is a fourstage Johnson octal counter with builtin
code converter. Highspeed operation and spikefree outputs are
obtained by use of a Johnson octal counter design. The eight decoded
outputs are normally low, and go high only at their appropriate octal
time period. The output changes occur on the positivegoing edge of
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the clock pulse. This part can be used in frequency division
applications as well as octal counter or octal decode display
applications.
Fully Static Operation MARKING
DIAGRAMS
DC Clock Input Circuit Allows Slow Rise Times
16
Carry Out Output for Cascading PDIP16
Supply Voltage Range = 3.0 Vdc to 18 Vdc P SUFFIX MC14022BCP
AWLYYWW
CASE 648
1
16
Triple Diode Protection on All Inputs SOIC16
14022B
D SUFFIX AWLYWW
CASE 751B
1
WL or L = Wafer Lot
VDD DC Supply Voltage Range 0.5 to +18.0 V YY or Y = Year
WW or W = Work Week
(DC or Transient)
MC14022BD SOIC16 2400/Box
may occur.

MC14022B
PIN ASSIGNMENT
Q1 1 16 VDD
Q0 2 15 R
Q2 3 14 C
Q5 4 13 CE
Q6 5 12 Cout
NC 6 11 Q4
Q3 7 10 Q7
VSS 8 9 NC
NC = NO CONNECTION
BLOCK DIAGRAM FUNCTIONAL TRUTH TABLE

(Positive Logic)
Q0 2 Clock
CLOCK 14
Q1 1
Clock Enable Reset Output=n
Q2 3
Q3 7 0 X 0 n
CLOCK X 1 0 n
13 Q4 11
ENABLE 0 0 n+1
Q5 4
Q6 5 X 0 n
Q7 10 1 0 n+1
RESET 15 Cout 12 X 0 n
VDD = PIN 16 X X 1 Q0
VSS = PIN 8 X = Dont Care. If n < 4 Carry = 1,
Otherwise = 0.
NC = PIN 6, 9
LOGIC DIAGRAM
11 1 5 7
Q4 Q1 Q6 Q3
CLOCK
14
13 CARRY
CLOCK VDD C Q C Q C Q C Q 12
C C C C
ENABLE
D RQ D RQ D RQ D RQ
VSS
15
RESET
Q0 Q5 Q2 Q7
2 4 3 10
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98
MC14022B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600
Total Supply Current (4.) (5.) IT = (0.28 A/kHz)f + IDD Adc

IT 5.0

Per Package) 15 IT = (0.85 A/kHz)f + IDD

buffers switching)
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99
MC14022B

VDD





Reset to Decode Output tPHL



Clock to Cout

tPLH,
tPHL
ns




Clock to Decode Output tPHL


TurnOff Delay Time
Reset to Cout

tPLH ns

tPLH = (1.7 ns/pF) CL + 315 ns 5.0 400 800
tPLH = (0.66 ns/pF) CL + 142 ns 10 175 350

Clock Pulse Width


tWH
15
5.0

250
125
125
250
ns

10 100 50
15 75 35

Clock Frequency

fcl 5.0
10

5.0
12
2.0
5.0
MHz

15 16 6.7

Reset Pulse Width tWH 5.0 500 250 ns
10 250 125

Reset Removal Time

trem
15
5.0
190
750
95
375

ns

10 275 135
15 210 105

Clock Input Rise and Fall Time

tTLH, tTHL 5.0
10 No Limit

15

Clock Enable Setup Time tsu 5.0 350 175 ns
10 150 75

15 115 52

Clock Enable Removal Time trem 5.0 420 260 ns

10 200 100
15 140 70
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100
MC14022B
VDD
Output Output
Vout Sink Drive Source Drive
CLOCK Q0
VSS
ENABLE Q1 Clock to desired
VDD A Q2 Output
Q3 Outputs (S1 to A) (S1 to B)
RESET Q4 Clock to Q5
S1 Q5 ID Carry thru Q7 S1 to A
VSS B
Q6 (S1 to B)
Q7 VGS = VDD VDD
CLOCK C
out
VDS = Vout Vout VDD
EXTERNAL
VSS POWER
SUPPLY
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
0.01 F
500 F ID
CERAMIC
Q0
Q1
CLOCK Q2
ENABLE
Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Cout
GENERATOR
VSS CL CL CL CL CL CL CL CL CL
Figure 2. Typical Power Dissipation Test Circuit
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
R R R
C C C
CE MC14022B CE MC14022B CE MC14022B
Q0 Q1 Q6 Q7 Q0 Q1 Q6 Q7 Q1 Q6 Q7
6 DECODED
7 DECODED 6 DECODED
OUTPUTS
OUTPUTS OUTPUTS
CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE
Figure 3. Counter Expansion
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101
MC14022B
tWH
tWL 90% VDD
CLOCK 50%
10% VSS
trel tsu 20 ns
CLOCK 20 ns
VDD
ENABLE
VSS
trem 20 ns 20 ns 20 ns
VDD
RESET
VSS
tPHL tPLH tPLH
Q0 VOH
50%
VOL
tPLH tPHL tTHL
90% 50% VOH
Q1 10% VOL
tPLH tPHL tTLH
VOH
Q2 VOL
tPLH tPHL tTLH
VOH
Q3 VOL
tPLH tPHL tTLH
VOH
Q4 VOL
tPLH tPHL tTLH tPHL
VOH
Q5 VOL
tTLH tTHL tTLH tTHL
tPLH tPHL
VOH
Q6 VOL
tPLH tPHL
VOH
Q7 VOL
tPHL tTLH tTHL tPLH
Cout tPHL VOH
VOL
tTLH tTHL
Figure 4. AC Measurement Definition and Functional Waveforms
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102
MC14024B
7-Stage Ripple Counter

The MC14024B is a 7stage ripple counter with short propagation
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.
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Output Transitions Occur on the Falling Edge of the Clock Pulse MARKING
Supply Voltage Range = 3.0 Vdc to 18 Vdc DIAGRAMS
PDIP14
Schottky TTL Load Over the Rated Temperature Range P SUFFIX MC14024BCP
PinforPin Replacement for CD4024B CASE 646 AWLYYWW
14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOIC14
14024B
D SUFFIX AWLYWW
Symbol Parameter Value Unit CASE 751A

(DC or Transient)
SOEIAJ14
Iin, Iout Input or Output Current 10 mA F SUFFIX MC14024B
(DC or Transient) per Pin CASE 965 AWLYWW

TA Ambient Temperature Range 55 to +125 C WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(8Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device ORDERING INFORMATION
may occur.
3. Temperature Derating: Device Package Shipping


MC14024B
TRUTH TABLE
Clock Reset State
0 0 No Change
0 1 All Outputs Low
1 0 No Change
1 1 All Outputs Low
0 No Change
1 All Outputs Low
0 Advance One Count
1 All Outputs Low
PIN ASSIGNMENT
CLOCK 1 14 VDD
RESET 2 13 NC
Q7 3 12 Q1
Q6 4 11 Q2
Q5 5 10 NC
Q4 6 9 Q3
VSS 7 8 NC
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
LOGIC DIAGRAM
1
CLOCK C Q C Q C Q C Q
R Q R Q R Q R Q
2
RESET
12 11 4 3
Q1 Q2 Q6 Q7
Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5
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104
MC14024B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

(Per Package) 10 10 0.010 10 300

15 20 0.015 20 600



buffers switching)
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105
MC14024B






tPLH,
15 40 80
ns

Clock to Q1 tPHL
Clock to Q7


10
15

150
110
230
175


5.0
10
15

1000
400
300
2000
750
565
Reset to Qn

5.0
10

500
250
800
400



10 165 60
15 125 40

Reset Pulse Width

tWH 5.0
10
600
350
375
200

ns

15 260 150

Reset Removal Time trem 5.0 625 250 ns
10 190 75

15 145 50

Clock Input Rise and Fall Time tTLH, tTHL 5.0 1.0 s

10 8.0 ms
15 200 s

Input Pulse Frequency

fcl 5.0
10
15

2.5
8.0
12
1.0
3.0
4.0
MHz
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106
MC14024B
VDD VOL = Vout VDD VOH = Vout

VDD
C Qn C Qn
R IOH R IOL
EXTERNAL EXTERNAL
COUNT Qn TO A VSS POWER VSS POWER
LOGIC 1 LEVEL. SUPPLY SUPPLY

VDD
0.01 F
500 F ID CERAMIC
PULSE f
C Q1
GENERATOR CL
Q2
CL
Q3
CL
Q4
CL
Q5
CL
Q6
CL
R Q7
CL
VSS
Figure 3. Power Dissipation Test Circuit
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107
t WL
t WH
VDD
1 50% 2 4 8 16 32 64 128 255
CLOCK (1) VSS
t rem
RESET (2) VDD
50%
VSS
t PLH1 t PHL1 t R1
90% VOH
50%
Q1 (12) 10% VOL
t TLH t PHL2 t THL t R2
t PLH2
VOH
90%
50%
Q2 (11) 10% VOL
t PLH3
VOH
50%
Q3 (9) VOL
108
t PLH4 VOH
50%
MC14024B
http://onsemi.com
Q4 (6) VOL
t PLH5 VOH
Figure 4. Functional Waveforms

50%
Q5 (5) t PHL6 VOL
t TLH t THL t R6
t PLH6
90% VOH
50%
10%
Q6 (4) VOL
t PLH7 VOH
Q7 (3) VOL
t TLH t THL
Input t TLH and t THL = 20 ns

MC14027B
Dual J-K Flip-Flop

The MC14027B dual JK flipflop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flipflop. These devices may be
used in control, register, or toggle functions.
Supply Voltage Range = 3.0 Vdc to 18 Vdc http://onsemi.com
Logic Swing Independent of Fanout
Logic EdgeClocked FlipFlop Design MARKING
Logic state is retained indefinitely with clock level either high or low; DIAGRAMS
information is transferred to the output only on the positivegoing 16
edge of the clock pulse PDIP16
AWLYYWW
CASE 648
1
16
SOIC16
14027B
D SUFFIX AWLYWW
CASE 751B
F SUFFIX MC14027B
CASE 966
WL or L = Wafer Lot
WW or W = Work Week
(8Second Soldering)
applications of any voltage higher than maximum rated voltages to this MC14027BD SOIC16 2400/Box


MC14027B
TRUTH TABLE
Inputs Outputs*
C J K S R Qn Qn+1 Qn+1
1 X 0 0 0 1 0
X 0 0 0 1 1 0
0 X 0 0 0 0 1
X 1 0 0 1 0 1
1 1 0 0 Qo Qo Qo
X X 0 0 X Qn Qn No
Change
X X X 1 0 X 1 0
X X X 0 1 X 0 1
X X X 1 1 X 1 1
X = Dont Care = Present State
= Level Change * = Next State
PIN ASSIGNMENT
QA 1 16 VDD
QA 2 15 QB
CA 3 14 QB
RA 4 13 CB
KA 5 12 RB
JA 6 11 KB
SA 7 10 JB
VSS 8 9 SB
BLOCK DIAGRAM
S
6 J Q 1
3 C
5 K Q 2
R
4
S
10 J Q 15
13 C
11 K Q 14
R
12
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
110
MC14027B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

(Per Package) 10 2.0 0.004 2.0 60

15 4.0 0.006 4.0 120



buffers switching)
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111
MC14027B




Propagation Delay Times**

tPLH,
15 40 80
ns

Clock to Q, Q tPHL


10
15

75
50
150
100

Set to Q, Q

5.0 175 350


Reset to Q, Q

5.0 350 450


Setup Times tsu 5.0 140 70 ns

10 50 25
15 35 17
Hold Times

th 5.0
10
15
140
50
35
70
25
17

ns
Clock Pulse Width

tWH, tWL 5.0
10
330
110
165
55

ns

15 75 38

10 9.0 4.5

Clock Pulse Rise and Fall Time tTLH, tTHL
15
5.0

13

6.5
15 s

10 5.0
15 4.0
Removal Times

trem
5 90 10
ns

Set 10 45 5
15 35 3
Reset

5
10
50
25
30
15

15 20 10

Set and Reset Pulse Width tWH 5.0 250 125 ns
10 100 50

15 70 35
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112
MC14027B
20 ns 20 ns
VDD
90%
J 50%
10% VSS
20 ns 20 ns
VDD
K 90%
tsu 50%
10% VSS
tsu th
20 ns 20 ns
90% VDD
C 50%
10% VSS 20 ns 20 ns
tWH tWL 90% VDD
1 SET OR 50%
fcl RESET 10% VSS
tPLH tPHL tw trem
VOH 20 ns 20 ns
90% VDD
Q 50% 90%
CLOCK 50%
10% VOL 10% VSS
tTLH tTHL tw
tPLH
tPHL
Inputs R and S low. VOH
For the measurement of tWH, I/fcl, and PD Q or Q 50%
the Inputs J and K are kept high. VOL
Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(J, K, Clock, and Output) (Set, Reset, Clock, and Output)
LOGIC DIAGRAM
S
Q
C
J
C
C
C
K C C
C C
R
Q
C
C C
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113
MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
The MC14028B decoder is constructed so that an 8421 BCD code
on the four inputs provides a decimal (oneoften) decoded output,
while a 3bit binary input provides a decoded octal (oneofeight)
code output with D forced to a logic 0. Expanded decoding such as http://onsemi.com
binarytohexadecimal (oneof16), etc., can be achieved by using
other MC14028B devices. The part is useful for code conversion,
MARKING
address decoding, memory selection control, demultiplexing, or
DIAGRAMS
readout decoding.
16
Diode Protection on All Inputs PDIP16
CASE 648 AWLYYWW
Positive Logic Design
16
Low Outputs on All Illegal Input Combinations SOIC16
Similar to CD4028B. D SUFFIX
14028B
AWLYWW
CASE 751B
1

F SUFFIX MC14028B
VDD DC Supply Voltage Range 0.5 to +18.0 V CASE 966 AWLYWW
1
(DC or Transient)
WL or L = Wafer Lot
PD Power Dissipation, 500 mW YY or Y = Year
per Package (Note 3.) WW or W = Work Week

(8Second Soldering) Device Package Shipping
may occur.
3. Temperature Derating: MC14028BD SOIC16 2400/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14028BF SOEIAJ16 See Note 1.
highimpedance circuit. For proper operation, Vin and Vout should be constrained MC14028BFEL SOEIAJ16 See Note 1.

MC14028B
PIN ASSIGNMENT
Q4 1 16 VDD
Q2 2 15 Q3
Q0 3 14 Q1
Q7 4 13 B
Q9 5 12 C
Q5 6 11 D
Q6 7 10 A
VSS 8 9 Q8
TRUTH TABLE
D C B A Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 0 0 0 0 0 0 0 1 0 0 0 0
0 1 0 1 0 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0
BLOCK DIAGRAM
10 A Q0 3
Q1 14
3BIT Q2 2
BINARY 13 B Q3 15 OCTAL
8421 DECODED
INPUTS Q4 1 DECIMAL
BCD OUTPUTS
Q5 6 DECODED
INPUTS
OUTPUTS
12 C Q6 7
Q7 4
Q8 9
11 D Q9 5
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
115
MC14028B

VDD
55_C 25_C 125_C


Output Voltage 0 Level 5.0 0.05 0 0.05 0.05 Vdc

Vin = VDD or 0 VOL 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH
5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

Input Voltage 0 Level Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

VIL
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

VIH
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

Output Drive Current mAdc
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) IOH 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink
IOL
5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0


buffers switching)


Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH,
tTHL 5.0 100 200
ns



tPLH,
tPHL 5.0 300 600
ns

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116
MC14028B
20 ns 20 ns
Inputs B, C, and D VDD All outputs connected
switching in respect 90% to respective CL loads.
INPUT A 50%
to a BCD code. f in respect to a system
10%
VSS clock.
1/f
20 ns 20 ns
VDD
INPUT C 90%
50%
10%
VSS
Inputs A, B, and D low. tPLH tPHL
VOH
90%
Q4 50%
10%
VOL
tTLH tTHL
Figure 1. Dynamic Signal Waveforms
LOGIC DIAGRAM
Q0
Q1
A
Q2
Q3
B
Q4
Q5
C
Q6
Q7
D
Q8
Q9
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117
MC14028B
APPLICATIONS INFORMATION INPUTS

D C B A
Expanded decoding can be performed by using the
MC14028B and other CMOS Integrated Circuits. The
circuit in Figure 2 converts any 4bit code to a decimal or
hexadecimal code. The accompanying table shows the input
binary combinations, the associated output numbers that D C B A D C B A
go high when selected, and the redefined output MC14028B MC14028B
numbers needed for the proper code. For example: For the Q9 Q0 Q9 Q0
combination DCBA = 0111 the output number 7 is redefined
for the 4bit binary, 4bit gray, excess3, or excess3 gray 15 8 15 0
codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6bit
OUTPUT NUMBERS
binary 1of64 decoder using nine MC14028B circuits and
two MC14069UB inverters. Figure 2. Code Conversion Circuit and Truth Table
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
as shown in Figure 4.
Code and Redefined

Output Numbers
Hexadecimal Decimal
Excess3
Excess3
Inputs Output Numbers
Binary
Aiken
4Bit
4Bit
Gray
Gray
4221
D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 0 2 2
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 2 0 3 3
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 7 1 4 4
0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 5 6 2 3
0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 4 3 1 4
0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 7 5 4 2
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 15 5
1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14 6 5
1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12 7 9 6
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13 8 5
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8 9 5 6
1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9 6 7 7
1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11 8 8 8
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10 7 9 9
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118
MC14028B
INPUTS
A B C D E F INHIBIT
(NO SELECTION)
A B C D
MC14028B
Q0 Q9
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B
Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9
0 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63
*1/6 MC14069UB 64 OUTPUTS (SELECTED OUTPUT IS HIGH)
Figure 3. SixBit Binary 1of64 Decoder
APPROPRIATE APPROPRIATE
Q0 VOLTAGE VOLTAGE
A Q1 NEON INCANDESCENT
Q2 DISPLAY DISPLAY
B Q3
Q4 OR
MC14028B Q5
C Q6
Q7 0
Q8 9 9 2 1 0
D Q9
Figure 4. Decimal Digit Display Application
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119
MC14029B
Binary/Decade Up/Down
Counter
The MC14029B Binary/Decade up/down counter is constructed

with MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. The counter consists of type D flipflop
stages with a gating structure to provide toggle flipflop capability. http://onsemi.com
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
MARKING
difference counting and frequency synthesizer applications where low
DIAGRAMS
power dissipation and/or high noise immunity is desired. It is also
16
useful in A/D and D/A conversion and for magnitude and sign
PDIP16
generation. P SUFFIX MC14029BCP
AWLYYWW
Diode Protection on All Inputs CASE 648
Internally Synchronous for High Speed

Logic EdgeClocked Design Count Occurs on Positive Going
16
SOIC16
Edge of Clock 14029B
D SUFFIX
AWLYWW
Asynchronous Preset Enable Operation CASE 751B
Pin for Pin Replacement for CD4029B 16
SOEIAJ16
F SUFFIX MC14029B
CASE 966 AWLYWW

WL or L = Wafer Lot
PD Power Dissipation, 500 mW ORDERING INFORMATION
TL Lead Temperature 260 C MC14029BD SOIC16 2400/Box
may occur. MC14029BF SOEIAJ16 See Note 1.
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14029BFEL SOEIAJ16 See Note 1.

static voltages or electric fields. However, precautions must be taken to avoid ON Semiconductor representative.

MC14029B
PIN ASSIGNMENT
PE 1 16 VDD
TRUTH TABLE
Q3 2 15 CLK
Preset
P3 3 14 Q2
Carry In Up/Down Enable Action
P0 4 13 P2
1 X 0 No Count
Cin 5 12 P1
0 1 0 Count Up
0 0 0 Count Down Q0 6 11 Q1
X X 1 Preset Cout 7 10 U/D
X = Dont Care VSS 8 9 B/D

55_C 25_C 125_C

VDD

Output Voltage

Vin = VDD or 0

0 Level

VOL 5.0
10

0.05
0.05

0
0
0.05
0.05

0.05
0.05
Vdc

15 0.05 0 0.05 0.05

1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95

15 14.95 14.95 15 14.95


(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc

(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



(Vin = 0)
Adc

(Per Package) 10 10 0.010 10 300

15 20 0.015 20 600



buffers switching)
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121
MC14029B

All Types






Clk to Q tPHL



Clk to Cout tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 250 500



Cin to Cout tPLH, ns



PE to Q tPLH, ns


15 80 160

PE to Cout tPLH, ns
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns tPHL 5.0 320 640


15 105 210

Clock Pulse Width tW(cl) 5.0 180 90 ns
10 80 40

15 60 30


10 8.0 4.0
15 10 5.0

Preset Removal Time

The Preset Signal must be low prior to a positivegoing
trem 5.0
10
160
80
80
40

ns

transition of the clock. 15 60 30
s

Clock Rise and Fall Time tr(cl) 5.0 15
tf(cl) 10 5

15 4

Carry In Setup Time tsu 5.0 150 75 ns

10 60 30
15 40 20

Up/Down Setup Time

5.0
10
15
340
140
100
170
70
50

ns

Binary/Decade Setup Time

5.0
10
320
140
160
70

ns

15 100 50

Preset Enable Pulse Width tW 5.0 130 65 ns
10 70 35

15 50 25
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122
MC14029B
VDD
500 pF ID 0.01 F
CERAMIC
PE Q0
Cin
B/D Q1
PULSE U/D
CLK Q2
GENERATOR CL
P0
P1 Q3 CL
P2 CL
P3 Cout CL
CL
20 ns 20 ns
VDD
50% 90%
CLK 10%
VSS
VARIABLE
WIDTH
VDD
PE Q0
PROGRAMMABLE Cin
PULSE B/D Q1
GENERATOR U/D
CLK Q2
P0 CL
P1 Q3 CL
P2 CL
P3 Cout CL
CL
VSS
tW
tsu trem
CARRY IN OR 1/fcl
VDD
UP/DOWN 50%
OR BINARY/DECADE VSS
VDD
CLOCK 50%
VSS
tW VDD
PRESET ENABLE
VSS
20 ns
Cout ONLY tTLH
VOH
Q0 OR CARRY OUT 90% 10% 90%
10% VOL
tPLH
tTHL tPHL tPLH
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123
MC14029B
TIMING DIAGRAM
CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Cout MC14029B Cin Cout Cin Cout MC14029B Cin
U/D U/D MC14029B U/D
MSD LSD
B/D PE B/D PE B/D PE OUTPUT
P3 P2 P1 P0 CLK P3 P2 P1 P0 CLK P3 P2 P1 P0 CLK
VDD VDD VDD VDD

1 2 3
INPUT
CLOCK
CLOCK
Cout 1 (LSD)
Cout 2
Cout 3 (MSD)
PE
123
122
121
120
101
100
123
122
119
99
10
11
COUNT
9
1
0
*tW ^ 900 ns @ VDD = 5 V

Figure 3. Divide by N BCD Down Counter and Timing Diagram
(Shown for N = 123)
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124
9 4 P0 12 P1 13 P2 3 P3
BINARY/DECADE
1
PRESET ENABLE
5 PE P0 PE P1 PE P2 PE P3
CARRY IN TE Q0 TE Q1 TE Q2 TE Q3
125
7
CLK Q0 CLK Q1 CLK Q2 CLK Q3 CARRY OUT

MC14029B
LOGIC DIAGRAM
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10
UP/DOWN
15
CLOCK
6 Q0 1 Q1 14 Q2 2 Q3
MC14040B
12-Bit Binary Counter

The MC14040B 12stage binary counter is constructed with MOS
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
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Applications include time delay circuits, counter controls, and
frequencydriving circuits. MARKING
Fully Static Operation DIAGRAMS

PDIP16
P SUFFIX MC14040BCP
Capable of Driving Two Lowpower TTL Loads or One Lowpower CASE 648 AWLYYWW

Common Reset Line 16
PinforPin Replacement for CD4040B SOIC16
14040B
D SUFFIX AWLYWW
CASE 751B
1
Symbol Parameter Value Unit TSSOP16 14
VDD DC Supply Voltage Range 0.5 to +18.0 V DT SUFFIX 040B
CASE 948F ALYW
(DC or Transient) 1
Iin, Iout Input or Output Current 10 mA 16
(DC or Transient) per Pin SOEIAJ16
F SUFFIX MC14040B
PD Power Dissipation, 500 mW AWLYWW
per Package (Note 3.) CASE 966
TA Ambient Temperature Range 55 to +125 C 1
Tstg Storage Temperature Range 65 to +150 C A = Assembly Location

WL or L = Wafer Lot
YY or Y = Year
(8Second Soldering)
WW or W = Work Week
may occur.
3. Temperature Derating: ORDERING INFORMATION
static voltages or electric fields. However, precautions must be taken to avoid MC14040BCP PDIP16 2000/Box
highimpedance circuit. For proper operation, Vin and Vout should be constrained MC14040BD SOIC16 2400/Box


MC14040B
PIN ASSIGNMENT
Q12 1 16 VDD
Q6 2 15 Q11
Q5 3 14 Q10
Q7 4 13 Q8
Q4 5 12 Q9
Q3 6 11 R
Q2 7 10 C
VSS 8 9 Q1
TRUTH TABLE
0 No Change
0 Advance to next state
X 1 All Outputs are low
X = Dont Care
LOGIC DIAGRAM
Q1 Q2 Q3 Q10 Q11 Q12

9 7 6 14 15 1
CLOCK
C Q C Q C Q C Q C Q C
R R R R R R
RESET
11
Q4 = PIN 5 Q7 = PIN 4 VDD = PIN 16

Q6 = PIN 2 Q9 = PIN 12
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127
MC14040B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0


buffers switching)
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128
MC14040B

VDD


TTLH, TTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200

TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100

TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80

Propagation Delay Time tPLH,
Clock to Q1 tPHL ns

tPHL, tPLH = (1.7 ns/pF) CL + 315 ns 5.0 260 520
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns

10 115 230
Clock to Q12

5.0
10

1625
720
3250
1440
ns



tPHL
15 500 1000
ns

Reset to Qn
tPHL = (1.7 ns/pF) CL + 485 ns 5.0 370 740

tPHL = (0.86 ns/pF) CL + 182 ns

10
15

155
115
310
230

10 150 55

15 115 38


10 7.0 3.5
15 10.0 4.5


tTLH, tTHL 5.0
10
15
No Limit
ns

Reset Pulse Width

tWH 5.0
10
960
360
320
120

ns

15 270 80

10 50 25

15 30 15
VDD
VDD
0.01 F PULSE
500 F ID C Q1
CERAMIC GENERATOR
Q2
Q CL
R n CL
PULSE
C Q1 CL
GENERATOR VSS
Q2
Q CL
R n CL
VSS CL
20 ns 20 ns
CLOCK
90%
50%
10%
20 ns 20 ns tWH
tPLH tPHL
VDD
CLOCK 90%
50% Q 90%
10% VSS 50%
10%
50% DUTY CYCLE tTLH tTHL
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129
MC14040B
1 2 4 8 16 32 64 128 256 512 1024 2048 4096

CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
TIMEBASE GENERATOR outputs Q5, Q10, Q11, and Q12 division by 3600 is
A 60 Hz sinewave obtained through a 1.0 Megohm accomplished. The MC14012B decodes the counter
resistor connected directly to a standard 120 Vac power line outputs, produces a single output pulse, and resets the binary
is applied to the clock input of the MC14040B. By selecting counter. The resulting output frequency is 1.0 pulse/minute.
VDD
1.0 M MC14040B
C Q5 1.0 PULSE/MINUTE
20 pF Q10 OUTPUT
1/2 1/2
120 Vac MC14012B MC14012B
Q11
60 Hz
R Q12
VSS
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130
MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
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input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic 0 state, data is transferred MARKING
during the low clock level, and when the polarity input is in the logic DIAGRAMS
1 state the transfer occurs during the high clock level. 16
PDIP16
Buffered Data Inputs P SUFFIX MC14042BCP
AWLYYWW
Common Clock CASE 648
Clock Polarity Control 1
Q and Q Outputs 16
Double Diode Input Protection SOIC16
14042B
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc D SUFFIX AWLYWW
CASE 751B
1
16
SOEIAJ16
F SUFFIX MC14042B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) CASE 966 AWLYWW
1
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V WL or L = Wafer Lot
(DC or Transient) YY or Y = Year
Iin, Iout Input or Output Current 10 mA WW or W = Work Week
per Package (Note 3.) ORDERING INFORMATION
TA Ambient Temperature Range 55 to +125 C Device Package Shipping
Tstg Storage Temperature Range 65 to +150 C MC14042BCP PDIP16 2000/Box
(8Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device MC14042BDR2 SOIC16 2500/Tape & Reel
may occur.
3. Temperature Derating: MC14042BF SOEIAJ16 See Note 1.
MC14042BFR1 SOEIAJ16 See Note 1.
applications of any voltage higher than maximum rated voltages to this MC14042BFR2 SOEIAJ16 See Note 1.
to the range VSS v (Vin or Vout) vVDD. 1. For ordering information on the EIAJ version of
Unused inputs must always be tied to an appropriate logic voltage level (e.g., the SOIC packages, please contact your local
either VSS or VDD). Unused outputs must be left open. ON Semiconductor representative.

MC14042B
PIN ASSIGNMENT
Q3 1 16 VDD
Q0 2 15 Q3
Q0 3 14 D3
D0 4 13 D2
CLOCK 5 12 Q2
POLARITY 6 11 Q2
D1 7 10 Q1
VSS 8 9 Q1
TRUTH TABLE
Clock Polarity Q
0 0 Data
1 0 Latch
1 1 Data
0 1 Latch
LOGIC DIAGRAM
D0 LATCH Q0
5 4 2
CLOCK 1
Q0
POLARITY 3
6
D1 LATCH Q1
7 10
2
Q1
9
D2 LATCH Q2
13 11
3
Q2
12
VDD = PIN 16
VSS = PIN 8
D3 LATCH Q3
14 1
4
Q3
15
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132
MC14042B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

1.0
2.0

0.002
0.004
1.0
2.0

30
60
Adc

15 4.0 0.006 4.0 120

IT 5.0


(CL = 50 pF on all outputs all
buffers switching)
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133
MC14042B





Propagation Delay Time, D to Q, Q tPLH, no



Propagation Delay Time, Clock to Q, Q tPLH, ns



Clock Pulse Width tWH ns
5.0 300 150

10
15
100
80
50
40

Clock Pulse Rise and Fall Time tTLH, s
tTHL 5.0 15

10
15

5.0
4.0

Hold Time th ns
5.0 100 50

10 50 25

15 40 20

Setup Time tsu ns
5.0 50 0

10 30 0
15 25 0
VDD
1
16
f
20 ns 20 ns
5 90%
CLOCK Q0 2 50%
6 10%
Q0 3 DATA INPUT
POLARITY tPLH tPHL
PULSE 4 Q1 10
D0 Q1 9 90%
GENERATOR 1 50%
7 Q2 11 10%
D1 Q OUTPUT
13 Q2 12 tTLH tTHL
D2
14 Q3 1 tPHL
D3 Q3 15 Q OUTPUT
90%
50%
10%
8 VSS
For Power Dissipation test, each output tTHL tTLH
is loaded with capacitance CL.
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

(Data to Output)
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134
MC14042B
VDD
16
PULSE 5
CLOCK Q0 2
GENERATOR 1
6 Q0 3
POLARITY
4 Q1 10
PULSE
D0 Q1 9
GENERATOR 2 7
D1 Q2 11
13 Q2 12
D2 Q3 1
14
D3 Q3 15
NOTE: CL connected to output under test. 8 VSS
20* ns 20 ns
90%
50%
CLOCK INPUT 10% tWH
P.G. 1 20 ns
90%
50%
DATA INPUT tsu th
P.G. 2
tPLH
Q OUTPUT 90%
50%
10%
*Input clock rise time is 20 ns except for maximum rise time test.
Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)
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135
MC14043B, MC14044B
CMOS MSI
Quad RS Latches
The MC14043B and MC14044B quad RS latches are constructed
with MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output http://onsemi.com
and set and reset inputs. The Q outputs are gated through threestate
buffers having a common enable input. The outputs are enabled with a MARKING
logical 1 or high on the enable input; a logical 0 or low DIAGRAMS
disconnects the latch from the Q outputs, resulting in an open circuit at 16
the Q outputs. PDIP16
P SUFFIX MC140XXBCP
Double Diode Input Protection CASE 648 AWLYYWW
ThreeState Outputs with Common Enable 1
Outputs Capable of Driving Two Lowpower TTL Loads or One
16
LowPower Schottky TTL Load Over the Rated Temperature Range
SOIC16
Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
140XXB
AWLYWW
CASE 751B
1
16
SOEIAJ16
Symbol Parameter Value Unit F SUFFIX MC140XXB
CASE 966 AWLYWW
(DC or Transient)
XX = Specific Device Code
YY or Y = Year
WW or W = Work Week
Tstg Storage Temperature Range 65 to +150 C ORDERING INFORMATION

(8Second Soldering)
may occur. MC14043BD SOIC16 2400/Box
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14043BDR2 SOIC16 2500/Tape & Reel
This device contains protection circuitry to guard against damage due to high MC14043BF SOEIAJ16 See Note 1.
applications of any voltage higher than maximum rated voltages to this MC14043BFEL SOEIAJ16 See Note 1.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14044BD SOIC16 2400/Box


MC14043B, MC14044B
PIN ASSIGNMENT
MC14043B MC14044B
Q3 1 16 VDD Q3 1 16 VDD
Q0 2 15 R3 NC 2 15 S3
R0 3 14 S3 S0 3 14 R3
S0 4 13 NC R0 4 13 Q0
E 5 12 S2 E 5 12 R2
S1 6 11 R2 R1 6 11 S2
R1 7 10 Q2 S1 7 10 Q2
VSS 8 9 Q1 VSS 8 9 Q1
NC = NO CONNECTION
MC14043B MC14044B
4 4
S0 2 R0 13
Q0 Q0
3 3
R0 S0
6 6
S1 9 R1 9
Q1 Q1
7 VDD = PIN 16 7 VDD = PIN 16

R1 S1
VSS = PIN 8 VSS = PIN 8
12 NC = PIN 13 12 NC = PIN 2
S2 10 R2 10
Q2 Q2
11 11
R2 S2
14 14
S3 1 TRUTH TABLE R3 1 TRUTH TABLE
Q3 Q3
S R E Q S R E Q
X X 0 High X X 0 High
15 Impedance Impedance
15
R3 0 0 1 No Change S3 0 0 1 0
0 1 1 0 0 1 1 1
5 1 0 1 1 5 1 0 1 0
ENABLE 1 1 1 1 1 1 1 No Change
ENABLE
X = Dont Care X = Dont Care
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137
MC14043B, MC14044B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

1.0
2.0

0.002
0.004
1.0
2.0

30
60
Adc

15 4.0 0.006 4.0 120

IT 5.0


(CL = 50 pF on all outputs all
buffers switching)

Current

ThreeState Output Leakage

ITL 15 0.1 0.0001 0.1 3.0
Adc
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138
MC14043B, MC14044B

VDD


tTLH = (1.35 ns/pF) CL + 32.5 ns

5.0
10
15

100
50
40
200
100
80

Output Fall Time

tTHL = (1.35 ns/pF) CL + 32.5 ns
tTHL
5.0 100 200
ns

tTHL = (0.60 ns/pF) CL + 20 ns 10 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 40 80


tPLH = (0.90 ns/pF) CL + 130 ns 5.0 175 350
tPLH = (0.36 ns/pF) CL + 57 ns 10 75 175

tPLH = (0.26 ns/pF) CL + 47 ns 15 60 120

tPHL = (0.90 ns/pF) CL + 130 ns tPHL 5.0 175 350 ns
tPHL = (0.90 ns/pF) CL + 57 ns 10 75 175

Set, Set Pulse Width


tW
15
5.0

200
60
80
120
ns

10 100 40
15 70 30

Reset, Reset Pulse Width

tW 5.0
10
15
200
100
70
80
40
30

ns

ThreeState Enable/Disable Delay

tPLZ,
tPHZ,
5.0
10

150
80
300
160
ns

tPZL, 15 55 110
tPZH
AC WAVEFORMS
MC14043B MC14044B
20 ns 20 ns 20 ns 20 ns
VDD VDD
90% 90%
50% 50%
SET 10% SET 10%
VSS VSS
20 ns 20 ns 20 ns 20 ns
VDD
90% 90% VDD
50% 50%
RESET 10% RESET 10%
VSS VSS
tTHL tTLH
tTLH tTHL
VOH VOH
90% 90%
Q 10% 50% Q 50%
VOL 10% VOL
tPHL tPLH
tPLH tPHL
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139
MC14043B, MC14044B
THREESTATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3State Tests VDD
MC14043B MC14044B
Test Enable S1 S2 Q S R S R
tPZH Open Closed A VDD VSS VSS VDD S1
tPZL Closed Open B VSS VDD VDD VSS TO

1k
OUTPUT
tPHZ Open Closed A VDD VSS VSS VDD UNDER CL
TEST 50 pF
tPLZ Closed Open B VSS VDD VDD VSS
S2
VSS
VDD
ENABLE 50%
VSS
tPZH VDD
90%
QA 10%
tPHZ VOL
tPZL
tPLZ VOH
QB
10%
VSS
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140
MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltagecontrolled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
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signals. The selfbias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate) MARKING
provides a digital error signal PC1out, and maintains 90 phase shift at DIAGRAMS
the center frequency between PCAin and PCBin signals (both at 50% 16
duty cycle). Phase comparator 2 (with leading edge sensing logic) PDIP16
P SUFFIX MC14046BCP
provides digital error signals, PC2out and LD, and maintains a 0 AWLYYWW
phase shift between PCA in and PCBin signals (duty cycle is CASE 648
immaterial). The linear VCO produces an output signal VCOout 1
whose frequency is determined by the voltage of input VCOin and the 16
capacitor and resistors connected to pins C1A, C1B, R1, and R2. The 14046B
SOIC16
sourcefollower output SFout with an external resistor is used where DW SUFFIX
the VCOin signal is needed but no loading can be tolerated. The inhibit CASE 751G
input Inh, when high, disables the VCO and source follower to AWLYYWW
minimize standby power consumption. The zener diode can be used to 1
assist in power supply regulation. 16
Applications include FM and FSK modulation and demodulation, SOEIAJ16
frequency synthesis and multiplication, frequency discrimination, F SUFFIX MC14046B
tone decoding, data synchronization and conditioning, CASE 966 AWLYWW
voltagetofrequency conversion and motor speed control.
1
Buffered Outputs Compatible with MHTL and LowPower TTL A = Assembly Location
Diode Protection on All Inputs WL or L = Wafer Lot
YY or Y = Year
Supply Voltage Range = 3.0 to 18 V WW or W = Work Week
Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited ORDERING INFORMATION
Phase Comparator 2 switches on Rising Edges and is not Duty Cycle Device Package Shipping
Limited
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) MC14046BDW SOIC16 2350/Box
MC14046BDWR2 SOIC16 1000/Tape & Reel
Vin Input Voltage Range (All Inputs) 0.5 to VDD + 0.5 V
Iin DC Input Current, per Pin 10 mA
TA Operating Temperature Range 55 to +125 C
This device contains protection circuitry to guard
Tstg Storage Temperature Range 65 to +150 C against damage due to high static voltages or electric
2. Maximum Ratings are those values beyond which damage to the device fields. However, precautions must be taken to avoid ap-
may occur. plications of any voltage higher than maximum rated
3. Temperature Derating: voltages to this highimpedance circuit. For proper
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C operation, Vin and Vout should be constrained to the
range VSS v v
(Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.

MC14046B
BLOCK DIAGRAM PIN ASSIGNMENT
SELF BIAS PHASE LD 1 16 VDD

PCAin 14 2 PC1out
CIRCUIT COMPARATOR 1 PC1out 2 15 ZENER
PHASE 13 PC2out
PCBin 3 14 PCAin
PCBin 3 COMPARATOR 2 1 LD
VOLTAGE 4 VCOout VCOout 4 13 PC2out
VCOin 9 11 R1
CONTROLLED INH 5 12 R2
12 R2
VDD = PIN 16 OSCILLATOR 6 C1A
(VCO) 7 C1B C1A 6 11 R1
VSS = PIN 8
C1B 7 10 SFout
INH 5 SOURCE FOLLOWER 10 SFout
VSS 15 ZENER VSS 8 9 VCOin

VDD 55_C 25_C 125_C

Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
VOL 5.0 0.05 0 0.05 0.05 Vdc

Output Voltage 0 Level
Vin = VDD or 0 10 0.05 0 0.05 0.05

15 0.05 0 0.05 0.05

1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95

Input Voltage (4.)

0 Level VIL
15 14.95 14.95 15 14.95
Vdc

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc)

(VO = 0.5 or 4.5 Vdc)

1 Level VIH
15
5.0

3.5
4.0

3.5
6.75
2.75
4.0

3.5
4.0
Vdc

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

Output Drive Current

(VOH = 2.5 Vdc)

Source
IOH
5.0 1.2 1.0 1.7 0.7
mAdc

(VOH = 4.6 Vdc) 5.0 0.25 0.2 0.36 0.14
(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35

(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1


(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4

Input Current

Input Capacitance

Iin
Cin
15

0.1

0.00001
5.0
0.1
7.5

1.0

Adc
pF

Quiescent Current

(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V, PCBin = VDD
IDD 5.0
10
15

5.0
10
20

0.005
0.010
0.015
5.0
10
20

150
300
600
Adc

or 0 V, Iout = 0 A

Total Supply Current (5.) IT 5.0 IT = (1.46 A/kHz) f + IDD mAdc

(Inh = 0, fo = 10 kHz, CL = 50 pF, 10
R
R1 = 1.0 M, R2 = RSF = , 15 IT = (4.37 A/kHz) f + IDD

and 50% Duty Cycle)
4. Noise immunity specified for worstcase input combination.
Noise Margin for both 1 and 0 level = 1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc

5. To Calculate Total Current in General:
IT [ 2.2 x VDD
VCOin 1.65
R1
+
VDD 1.35 3/4
R2
+ 1.6 x
VCOin 1.65 3/4
RSF
+ 1 x 103 (CL + 9) VDD f +
1 x 101 VDD2 100% Duty Cycle of PCAin

100
+ IQ where: IT in A, CL in pF, VCOin, VDD in Vdc, f in kHz, and
R1, R2, RSF in M, CL on VCOout.
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142
MC14046B

ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25C)

VDD
Minimum Maximum

Characteristic Symbol Vdc Device Typical Device Units


tTLH = (3.0 ns/pF) CL + 30 ns 5.0 180 350
tTLH = (1.5 ns/pF) CL + 15 ns 10 90 150

tTLH = (1.1 ns/pF) CL + 10 ns 15 65 110


tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 175
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 75

tTHL = (0.55 ns/pF) CL + 9.5 ns 15 37 55
PHASE COMPARATORS 1 and 2

Input Resistance PCAin Rin 5.0 1.0 2.0 M
10 0.2 0.4

PCBin

Rin
15
15
0.1
150
0.2
1500

Minimum Input Sensitivity

AC Coupled PCAin

C series = 1000 pF, f = 50 kHz
Vin 5.0
10
15

200
400
700
300
600
1050
mV pp

DC Coupled PCAin, PCBin

5 to 15 See Noise Immunity

VOLTAGE CONTROLLED OSCILLATOR (VCO)
Maximum Frequency fmax 5.0 0.5 0.7 MHz

(VCOin = VDD, C1 = 50 pF

R1 = 5.0 k, and R2 = )

10
15
1.0
1.4
1.4
1.9

Temperature Frequency Stability 5.0 0.12 %/_C
(R2 = ) 10 0.04

15 0.015

Linearity (R2 = )

(VCOin = 2.5 V 0.3 V, R1 > 10 k)
(VCOin = 5.0 V 2.5 V, R1 > 400 k)

5.0
10

1.0
1.0

%

(VCOin = 7.5 V 5.0 V, R1 1000 k) 15 1.0

Output Duty Cycle 5 to 15 50 %

Input Resistance VCOin Rin 15 150 1500 M
SOURCEFOLLOWER

Offset Voltage 5.0 1.65 2.2 V

(VCOin minus SFout, RSF > 500 k) 10 1.65 2.2
15 1.65 2.2
Linearity

(VCOin = 2.5 V 0.3 V, RSF > 50 k)
(VCOin = 5.0 V 2.5 V, RSF > 50 k)

5.0 0.1
%

10 0.6
(VCOin = 7.5 V 5.0 V, RSF > 50 k) 15 0.8
ZENER DIODE

Zener Voltage (Iz = 50 A)

Dynamic Resistance (Iz = 1.0 mA)
6. The formula given is for the typical characteristics only.
VZ
RZ

6.7

7.0
100
7.3

V

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143
MC14046B
PHASE COMPARATOR 1
Input Stage
00 01
X X
11 10
PCAin PCBin
PC1out 0 1
PHASE COMPARATOR 2
Input Stage
X X 00 00 00
01 10 10 01 01 10
PCAin PCBin
11 11 11
3State
PC2out 0 1
Output Disconnected
LD (Lock Detect) 0 1 0
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams

Characteristic Using Phase Comparator 1 Using Phase Comparator 2

No signal on input PCAin.

VCO in PLL system adjusts to center
frequency (f0).
VCO in PLL system adjusts to minimum
frequency (fmin).

Phase angle between PCAin and PCBin. 90 at center frequency (f0), approaching Always 0_ in lock (positive rising edges).
0_ and 180 at ends of lock range (2fL)

Locks on harmonics of center frequency. Yes No

Signal input noise rejection. High Low

Lock frequency range (2fL).

The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax fmin.

Capture frequency range (2fC).

The frequency range of the input signal on which the loop will lock if it was initially
out of lock.

Depends on lowpass filter characteristics fC = fL
v

(see Figure 3). fC fL

Center frequency (f0). The frequency of VCOout, when VCOin = 1/2 VDD

VCO output frequency (f). 1
fmin = (VCO input = VSS)

R2(C1 + 32 pF)

Note: These equations are intended to be 1
fmax = + fmin (VCO input = VDD)

a design guide. Since calculated component
R1(C1 + 32 pF)
values may be in error by as much as a

v v
factor of 4, laboratory experimentation may Where: 10K R1 1M
v v

be required for fixed designs. Part to part 10K R2 1M
v v
frequency variation with identical passive
100pF C1 .01 F

components is typically less than 20%.
Figure 2. Design Information
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144
MC14046B
9 SOURCE 10 SFout
FOLLOWER
VCOin RSF
PCAin 14 EXTERNAL
PHASE 2 OR 13 9 VCO 4 VCOout
@ FREQUENCY f 3 LOWPASS
COMPARATOR PC1out 11 12 6 7 @ FREQUENCY Nf = f
FILTER
PCBin OR CIA CIB
PC2out R1 R2
CI
EXTERNAL
N
COUNTER
Typical LowPass Filters

Typically:
+ fmax
(a) R3 (a) R3
OUTPUT OUTPUT R4 C2 6N N
INPUT INPUT 2 pD f
2 p fL
C2
2fC [p
1
R3 C2
R4
(R3 ) 3, 000W) C2 + 100N Df R4 C2
fmax2
C2
f = fmax fmin
NOTE: Sometimes R3 is split into two series resistors each R3 2. A capacitor CC is then placed from the midpoint to ground. The value for
CC should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the
damping, R4 ^
(0.1)(R3) for optimum results.
LOWPASS FILTER

Filter A Filter B
Definitions: N = Total division ratio in feedback loop
KfKVCO KfKVCO
wn + wn +
K = VDD/ for Phase Comparator 1
K = VDD/4 for Phase Comparator 2 NR3C2 NC2(R3 R4) )
2 p D fVCO
+
z + 2K NKwn
KVCO
VDD 2 V
2 p fr z + 0.5 wn ) KfKNVCO)
for a typical design n ^ 10
(at phase detector input) f VCO
(R3C2
^ R3C2S ) 1
+ R3C21S ) 1 F(s) +
0.707
S(R3C2 ) R4C2) ) 1
F(s)
Waveforms
Phase Comparator 1 Phase Comparator 2

VDD VDD
PCAin PCAin
VSS VSS
VOH VOH
PCBin PCBin
VOL VOL
VOH VOH
PC1out LD
VOL VOL
VOH VOH
VCOin PC2out
VOL VOL
VOH
VCOin
VOL
Note: for further information, see:
(1) F. Gardner, PhaseLock Techniques, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, Miniature RC Filters Using PhaseLocked Loop, BSTJ, May, 1965.
(3) Garth Nash, PhaseLock Loop Design Fundamentals, AN535, Motorola Inc.
(4) A. B. Przedpelski, PhaseLocked Loop Design Articles, AR254, reprinted by Motorola Inc.
Figure 3. General PhaseLocked Loop Connections and Waveforms
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145
MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS PChannel and NChannel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
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provide logic level conversion using only one supply voltage, VDD.
The inputsignal high level (VIH) can exceed the VDD supply MARKING
voltage for logic level conversions. Two TTL/DTL loads can be driven DIAGRAMS
16
v
when the devices are used as a CMOStoTTL/DTL converter (VDD
= 5.0 V, VOL 0.4 V, IOL 3.2 mA). PDIP16
MC140XXBCP
P SUFFIX
Note that pins 13 and 16 are not connected internally on these AWLYYWW
CASE 648
devices; consequently connections to these terminals will not affect
1
circuit operation. 16
High Source and Sink Currents SOIC16
140XXB
D SUFFIX
HightoLow Level Converter CASE 751B
AWLYWW
Supply Voltage Range = 3.0 V to 18 V 1 16

VIN can exceed VDD
TSSOP16 14
Meets JEDEC B Specifications DT SUFFIX 0XXB
Improved ESD Protection On All Inputs CASE 948F ALYW

16
F SUFFIX MC140XXB
CASE 966
Vin Input Voltage Range 0.5 to +18.0 V
(DC or Transient) 1
Vout Output Voltage Range 0.5 to VDD + 0.5 V A = Assembly Location
(DC or Transient) WL or L = Wafer Lot
YY or Y = Year
Iin Input Current 10 mA
WW or W = Work Week
Iout Output Current 45 mA ORDERING INFORMATION
PD Power Dissipation, mW
(Plastic) 825
(SOIC) 740 MC14049BD SOIC16 2400/Box
TA Ambient Temperature Range 55 to +125 C MC14049BDR2 SOIC16 2500/Tape & Reel

Tstg Storage Temperature Range 65 to +150 C MC14049BF SOEIAJ16 See Note 1.
(8Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device MC14050BD SOIC16 2400/Box
may occur.
3. Temperature Derating: See Figure 3. MC14050BDR2 SOIC16 2500/Tape & Reel
This device contains protection circuitry to protect the inputs against damage MC14050BDTEL TSSOP16 2000/Tape & Reel
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this highimpedance circuit. For proper operation, the
ranges VSS Vin 18 V and VSS Vout VDD are recommended.

MC14049B, MC14050B
PIN ASSIGNMENT
VDD 1 16 NC
OUTA 2 15 OUTF
INA 3 14 INF
OUTB 4 13 NC
INB 5 12 OUTE
OUTC 6 11 INE
INC 7 10 OUTD
VSS 8 9 IND
LOGIC DIAGRAM
MC14049B MC14050B
3 2 3 2
5 4 5 4
7 6 7 6
9 10 9 10
11 12 11 12
14 15 14 15
NC = PIN 13, 16 NC = PIN 13, 16

VSS = PIN 8 VSS = PIN 8
VDD = PIN 1 VDD = PIN 1
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147
MC14049B, MC14050B

VDD
55_C + 25_C + 125_C



Vin = VDD 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 1.6 1.25 2.5 1.0

(VOH = 9.5 Vdc) 10 1.6 1.30 2.6 1.0

(VOH = 13.5 Vdc) 15 4.7 3.75 10 3.0

(VOL = 0.5 Vdc) 10 10 8.0 16 6.6

(VOL = 1.5 Vdc) 15 30 24 40 19


Input Capacitance (Vin = 0) Cin 10 20 pF

Quiescent Current (Per Package) IDD 5.0 1.0 0.002 1.0 30 Adc

10 2.0 0.004 2.0 60
15 4.0 0.006 4.0 120



IT 5.0
10
Adc

per package) 15

buffers switching
5. The formulas given are for the typical characteristics only at + 25_C
Where: IT is in A (per Package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency and k = 0.002.
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148
MC14049B, MC14050B
AC SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = + 25_C)

VDD


tTLH = (0.7 ns/pF) CL + 65 ns 5.0 100 160

tTLH = (0.25 ns/pF) CL + 37.5 ns 10 50 80

tTLH = (0.2 ns/pF) CL + 30 ns 15 40 60

tTHL = (0.2 ns/pF) CL + 30 ns 5.0 40 60

tTHL = (0.06 ns/pF) CL + 17 ns 10 20 40

tTHL = (0.04 ns/pF) CL + 13 ns 15 15 30

tPLH = (0.33 ns/pF) CL + 63.5 ns 5.0 80 140

tPLH = (0.19 ns/pF) CL + 30.5 ns 10 40 80

tPLH = (0.06 ns/pF) CL + 27 ns 15 30 60

Propagation Delay Time tPHL ns
tPHL = (0.2 ns/pF) CL + 30 ns 5.0 40 80

tPHL = (0.1 ns/pF) CL + 15 ns 10 20 40
tPHL = (0.05 ns/pF) CL + 12.5 ns 15 15 30
8. Data labeled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
MC14049B MC14050B MC14049B MC14050B

VDD VDD VDD VDD
1 1 1 1
IOH IOL IOL IOH

VOH VOL VOL VOH
VSS 8 VSS 8 VSS VSS
8 8
VDS = VOH VDD VDD = VOL
0 160
I OH , OUTPUT SOURCE CURRNT (mAdc)
VGS = 15 Vdc
I OL, OUTPUT SINK CURRENT (mAdc)
VGS = 5.0 Vdc

10
120
20
VGS = 10 Vdc
80
30 VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
40
40 VGS = 15 Vdc
MAXIMUM CURRENT LEVEL VGS = 5.0 Vdc
50 0
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10
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149
MC14049B, MC14050B
1200
PD , MAXIMUM POWER DISSIPATION (mW)

1100
1000
900
825
800
PER PACKAGE
740
700
600
500 (P) PDIP
400
300 (D) SOIC
200 175 mW (P)
100 120 mW (D)
0
25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (C)
Figure 3. Ambient Temperature Power Derating
20 ns 20 ns
VDD
INPUT 90%
50%
VDD 10% VSS
tPHL tPLH
1
# 90% VOH
OUTPUT
PULSE 50%
MC14049B
GENERATOR 10%
Vin Vout VOL
tPLH tTHL tTLH
8 VSS CL tPHL tPHL
VOH
OUTPUT 90%
MC14050B 50%
# Invert on MC14049B only 10% VOL
tTLH tTHL
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150
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logiclevel conversion using only one
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supply voltage, VDD. The inputsignal high level (VIH) can exceed the
VDD supply voltage for logiclevel conversions. Two TTL/DTL MARKING
v
Loads can be driven when the device is used as CMOStoTTL/DTL DIAGRAMS
converters (VDD = 5.0 V, VOL 0.4 V, IOL 3.2 mA). Note that pins 16
13 and 16 are not connected internally on this device; consequently PDIP16
connections to these terminals will not affect circuit operation. P SUFFIX MC14049UBCP
AWLYYWW
High Source and Sink Currents
CASE 648
1
HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V 16
Meets JEDEC UB Specifications

SOIC16
D SUFFIX
14049U
AWLYWW
VIN can exceed VDD CASE 751B
Improved ESD Protection on All Inputs 1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) TSSOP16 14

DT SUFFIX 049U
CASE 948F ALYW
1
Vin Input Voltage Range 0.5 to +18.0 V
SOEIAJ16
Vout Output Voltage Range 0.5 to VDD +0.5 V MC14049U
F SUFFIX
(DC or Transient) AWLYWW
CASE 966
1
Iout Output Current +45 mA A = Assembly Location
YY or Y = Year
PD Power Dissipation, mW WW or W = Work Week
Plastic 825
SOIC 740 ORDERING INFORMATION
(8Second Soldering) MC14049UBD SOIC16 2400/Box
2. Maximum Ratings are those values beyond which damage to the device MC14049UBDR2 SOIC16 2500/Tape & Reel
may occur.
3. Temperature Derating: MC14049UBDT TSSOP16 96/Rail
All Packages: See Figure 4.
MC14049UBDTR2 TSSOP16 2500/Tape & Reel
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the VSS pin, only. Extra precautions MC14049UBF SOEIAJ16 See Note 1.
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this highimpedance circuit. For proper operation, the ranges VSS v MC14049UBFEL SOEIAJ16 See Note 1.
Vin v 18 V and VSS v Vout v VDD are recommended.

MC14049UB
PIN ASSIGNMENT LOGIC DIAGRAM CIRCUIT SCHEMATIC

MC14049UB (1/6 OF CIRCUIT SHOWN)
VDD 1 16 NC
VDD
3 2
OUTA 2 15 OUTF
INA 3 14 INF
5 4 MC14049UB
OUTB 4 13 NC
INB 5 12 OUTE 7 6
OUTC 6 11 INE
INC 7 10 OUTD 9 10
VSS 8 9 IND
11 12
NC = NO CONNECTION NC = PIN 13, 16
VSS = PIN 8
14 15 VSS
VDD = PIN 1

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 Vdc) 5.0 1.0 2.25 1.0 1.0

(VO = 9.0 Vdc) 10 2.0 4.50 2.0 2.0

(VO = 13.5 Vdc) 15 2.5 6.75 2.5 2.5

1 Level VIH Vdc
(VO = 0.5 Vdc) 5.0 4.0 4.0 2.75 4.0

(VO = 1.0 Vdc) 10 8.0 8.0 5.50 8.0

(VO = 1.5 Vdc) 15 12.5 12.5 8.25 12.5

(VOH = 2.5 Vdc) Source 5.0 1.6 1.25 2.5 1.0

(VOH = 9.5 Vdc) 10 1.6 1.3 2.6 1.0

(VOH = 13.5 Vdc) 15 4.7 3.75 10 3.0

(VOL = 0.5 Vdc) 10 10 8.0 16 6.6

(VOL = 1.5 Vdc) 15 30 24 40 19


Input Capacitance (Vin = 0) Cin 10 20 pF

Quiescent Current IDD 5.0 1.0 0.002 1.0 30 Adc

(Per Package) 10 2.0 0.004 2.0 60
15 4.0 0.006 4.0 120



IT 5.0
10
Adc

Per Package) 15

buffers switching)
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152
MC14049UB

VDD


tTLH = (0.8 ns/pF) CL + 60 ns 5.0 100 160

tTLH = (0.3 ns/pF) CL + 35 ns 10 50 100

tTLH = (0.27 ns/pF) CL + 26.5 ns 15 40 60

tTHL = (0.3 ns/pF) CL + 25 ns 5.0 40 60

tTHL = (0.12 ns/pF) CL + 14 ns 10 20 40

tTHL = (0.1 ns/pF) CL + 10 ns 15 15 30

tPLH = (0.38 ns/pF) CL + 61 ns 5.0 80 120

tPLH = (0.20 ns/pF) CL + 30 ns 10 40 65

tPLH = (0.11 ns/pF) CL + 24.5 ns 15 30 50

tPHL = (0.38 ns/pF) CL + 11 ns 5.0 30 60

tPHL = (0.12 ns/PF) CL + 9 ns 10 15 30
tPHL = (0.11 ns/pF) CL + 4.5 ns 15 10 20
18
VDD = 15 Vdc
15
VDD = 10 Vdc
10 55C
VDD = 5 Vdc
5
+125C
5 10 15 18
Figure 1. Typical Voltage Transfer Characteristics versus Temperature
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153
MC14049UB
VDD VDD
1 1
IOH IOL
VOH VOL
VSS 8 VSS
8
VDS = VOH VDD VDD = VOL
0 160
I OH , OUTPUT SOURCE CURRNT (mAdc)
VGS = 15 Vdc
I OL, OUTPUT SINK CURRENT (mAdc)

VGS = 5.0 Vdc
10
120
20
VGS = 10 Vdc
80
30 VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
40
40 VGS = 15 Vdc
MAXIMUM CURRENT LEVEL VGS = 5.0 Vdc
50 0
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10
VDD
1
PULSE
Vout
1200 GENERATOR
Vin
PD , MAXIMUM POWER DISSIPATION (mW)
1100
8 VSS CL
1000
900
825
800 20 ns 20 ns
PER PACKAGE
740
700
VDD
600 INPUT 90%
500 (P) PDIP 50%
400 10% VSS
300 (D) SOIC tPHL tPLH
200 175 mW (P) 90% VOH
100 120 mW (D) OUTPUT
50%
0 10%
25 50 75 100 125 150 175 VOL
tTHL tTLH
Figure 4. Ambient Temperature Power Derating Figure 5. Switching Time Test Circuit
and Waveforms
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154
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitallycontrolled analog switches. The MC14051B effectively http://onsemi.com
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
MARKING
impedance and very low OFF leakage current. Control of analog
DIAGRAMS
signals up to the complete supply voltage range can be achieved.
16
Triple Diode Protection on Control Inputs PDIP16
Switch Function is Break Before Make P SUFFIX MC140XXBCP
AWLYYWW
CASE 648
1
Analog Voltage Range (VDD VEE) = 3.0 to 18 V
Note: VEE must be VSS v 16
Linearized Transfer Characteristics SOIC16
140XXB
Lownoise 12 nV/Cycle, f 1.0 kHz Typical D SUFFIX AWLYWW
CASE 751B
PinforPin Replacement for CD4051, CD4052, and CD4053 1
For 4PDT Switch, See MC14551B
For Lower RON, Use the HC4051, HC4052, or HC4053 HighSpeed 16
CMOS Devices TSSOP16 14
DT SUFFIX 0XXB
MAXIMUM RATINGS (Note 1.) CASE 948F ALYW
1
VDD DC Supply Voltage (Referenced 0.5 to +18.0 V
to VEE, VSS VEE) 16
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V SOEIAJ16
(DC or Transient) (Referen F SUFFIX MC140XXB
ced to VSS for Control Inputs CASE 966 AWLYWW
and VEE for Switch I/O)
1
Iin Input Current (DC or Transient) 10 mA
per Control Pin
ISW Switch Through Current 25 mA XX = Specific Device Code
PD Power Dissipation, 500 mW WL or L = Wafer Lot
per Package (Note 2.) YY or Y = Year
WW or W = Work Week
(8Second Soldering) ORDERING INFORMATION
1. Maximum Ratings are those values beyond which damage to the device See detailed ordering and shipping information in the package
may occur. dimensions section on page 163 of this data sheet.
either VSS, VEE or VDD). Unused outputs must be left open.

MC14051B, MC14052B, MC14053B
MC14051B MC14052B MC14053B

8Channel Analog Dual 4Channel Analog Triple 2Channel Analog
Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer
6 INHIBIT 6 INHIBIT 6 INHIBIT

11 A CONTROLS 10 A 11 A X 14
CONTROLS X 13 CONTROLS
10 B 9 B 10 B
9 C 12 X0 9 C
13 X0 14 X1 12 X0 Y 15 COMMONS
COMMONS
14 X1 15 X2 13 X1 OUT/IN
X 3 OUT/IN
15 X2 SWITCHES 11 X3 SWITCHES 2 Y0
COMMON
SWITCHES 12 X3 IN/OUT 1 Y0 IN/OUT 1 Y1
OUT/IN Y 3 Z 4
IN/OUT 1 X4 5 Y1 5 Z0
5 X5 2 Y2 3 Z1
2 X6 4 Y3
4 X7
VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

VSS = PIN 8 VSS = PIN 8 VSS = PIN 8
VEE = PIN 7 VEE = PIN 7 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be VSS.
PIN ASSIGMENT
MC14051B MC14052B MC14053B
X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD
X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y
X 3 14 X1 Y 3 14 X1 Z1 3 14 X
X7 4 13 X0 Y3 4 13 X Z 4 13 X1
X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0
INH 6 11 A INH 6 11 X3 INH 6 11 A
VEE 7 10 B VEE 7 10 A VEE 7 10 B
VSS 8 9 C VSS 8 9 B VSS 8 9 C
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156
MC14051B, MC14052B, MC14053B

55_C 25_C 125_C

Characteristic Symbol VDD Test Conditions Min Max Min Typ (3.) Max Min Max Unit

Power Supply Voltage

VDD
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

VDD 3.0 VSS VEE 3.0 18 3.0 18 3.0 18 V

Range
A

Quiescent Current Per IDD 5.0 Control Inputs: 5.0 0.005 5.0 150
Package 10 Vin = VSS or VDD, 10 0.010 10 300
v

15 Switch I/O: VEE VI/O 20 0.015 20 600
v VDD, and Vswitch

v

500 mV (4.)

Total Supply Current

ID(AV)

5.0 TA = 25_C only (The
(0.07 A/kHz) f + IDD
A

(Dynamic Plus 10 channel component,
Typical (0.20 A/kHz) f + IDD

Quiescent, Per Package 15 (Vin Vout)/Ron, is
not included.)
CONTROL INPUTS INHIBIT, A, B, C (Voltages Referenced to VSS)

LowLevel Input Voltage

VIL

5.0
10
15
Ron = per spec,
Ioff = per spec

1.5
3.0
4.0

2.25
4.50
6.75
1.5
3.0
4.0

1.5
3.0
4.0
V

HighLevel Input Voltage

VIH 5.0 Ron = per spec, 3.5 3.5 2.75 3.5 V

10
15
Ioff = per spec 7.0
11

7.0
11
5.50
8.25

7.0
11

Input Leakage Current Iin 15 Vin = 0 or VDD 0.1 0.00001 0.1 1.0 A


SWITCHES IN/OUT AND COMMONS OUT/IN X, Y, Z (Voltages Referenced to VEE)

Recommended VI/O Channel On or Off 0 VDD 0 VDD 0 VDD VPP
PeaktoPeak Voltage

Into or Out of the Switch

Recommended Static or Vswitch Channel On 0 600 0 600 0 300 mV

Dynamic Voltage Across
the Switch (4.) (Figure 5)

Output Offset Voltage

VOO
Vin = 0 V, No Load 10 V

ON Resistance v

Ron 5.0 Vswitch 500 mV (4.) 800 250 1050 1200

10 Vin = VIL or VIH 400 120 500 520

15 (Control), and Vin = 220 80 280 300
0 to VDD (Switch)

ON Resistance Between

Ron 5.0 70 25 70 135

Any Two Channels in the 10 50 10 50 95

Same Package 15 45 10 45 65
100 0.05 100 1000

OffChannel Leakage Ioff 15 Vin = VIL or VIH nA
Current (Figure 10) (Control) Channel to

Channel or Any One
Channel

Capacitance, Switch I/O

CI/O Inhibit = VDD 10 pF

Capacitance, Common O/I

CO/I

Inhibit = VDD pF

(MC14051B)
(MC14052B)
(MC14053B)

60
32
17

Capacitance, Feedthrough

CI/O

Pins Not Adjacent 0.15 pF

(Channel Off)
Pins Adjacent 0.47
3. Data labeled Typ is not to be used for design purposes, but is intended as an indication of the ICs potential performance.

4. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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157
MC14051B, MC14052B, MC14053B
ELECTRICAL CHARACTERISTICS (5.) (CL = 50 pF, TA = 25_C) (VEE

VSS unless otherwise indicated)
VDD VEE Typ (6.)

Characteristic Symbol Vdc All Types Max Unit
Propagation Delay Times (Figure 6) tPLH, tPHL ns
MC14051

Switch Input to Switch Output (RL = 10 k)

tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 35 90


tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 12 30
MC14052 ns

tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns

5.0
10
15
30
12
10
75
30
25

MC14053

ns

tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns 10 8.0 20

Inhibit to Output (RL = 10 k, VEE = VSS)

Output 1 or 0 to High Impedance, or
High Impedance to 1 or 0 Level
tPHZ, tPLZ,
tPZH, tPZL
ns

MC14051B 5.0 350 700

10 170 340
15 140 280

MC14052B

5.0
10
15
300
155
125
600
310
250
ns

MC14053B

5.0
10
275
140
550
280
ns

15 110 220
Control Input to Output (RL = 10 k, VEE = VSS) tPLH, tPHL ns
MC14051B

5.0
10
15
360
160
120
720
320
240

MC14052B

5.0
10
325
130
650
260
ns

15 90 180
MC14053B 5.0 300 600 ns

10
15
120
80
240
160

Second Harmonic Distortion 10 0.07 %
(RL = 10K, f = 1 kHz) Vin = 5 VPP

Bandwidth (Figure 7)

(RL = 1 k, Vin = 1/2 (VDDVEE) pp, CL = 50pF
20 Log (Vout/Vin) = 3 dB)
BW 10 17 MHz

Off Channel Feedthrough Attenuation (Figure 7)

RL = 1K, Vin = 1/2 (VDD VEE) pp
fin = 4.5 MHz MC14051B
10 50 dB

fin = 30 MHz MC14052B

fin = 55 MHz MC14053B

Channel Separation (Figure 8) 10 50 dB
(RL = 1 k, Vin = 1/2 (VDDVEE) pp,

fin = 3.0 MHz

Crosstalk, Control Input to Common O/I (Figure 9) 10 75 mV
(R1 = 1 k, RL = 10 k

Control tTLH = tTHL = 20 ns, Inhibit = VSS)
6. Data labelled Typ is not lo be used for design purposes but In intended as an indication of the ICs potential performance.
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158
MC14051B, MC14052B, MC14053B
VDD VDD VDD

IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
TRUTH TABLE 16 VDD

Control Inputs
INH 6 BINARY TO 1OF8
Select ON Switches A 11 LEVEL
DECODER WITH
Inhibit C* B A MC14051B MC14052B MC14053B B 10 CONVERTER
C 9 INHIBIT
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1 8 VSS 7 VEE
0 0 1 0 X2 Y2 X2 Z0 Y1 X0 X0 13
0 0 1 1 X3 Y3 X3 Z0 Y1 X1 X1 14
0 1 0 0 X4 Z1 Y0 X0 X2 15
0 1 0 1 X5 Z1 Y0 X1 X3 12 3 X
0 1 1 0 X6 Z1 Y1 X0 X4 1
0 1 1 1 X7 Z1 Y1 X1 X5 5
1 x x x None None None X6 2
*Not applicable for MC14052 X7 4
x = Dont Care
Figure 2. MC14051B Functional Diagram
16 VDD
16 VDD
INH 6 BINARY TO 1OF4
LEVEL
A 10 DECODER WITH INH 6 BINARY TO 1OF2
CONVERTER A 11 LEVEL
B 9 INHIBIT DECODER WITH
B 10 CONVERTER
C 9 INHIBIT
8 VSS 7 VEE
X0 12 8 VSS 7 VEE
X1 14
13 X
X2 15 X0 12
14 X
X3 11 X1 13
Y0 1 Y0 2
15 Y
Y1 5 Y1 1
3 Y
Y2 2 Z0 5
4 Z
Y3 4 Z1 3
Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram
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159
MC14051B, MC14052B, MC14053B
TEST CIRCUITS
ON SWITCH
CONTROL A
PULSE
SECTION B
GENERATOR
OF IC C
LOAD Vout
V CL
INH RL
SOURCE
VDD VEE VEE VDD
Figure 5. V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output
A, B, and C inputs used to turn ON

or OFF
the switch under test. RL
A
B A
C B ON
Vout
C
VSS INH RL CL = 50 pF
INH OFF
Vout
Vin RL CL = 50 pF
VDD VEE
2 VDD VEE Vin
2
Figure 7. Bandwidth and OffChannel Figure 8. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST

VDD
VEE
A CONTROL
B SECTION OTHER
C CHANNEL(S)
Vout OF IC VEE
INH RL CL = 50 pF VDD
R1
VEE
COMMON
VDD
Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

Common O/I
NOTE: See also Figures 7 and 8 in the MC14016B

data sheet.
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160
MC14051B, MC14052B, MC14053B
VDD KEITHLEY 160

DIGITAL
MULTIMETER
10 k
1 k
VDD RANGE XY
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS

350 350
300 300
R ON , ON RESISTANCE (OHMS)
250 250
200 200
150 150 TA = 125C

TA = 125C
100 100 25C
25C
55C 55C
50 50
0 0
10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = 7.5 V Figure 13. VDD = 5.0 V, VEE = 5.0 V
700 350
TA = 25C
600 300
RON , ON RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125C 5.0 V
200 100
25C 7.5 V
100 55C 50
0 0
10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10
Figure 14. VDD = 2.5 V, VEE = 2.5 V Figure 15. Comparison at 25C, VDD = VEE
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161
MC14051B, MC14052B, MC14053B
Figure A illustrates use of the onchip level converter peak. If voltage transients above VDD and/or below VEE are
detailed in Figures 2, 3, and 4. The 0to5 V Digital Control anticipated on the analog channels, external diodes (Dx) are
signal is used to directly control a 9 Vpp analog signal. recommended as shown in Figure B. These diodes should be
The digital control logic levels are determined by VDD small signal types able to absorb the maximum anticipated
and VSS. The VDD voltage is the logic high voltage; the VSS current surges during clipping.
voltage is logic low. For the example, VDD = + 5 V = logic The absolute maximum potential difference between
high at the control inputs; VSS = GND = 0 V = logic low. VDD and VEE is 18.0 V. Most parameters are specified up to
The maximum analog signal level is determined by VDD 15 V which is the recommended maximum difference
and VEE. The VDD voltage determines the maximum between VDD and V EE.
recommended peak above VSS. The VEE voltage Balanced supplies are not required. However, VSS must
determines the maximum swing below VSS. For the be greater than or equal to VEE. For example, VDD = + 10
example, VDD VSS = 5 V maximum swing above VSS ; V, VSS = + 5 V, and VEE 3 V is acceptable. See the Table
VSS VEE = 5 V maximum swing below VSS. The example below.
shows a 4.5 V signal which allows a 1/2 volt margin at each
+5 V 5 V
VDD VSS VEE
+ 4.5 V
+5 V 9 Vpp SWITCH
ANALOG SIGNAL I/O COMMON 9 Vpp
GND
MC14051B O/I ANALOG SIGNAL
MC14052B
EXTERNAL MC14053B
CMOS 4.5 V
DIGITAL
CIRCUITRY 0TO5 V DIGITAL INHIBIT,
CONTROL SIGNALS A, B, C
VDD VDD
DX DX
ANALOG COMMON
I/O O/I
DX DX
VEE VEE

POSSIBLE SUPPLY CONNECTIONS

Control Inputs

VDD

In Volts
VSS

In Volts
VEE
In Volts
Logic High/Logic Low
In Volts
Maximum Analog Signal Range
In Volts

+8 0 8 + 8/0 + 8 to 8 = 16 Vpp

+5 0 12 + 5/0 + 5 to 12 = 17 Vpp

+5 0 0 + 5/0 + 5 to 0 = 5 Vpp

+5

0 5 + 5/0 + 5 to 5 = 10 Vpp

+ 10

+5 5 + 10/ + 5 + 10 to 5 = 15 Vpp
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162
MC14051B, MC14052B, MC14053B
ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMATION:

Device Package Shipping MC14053BCP PDIP16 2000 Units per Box
MC14051BCP PDIP16 2000 Units per Box MC14053BD SOIC16 48 Units per Rail
MC14051BD SOIC16 48 Units per Rail MC14053BDR2 SOIC16 2500 Units / Tape & Reel
MC14051BDR2 SOIC16 2500 Units / Tape & Reel MC14053BDT TSSOP16 96 Units per Rail
MC14051BDT TSSOP16 96 Units per Rail MC14053BDTEL TSSOP16 2000 Units / Tape & Reel
MC14051BDTEL TSSOP16 2000 Units / Tape & Reel MC14053BDTR2 TSSOP16 2500 Units / Tape & Reel
MC14051BDTR2 TSSOP16 2500 Units / Tape & Reel MC14053BF SOEIAJ16 See Note 7.
MC14051BF SOEIAJ16 See Note 7. MC14053BFEL SOEIAJ16 See Note 7.
MC14051BFEL SOEIAJ16 See Note 7. 7. For ordering information on the EIAJ version of the SOIC
packages, please contact your local ON Semiconductor rep-
resentative.
MC14052BCP PDIP16 2000 Units per Box
MC14052BD SOIC16 48 Units per Rail
MC14052BDT TSSOP16 96 Units per Rail
MC14052BDTR2 TSSOP16 2500 Units / Tape & Reel
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163
MC14060B
14-Bit Binary Counter and

Oscillator
The MC14060B is a 14stage binary ripple counter with an onchip
oscillator buffer. The oscillator configuration allows design of either
RC or crystal oscillator circuits. Also included on the chip is a reset
function which places all outputs into the zero state and disables the http://onsemi.com
oscillator. A negative transition on Clock will advance the counter to
the next state. Schmitt trigger action on the input line permits very MARKING
slow input rise and fall times. Applications include time delay circuits, DIAGRAMS
16
counter controls, and frequency dividing circuits.
PDIP16
Fully static operation P SUFFIX MC14060BCP
AWLYYWW
Diode Protection on All Inputs CASE 648
Supply Voltage Range = 3.0 V to 18 V

1

Schottky TTL Load Over the Rated Temperature Range SOIC16
14060B
Buffered Outputs Available from Stages 4 Through 10 and
D SUFFIX
CASE 751B
AWLYWW
12 Through 14 1
Common Reset Line
16
TSSOP16 14
DT SUFFIX 060B
CASE 948F ALYW
VDD DC Supply Voltage Range 0.5 to +18.0 V SOEIAJ16

F SUFFIX MC14060B
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V CASE 966 AWLYWW
(DC or Transient)
1
(DC or Transient) per Pin A = Assembly Location
WL or L = Wafer Lot
(8Second Soldering) Device Package Shipping
2. Maximum Ratings are those values beyond which damage to the device MC14060BCP PDIP16 2000/Box
may occur.
3. Temperature Derating: MC14060BD SOIC16 2400/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14060BDT TSSOP16 96/Rail
MC14060BDTR2 TSSOP16 2500/Tape & Reel


MC14060B
PIN ASSIGNMENT
Q12 1 16 VDD
Q13 2 15 Q10
Q14 3 14 Q8
Q6 4 13 Q9
Q5 5 12 RESET
Q7 6 11 CLOCK
Q4 7 10 OUT 1
VSS 8 9 OUT 2
TRUTH TABLE
L No Change
L Advance to next state
X H All Outputs are low
X = Dont Care
LOGIC DIAGRAM
OUT 2
9 Q4 Q5 Q12 Q13 Q14
OUT 1 7 5 1 2 3
10
CLOCK
C Q C Q C Q C Q C Q C Q
R R R R R R
RESET
12
Q6 = PIN 4 Q8 = PIN 14 Q10 = PIN 15 VDD = PIN 16
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165
MC14060B

55_C 25_C 125_C

VDD

Output Voltage

Vin = VDD or 0

0 Level

VOL 5.0
10

0.05
0.05

0
0
0.05
0.05

0.05
0.05
V

15 0.05 0 0.05 0.05

Vin = 0 or VDD 1 Level VOH 5.0 4.95 4.95 5.0 4.95 V
10 9.95 9.95 10 9.95

15 14.95 14.95 15 14.95

Input Voltage 0 Level VIL V

(VO = 4.5 or 0.5 V) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 V) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 V) 15 4.0 6.75 4.0 4.0

(VO = 0.5 or 4.5 V) 1 Level VIH 5.0 3.5 3.5 2.75 3.5 V

(VO = 1.0 or 9.0 V) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 V) 15 11.0 11.0 8.25 11.0

Input Voltage

(VO = 4.5 Vdc)

0 Level

(For Input 11
VIL
5.0 1.0 2.25 1.0 1.0
Vdc

(VO = 9.0 Vdc) and Output 10) 10 2.0 4.50 2.0 2.0
(VO = 13.5 Vdc) 15 2.5 6.75 2.5 2.5

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

1 Level

VIH 5.0
10
4.0
8.0

4.0
8.0
2.75
5.50

4.0
8.0

Vdc

(VO = 1.5 Vdc) 15 12.5 12.5 8.25 12.5

Output Drive Current IOH mA
(VOH = 2.5 V) (Except Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 V)

(VOH = 9.5 V)
(VOH = 13.5 V)

Pins 9 and 10)

5.0
10
15
0.64
1.6
4.2

0.51
1.3
3.4
0.88
2.25
8.8

0.36
0.9
2.4

(VOL = 0.4 V)

(VOL = 0.5 V)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mA

(VOL = 1.5 V) 15 4.2 3.4 8.8 2.4

Input Current Iin 15 0.1 0.00001 0.1 1.0 A

Input Capacitance (Vin = 0) Cin 5.0 7.5 pF
A

(Per Package) 10 10 0.010 10 300

15 20 0.015 20 600

Total Supply Current (5.) (6.) IT 5.0 IT = (0.25 A/kHz) f + IDD A


(CL = 50 pF on all outputs,
all buffers switching)
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166
MC14060B
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

VDD


Output Rise Time (Counter Outputs) tTLH 5.0 40 200 ns
10 25 100

15 20 80

Output Fall Time (Counter Outputs) tTHL 5.0 50 200 ns

10 30 100
15 20 80

Clock to Q4

tPLH
tPHL
5.0
10

415
175
740
300
ns

15 125 200
s

Clock to Q14 5.0 1.5 2.7
10 0.7 1.3

15 0.4 1.0

Clock Pulse Width twH 5.0 100 65 ns

10 40 30
15 30 20


f 5.0
10

5
14
3.5
8
MHz

15 17 12

Clock Rise and Fall Time tTLH 5.0 ns
tTHL 10 No Limit

15

Reset Pulse Width tw 5.0 120 40 ns

10 60 15
15 40 10
Reset to On


tPHL 5.0
10
15

170
80
60
350
160
100
ns
VDD
VDD
PULSE CLOCK
500 F ID 0.01 F Q4
GENERATOR
NC OUT1 Q5
NC OUT2
Qn CL
R CL
PULSE CLOCK
Q4 VSS CL
GENERATOR
NC OUT1 Q5
NC OUT2 Qn CL
R 20 ns 20 ns
CL
VSS CL 90%
CLOCK
50%
10%
tWH
20 ns 20 ns tPLH tPHL
VDD
90% 90%
50% 50%
CLOCK 10% Q
VSS 10%
50% DUTY CYCLE tTLH tTHL
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167
MC14060B
CLOCK 11
f [ 2.3 R1tcCtc
if 1 kHz f 100 kHz
RESET 10 OUT 1 9 OUT 2 and 2Rtc < RS < 10Rtc
Rtc (f in Hz, R in ohms, C in farads)
The formula may vary for other frequencies. Recommended
maximum value for the resistors in 1 M.
RS Ctc
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0 100
VDD = 10 V
VDD = 15 V 50
f, OSCILLATOR FREQUENCY (kHz)

4.0 f AS A FUNCTION
FREQUENCY DEVIATION (%)
20
OF RTC
0 10 (C = 1000 pF)
(RS 2RTC)
1.0 V 5
4.0
2 f AS A FUNCTION
OF C
8.0 1 (RTC = 56 k)
5.0 V
0.5 (RS = 120 k)
12
RTC = 56 k RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25C 0.2
C = 1000 pF RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
16 0.1
55 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
TA, AMBIENT TEMPERATURE (C) RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
C, CAPACITANCE (F)
Figure 4. RC Oscillator Stability Figure 5. RC Oscillator Frequency as a
Function of RTC and C

CLOCK
11

Characteristic
500 kHz 32 kHz
Circuit Circuit Unit
RESET 10 OUT 1 9 OUT 2

Crystal Characteristics
Resonant Frequency 500 32 kHz

18M Equivalent Resistance, RS 1.0 6.2 k
RO

External Resistor/Capacitor Values
RO
CT
47
82
750
82
k
pF

CS CT CS 20 20 pF
Figure 6. Typical Crystal Oscillator Circuit

Frequency Stability
Frequency Changes as a
Function of VDD (TA = 25_C)

VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm

Frequency Change as a Function
of Temperature (VDD = 10 V)

TA Change from 55_C to + 100 + 120 ppm
+ 25_C Complete Oscillator (8.)

TA Change from + 25_C to
+ 125_C Complete Oscillator (8.)
160 560 ppm
8. Complete oscillator includes crystal, capacitors, and resistors.

Figure 7. Typical Data for Crystal Oscillator Circuit
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168
MC14066B
Quad Analog Switch/Quad

Multiplexer
The MC14066B consists of four independent switches capable of

controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation. http://onsemi.com
The MC14066B is designed to be pinforpin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings MARKING
as large as the full supply voltage can be controlled via each DIAGRAMS
independent control input. 14
PDIP14
Triple Diode Protection on All Control Inputs P SUFFIX MC14066BCP
Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646 AWLYYWW
Linearized Transfer Characteristics 1
Low Noise 12 nV/Cycle, f 1.0 kHz typical 14
PinforPin Replacement for CD4016, CD4016, MC14016B

SOIC14
D SUFFIX
14066B
AWLYWW
For Lower RON, Use The HC4066 HighSpeed CMOS Device CASE 751A
1
14
TSSOP14 14
CASE 948G ALYW
14
F SUFFIX MC14066B
Iin Input Current (DC or Transient) 10 mA CASE 965 AWLYWW
per Control Pin
1
ISW Switch Through Current 25 mA
TA Ambient Temperature Range 55 to +125 C WW or W = Work Week

TL Lead Temperature 260 C ORDERING INFORMATION
(8Second Soldering)
may occur. MC14066BCP PDIP14 2000/Box
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14066BD SOIC14 55/Rail
This device contains protection circuitry to guard against damage due to high MC14066BDR2 SOIC14 2500/Tape & Reel
static voltages or electric fields. However, precautions must be taken to avoid 96/Rail
MC14066BDT TSSOP14
MC14066BDTEL TSSOP14 2000/Tape & Reel
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14066BDTR2 TSSOP14 2500/Tape & Reel


MC14066B
PIN ASSIGNMENT
IN 1 1 14 VDD
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3
BLOCK DIAGRAM LOGIC DIAGRAM AND TRUTH TABLE

13 (1/4 OF DEVICE SHOWN)
CONTROL 1 2
1 OUT 1
IN/OUT OUT/IN
IN 1
5
CONTROL 2 3 CONTROL
4 OUT 2
IN 2 Control Switch Logic Diagram Restrictions
6 0 = VSS OFF VSS Vin VDD
CONTROL 3
9 VSS Vout VDD
OUT 3 1 = VDD ON
8
IN 3
12
CONTROL 4 10
11 OUT 4
IN 4 VDD = PIN 14
VSS = PIN 7
CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
VDD VDD VDD
VSS
VDD
VDD VDD VDD
CMOS
INPUT 300
VSS VSS
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170
MC14066B

55_C 25_C 125_C


Power Supply Voltage

VDD

3.0 18 3.0 18 3.0 18 V

Range
A

Quiescent Current Per IDD 5.0 Control Inputs: 0.25 0.005 0.25 7.5
Package 10 Vin = VSS or VDD, 0.5 0.010 0.5 15
v

15 Switch I/O: VSS VI/O 1.0 0.015 1.0 30
v

VDD, and
v Vswitch 500 mV (5.)


ID(AV)

5.0 TA = 25_C only The
A

(Dynamic Plus Quiescent, 10 channel component,

Per Package 15 (Vin Vout)/Ron, is
not included.)
CONTROL INPUTS (Voltages Referenced to VSS)

LowLevel Input Voltage

VIL

5.0
10
15
Ron = per spec,
Ioff = per spec

1.5
3.0
4.0

2.25
4.50
6.75
1.5
3.0
4.0

1.5
3.0
4.0
V


VIH 5.0 Ron = per spec, 3.5 3.5 2.75 3.5 V

10
15
Ioff = per spec 7.0
11

7.0
11
5.50
8.25

7.0
11



SWITCHES IN AND OUT (Voltages Referenced to VSS)

Recommended Peakto VI/O Channel On or Off 0 VDD 0 VDD 0 VDD Vpp
Peak Voltage Into or Out

of the Switch



Output Offset Voltage

VOO
Vin = 0 V, No Load 10 V

ON Resistance v

Ron 5.0 Vswitch 500 mV (5.), 800 250 1050 1200

10 Vin = VIL or VIH 400 120 500 520

15 (Control), and Vin = 220 80 280 300
0 to VDD (Switch)

ON Resistance Between

Ron 5.0 70 25 70 135

Any Two Channels 10 50 10 50 95

in the Same Package 15 45 10 45 65
100 0.05 100 1000

OffChannel Leakage Ioff 15 Vin = VIL or VIH nA

Channel or Any One
Channel

Capacitance, Switch I/O

CI/O Switch Off 10 15 pF

(Switch Off)


CI/O

0.47 pF
5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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171
MC14066B
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C unless otherwise noted.)

VDD


Propagation Delay Times VSS = 0 Vdc tPLH, tPHL ns
Input to Output (RL = 10 k)



Control to Output (RL = 1 k) (Figure 2)

Output 1 to High Impedance
tPHZ
5.0 40 80
ns

10 35 70
15 30 60

Output 0 to High Impedance

tPLZ 5.0
10
15

40
35
30
80
70
60
ns

High Impedance to Output 1 tPZH 5.0
10

60
20
120
40
ns

15 15 30

High Impedance to Output 0 tPZL 5.0 60 120 ns
10 20 40

Second Harmonic Distortion

VSS = 5 Vdc
15
5.0

15
0.1
30
%

(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)

Bandwidth (Switch ON) (Figure 3)

VSS = 5 Vdc
(RL = 1 k, 20 Log (Vout/Vin) = 3 dB, CL = 50 pF,
5.0 65 MHz

Vin = 5 Vpp)

Feedthrough Attenuation (Switch OFF) VSS = 5 Vdc 5.0 50 dB
(Vin = 5 Vpp, RL = 1 k, fin = 1.0 MHz) (Figure 3)

Channel Separation (Figure 4)

(Vin = 5 Vpp, RL = 1 k, fin = 8.0 MHz)
VSS = 5 Vdc 5.0 50 dB

(Switch A ON, Switch B OFF)

Crosstalk, Control Input to Signal Output (Figure 5) mVpp
VSS = 5 Vdc 5.0 300

(R1 = 1 k, RL = 10 k, Control tTLH = tTHL = 20 ns)
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172
MC14066B
TEST CIRCUITS
Vout
VC
RL CL
ON SWITCH
Vin Vx
CONTROL 20 ns
SECTION VDD
90%
OF IC VC 50%
10%
tPZH VSS
tPHZ
LOAD 90%
V Vout Vin = VDD
10%
tPZL tPLZ Vx = VSS
90%
Vout Vin = VSS
SOURCE 10% Vx = VDD
Figure 1. V Across Switch Figure 2. TurnOn Delay Time Test Circuit

and Waveforms
VDD VSS
VC = VDD FOR BANDWIDTH TEST 2
VC = VSS FOR FEEDTHROUGH TEST
VDD VSS Vin

2
RL CL
VDD
Vin Vout
RL CL
VC
RL CL
VSS
VDD VSS
Figure 3. Bandwidth and Figure 4. Channel Separation

Feedthrough Attenuation

VDD
Vin
A
Vout VSS
1k CONTROL
RL CL = 50 pF SECTION
10 k OF IC
VSS
VC = 5.0 V TO + 5.0 V SWING VDD
Figure 5. Crosstalk, Figure 6. Off Channel Leakage

Control to Output
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173
MC14066B
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
VDD RANGE XY
PLOTTER
VSS
350 350
300 300
250 250
200 200
150 150 TA = 125C

TA = 125C
100 100 25C
25C
55C 55C
50 50
0 0
10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10
Figure 8. VDD = 7.5 V, VSS = 7.5 V Figure 9. VDD = 5.0 V, VSS = 5.0 V
700 350
TA = 25C
600 300
RON , ON RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125C 5.0 V
200 100
25C 7.5 V
100 55C 50
0 0
10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10
Figure 10. VDD = 2.5 V, VSS = 2.5 V Figure 11. Comparison at 25C, VDD = VSS
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174
MC14066B
Figure A illustrates use of the Analog Switch. The 0 VDD and/or below VSS are anticipated on the analog
to5 volt digital control signal is used to directly control a channels, external diodes (Dx) are recommended as shown
5 volt peaktopeak analog signal. in Figure B. These diodes should be small signal types able
The digital control logic levels are determined by VDD to absorb the maximum anticipated current surges during
and VSS. The VDD voltage is the logic high voltage, the VSS clipping.
high at the control inputs; VSS = GND = 0 V = logic low. VDD and VSS is 18.0 volts. Most parameters are specified up
The maximum analog signal level is determined by VDD to 15 volts which is the recommended maximum difference
and VSS. The analog voltage must not swing higher than between VDD and V SS.
VDD or lower than VSS.
The example shows a 5 volt peaktopeak signal which
allows no margin at either peak. If voltage transients above
+5 V
VDD VSS
+ 5.0 V
5 Vpp SWITCH
ANALOG SIGNAL IN SWITCH 5 Vpp
+ 2.5 V
+5 V OUT ANALOG SIGNAL
GND
EXTERNAL 0TO5 V DIGITAL MC14066B
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY
VDD VDD
DX DX
SWITCH SWITCH
IN OUT
DX DX
VSS VSS
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175
MC14067B
Analog Multiplexers /
Demultiplexers
The MC14067 multiplexer/demultiplexer is a digitally controlled

analog switch featuring low ON resistance and very low leakage
current. This device can be used in either digital or analog
applications. http://onsemi.com
The MC14067 is a 16channel multiplexer/demultiplexer with an
inhibit and four binary control inputs A, B, C, and D. These control MARKING
inputs select 1of16 channels by turning ON the appropriate analog DIAGRAMS
switch (see MC14067 truth table.) 24
Low OFF Leakage Current

PDIP24
P SUFFIX MC14067BCP
Matched Channel Resistance CASE 709 AWLYYWW
Low Quiescent Power Consumption 1

Low Crosstalk Between Channels
24
Wide Operating Voltage Range: 3 to 18 V SOIC24
Low Noise DW SUFFIX
14067B
AWLYYWW
Pin for Pin Replacement for CD4067B CASE 751E
1
WL or L = Wafer Lot
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) YY or Y = Year

WW or W = Work Week


VDD DC Supply Voltage Range 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V ORDERING INFORMATION
(DC or Transient)

10

Iin Input Current (DC or Transient), mA
per Control Pin MC14067BCP PDIP24 15/Rail

Isw Switch Through Current 25 mA MC14067BDW SOIC24 30/Rail

PD Power Dissipation, 500 mW MC14067BDWR2 SOIC24 1000/Tape & Reel


TA Ambient Temperature Range 55 to + 125 _C

Tstg Storage Temperature Range 65 to + 150 _C

TL Lead Temperature 260 _C
(8Second Soldering)
may occur.
to the range VSS v(Vin or Vout) v
VDD.

MC14067B
MC14067 TRUTH TABLE

Control Inputs
Selected
A B C D Inh Channel
X X X X 1 None
0 0 0 0 0 X0
1 0 0 0 0 X1
0 1 0 0 0 X2
1 1 0 0 0 X3
0 0 1 0 0 X4
1 0 1 0 0 X5
0 1 1 0 0 X6
1 1 1 0 0 X7
0 0 0 1 0 X8
1 0 0 1 0 X9
0 1 0 1 0 X10
1 1 0 1 0 X11
0 0 1 1 0 X12
1 0 1 1 0 X13
0 1 1 1 0 X14
1 1 1 1 0 X15
MC14067B
PIN ASSIGNMENT
X 1 24 VDD
X7 2 23 X8
X6 3 22 X9
X5 4 21 X10
X4 5 20 X11
X3 6 19 X12
X2 7 18 X13
X1 8 17 X14
X0 9 16 X15
A 10 15 INHIBIT
B 11 14 C
VSS 12 13 D
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177
MC14067B
MC14067B
16Channel Analog
Multiplexer/Demultiplexer
15 INHIBIT
10 A
CONTROLS 11 B
14 C
13 D
9 X0
8 X1
7 X2
6 X3
5 X4
COMMON
4 X5 X 1
OUT/IN
3 X6
SWITCHES 2 X7
IN/OUT 23 X8
22 X9
21 X10 VDD = PIN 24
20 X11 VSS = PIN 12
19 X12
18 X13
17 X14
16 X15
MC14067 FUNCTIONAL DIAGRAM
INHIBIT
CONTROL A
B 1OF16 DECODER
INPUTS C
D
X0
X1
X2
X3
X4
X5
X6
X X7 X
IN/OUT X8
X9 OUT/IN
X10
X11
X12
X13
X14
X15
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178
MC14067B

55C 25_C 125_C


SUPPLY REQUIREMENTS (Voltages Referenced to VSS)

Power Supply Voltage VDD 3.0 18 3.0 18 3.0 18 V

Range
A

Quiescent Current Per IDD 5.0 Control Inputs: Vin = 5.0 0.005 5.0 150
Package 10 VSS or VDD, 10 0.010 10 300
v v

15 Switch I/O: VSS VI/O 20 0.015 20 600
VDD, and

v

Vswitch 500 mV (4.)


ID(AV)

5.0 TA = 25_C only (The
A

Quiescent, 15 (Vin Vout)/Ron, is

Per Package not included.)

CONTROL INPUTS INHIBIT, A, B, C, D (Voltages Referenced to VSS)

LowLevel Input Voltage VIL 5.0 Ron = per spec, 1.5 2.25 1.5 1.5 V

10 Ioff = per spec 3.0 4.50 3.0 3.0
15 4.0 6.75 4.0 4.0


VIH

5.0
10
Ron = per spec,
Ioff = per spec
3.5
7.0

3.5
7.0
2.75
5.50

3.5
7.0

V

15 11 11 8.25 11
0.1 0.00001 0.1 A

Input Leakage Current Iin 15 Vin = 0 or VDD 1.0


SWITCHES IN/OUT AND COMMONS OUT/IN X, Y (Voltages Referenced to VSS)

Out of the Switch

Peak Voltage Into or

Dynamic Voltage

Across the Switch (4.)

(Figure 1)

Output Offset Voltage VOO Vin = 0 V, No Load 10 V
v

ON Resistance Ron 5.0 Vswitch 500 mV (4.), 800 250 1050 1300
10 Vin = VIL or VIH 400 120 500 550

15 (Control), and Vin 220 80 280 320

0 to VDD (Switch)
ON Resistance Between Ron

5.0 70 25 70 135


OffChannel Leakage Ioff 15 Vin = VIL or VIH 100 0.05 100 1000 nA

Channel or Any One

Channel

Capacitance, Switch I/O CI/O Inhibit = VDD 10 pF

Capacitance, Common O/I CO/I Inhibit = VDD pF

(MC14067B)

100

(MC14097B) 60


CI/O

Pins Not Adjacent 0.47 pF

(Channel Off) Pins Adjacent
4. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
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179
MC14067B
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)

VDD VSS

Characteristic Symbol Vdc Typ (5.) Max Unit

Propagation Delay Times tPLH, tPHL ns
Channel InputtoChannel Output (RL = 200 k)

MC14067B (Figure 3) 5.0 35 90

10 15 40
15 12 30

Control InputtoChannel Output

Channel TurnOn Time (RL = 10 k)
tPZH, tPZL ns

MC14067B (Figure 4) 5.0 240 600
10 115 290

15 75 190

Channel TurnOff Time (RL = 300 k) tPHZ, tPLZ ns

MC14067B
(Figure 4) 5.0 250 625

10 120 300
15 75 190
MC14067B

Any Pair of Address Inputs to Output

tPLH, tPHL ns

5.0 280 700
10 115 290

Second Harmonic Distortion

15
10
85
0.3
215
%

(RL = 10 k, f = 1 kHz, Vin = 5 Vpp)

ON Channel Bandwidth BW MHz
[RL = 1 k, Vin = 1/2 (VDD VSS) pp(sinewave)]

20 Log10 (Vout/Vin) = 3 dB

Off Channel Feedthrough Attenuation
MC14067B (Figure 5)

10
10
15
40

dB

[RL = 1 k, Vin = 1/2 (VDDVSS) pp(sinewave)]
fin = 20 MHz MC14067B (Figure 5)

Channel Separation

[RL = 1 k, Vin = 1/2 (VDDVSS) pp (sinewave)]
10 40 dB

fin = 20 MHz (Figure 6)

Crosstalk, Control InputstoCommon O/I 10 30 mV
(R1 = 1 k, RL = 10 k,

Control tr = tf = 20 ns, Inhibit = VSS) (Figure 7)
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180
MC14067B

ON SWITCH VDD
A VSS
CONTROL
SECTION CONTROL
OF IC SECTION OTHER
OF IC CHANNEL(S) VSS
LOAD
V VDD
SOURCE
VSS
VDD
Figure 1. V Across Switch Figure 2. Off Channel Leakage
VC
PULSE A
B
GENERATOR C
VDD Vout
D
A CL = 50 pF
B INH RL
C
D Vout Vin VX
INH RL CL = 50 pF VDD VSS VSS VDD
Vin 20 ns 20 ns
90%
VC 50%
20 ns 20 ns 10%
VDD
90%
Vin 50% 90% Vin = VDD
10% Vout
VSS 50% VX = VSS
tPLH tPHL
tPZH, tPZL tPHZ, tPLZ
Vout 50%
Vout 50% Vin = VSS
10% VX = VDD
Figure 3. Propagation Delay Test Circuit Figure 4. TurnOn and Delay TurnOff
and Waveforms Vin to Vout Test Circuit and Waveforms
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181
MC14067B
VDD
A, B, and C inputs used to turn ON or OFF RL
the switch under test. A
B ON
C
A D
B
C INH OFF
D Vout Vout
INH RL CL = 50 pF
RL CL = 50 pF
Vin Vin

Feedthrough Attenuation (Adjacent Channels Used for Setup)
A
VC B
C
D Vout
INH RL CL = 50 pF
R1
Figure 7. Crosstalk, Control to Common O/I
VA A
VB B
C
D
INH VDD
VDD CL
Vout
KEITHLEY 160
DIGITAL
MULTIMETER
VA 50%
10 k
VDD
1 k
RANGE XY VB 50%
PLOTTER
VSS tPHL tPLH
Vout 50%
Figure 8. Channel Resistance (RON) Test Circuit Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output
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182
MC14067B
350 350
300 300
250 250
200 200
150 150 TA = 125C

TA = 125C
100 100 25C
25C
55C 55C
50 50
0 0
10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10
Figure 10. VDD = 7.5 V, VSS = 7.5 V Figure 11. VDD = 5.0 V, VSS = 5.0 V
700 350
TA = 25C
600 RON , ON RESISTANCE (OHMS) 300
500 250 VDD = 2.5 V
400 200
300 150
TA = 125C 5.0 V
200 100
25C 7.5 V
100 55C 50
0 0
10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 0.2 4.0 6.0 8.0 10
Figure 12. VDD = 2.5 V, VSS = 2.5 V Figure 13. Comparison at 25C, VDD = VSS
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183
MC14067B
Figure A illustrates use of the Analog signal which allows no margin at either peak. If voltage
Multiplexer/Demultiplexer. The 0to5 volt Digital Control transients above VDD and/or below VSS are anticipated on
signal is used to directly control a 5 Vpp analog signal. the analog channels, external diodes (Dx) are recommended
The digital control logic levels are determined by VDD as shown in Figure B. These diodes should be small signal
and VSS. The VDD voltage is the logic high voltage; the VSS types able to absorb the maximum anticipated current surges
voltage is logic low. For the example. VDD = + 5 V = logic during clipping.
high at the control inputs; VSS = GND = 0 V = logic low. The absolute maximum potential difference between VDD
The maximum analog signal level is determined by VDD and VSS is 18.0 volts. Most parameters are specified up to
and VSS. The analog voltage must swing neither higher than 15 V which is the recommended maximum difference
VDD nor lower than VSS. The example shows a 5 Vpp between VDD and VSS.
+5 V
VDD VSS
+ 5.0 V
5 Vpp SWITCH
ANALOG SIGNAL I/O COMMON 5 Vpp
+ 2.5 V
+5 V O/I ANALOG SIGNAL
GND
MC14067B
EXTERNAL 0TO5 V DIGITAL
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY
VDD VDD
DX DX
SWITCH COMMON
I/O O/I
DX DX
VSS VSS
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184
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS Pchannel
and Nchannel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
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Capable of Driving Two LowPower TTL Loads or One LowPower MARKING
Schottky TTL Load Over the Rated Temperature Range DIAGRAMS
Triple Diode Protection on All Inputs 14
PinforPin Replacement for CD4069UB

PDIP14
P SUFFIX MC14069UBCP
Meets JEDEC UB Specifications CASE 646 AWLYYWW
1
14
SOIC14
14069U
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) D SUFFIX AWLYWW
CASE 751A
1
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V TSSOP14 14
(DC or Transient) DT SUFFIX 069U
Iin, Iout Input or Output Current 10 mA CASE 948G ALYW
1
SOEIAJ14
MC14069U
TA Ambient Temperature Range 55 to +125 C F SUFFIX
CASE 965 AWLYWW
1
(8Second Soldering) A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
may occur.
3. Temperature Derating: WW or W = Work Week
This device contains protection circuitry to guard against damage due to high ORDERING INFORMATION
applications of any voltage higher than maximum rated voltages to this Device Package Shipping
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14069UBD SOIC14 2750/Box
MC14069UBDR2 SOIC14 2500/Tape & Reel
MC14069UBDT TSSOP14 96/Rail
MC14069UBDTEL TSSOP14 2000/Tape & Reel
MC14069UBDTR2 TSSOP14 2500/Tape & Reel
MC14069UBF SOEIAJ14 See Note 1.


MC14069UB
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 IN 6
IN 2 3 12 OUT 6
OUT 2 4 11 IN 5
IN 3 5 10 OUT 5
OUT 3 6 9 IN 4
VSS 7 8 OUT 4
LOGIC DIAGRAM CIRCUIT SCHEMATIC

1 2 VDD
VDD = PIN 14
3 4 VSS = PIN 7
5 6 INPUT* OUTPUT
9 8
11 10 VSS
*Double diode protection on all
13 12 inputs not shown.
20 ns 20 ns
VDD
VDD
14 90%
PULSE OUTPUT INPUT 50%
10% VSS
GENERATOR INPUT tPHL tPLH
7 VSS CL 90% VOH
OUTPUT 50%
10% VOL
tTHL tTLH
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186
MC14069UB

Symbo VDD
55_C 25_C 125_C

Characteristic l Vdc Min Max Min Typ (4.) Max Min Max Unit


Vin = VDD 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0

1 Level VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 Vdc) 5.0 1.0 2.25 1.0 1.0

(VO = 9.0 Vdc) 10 2.0 4.50 2.0 2.0

(VO = 13.5 Vdc) 15 2.5 6.75 2.5 2.5

1 Level VIH Vdc
(VO = 0.5 Vdc) 5.0 4.0 4.0 2.75 4.0

(VO = 1.0 Vdc) 10 8.0 8.0 5.50 8.0

(VO = 1.5 Vdc) 15 12.5 12.5 8.25 12.5

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

0.25
0.5

0.0005
0.0010
0.25
0.5

7.5
15
Adc

15 1.0 0.0015 1.0 30
Total Supply Current (5.) (6.) IT = (0.3 A/kHz) f + IDD/6 Adc

IT 5.0
(Dynamic plus Quiescent, 10 IT = (0.6 A/kHz) f + IDD/6

Per Gate) (CL = 50 pF) 15 IT = (0.9 A/kHz) f + IDD/6

Output Rise and Fall Times (5.) tTLH, ns

(CL = 50 pF) tTHL 5.0 100 200


(CL = 50 pF)

Propagation Delay Times (5.)

tPLH,
tPHL
ns




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187
MC14070B, MC14077B
CMOS SSI
Quad Exclusive OR and NOR Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic http://onsemi.com
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired. MARKING
All Outputs Buffered 14
PDIP14
Capable of Driving Two LowPower TTL Loads or One LowPower P SUFFIX MC140XXBCP
AWLYYWW
Double Diode Protection on All Inputs 1
MC14070B Replacement for CD4030B and CD4070B Types 14
MC14077B Replacement for CD4077B Type SOIC14
140XXB
D SUFFIX AWLYWW
CASE 751A
1

F SUFFIX MC140XXB
VDD DC Supply Voltage Range 0.5 to +18.0 V CASE 965 AWLYWW
1
(DC or Transient)
Iin, Iout Input or Output Current 10 mA XX = Specific Device Code
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(8Second Soldering)
may occur. MC140XXBCP PDIP14 2000/Box
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC140XXBD SOIC14 2750/Box
This device contains protection circuitry to guard against damage due to high MC140XXBDR2 SOIC14 2500/Tape & Reel
MC140XXBF SOEIAJ14 See Note 1.
MC140XXBFEL SOEIAJ14 See Note 1.

MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A 1 14 VDD
IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D
OUTB 4 11 OUTD
IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C
VSS 7 8 IN 1C
MC14070B MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
Gate Gate
1 1
3 3
2 2
5 5
4 4
6 6
8 8
10 10
9 9
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
20 ns 20 ns
VDD VDD
90%
50%
Vin 10%
IDD VSS
1/f
Vin * 50% DUTY CYCLE
CL
*Inverted output on MC14077B only.
VDD 20 ns 20 ns
VDD
PULSE 90%
* INPUT 50%
GENERATOR 10%
# VSS
CL tPHL tPLH
VSS 90% VOH
OUTPUT 50%
10% VOL
tTHL tTLH
*Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
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189
MC14070B, MC14077B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc

Vin = 0 or VDD 10 9.95 9.95 10 9.95

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

Sink IOL 5.0 0.64 0.51 0.88 0.36 mAdc

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

0.25
0.5

0.0005
0.0010
0.25
0.5

7.5
15
Adc

15 1.0 0.0015 1.0 30

IT 5.0


buffers switching)

Output Rise and Fall Times (5.)

tTLH, ns

(CL = 50 pF) tTHL

5.0

100

200


10
15

50
40
100
80

Propagation Delay Times (5.) tPLH, ns
(CL = 50 pF) tPHL


5.0
10
15

175
75
55
350
150
110

where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.
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190
MC14076B
4-Bit D-Type Register

with Three-State Outputs
The MC14076B 4Bit Register consists of four Dtype flipflops
operating synchronously from a common clock. OR gated
outputdisable inputs force the outputs into a highimpedance state
for use in bus organized systems. OR gated datadisable inputs cause http://onsemi.com
the Q outputs to be fed back to the D inputs of the flipflops. Thus they
are inhibited from changing state while the clocking process remains MARKING
undisturbed. An asynchronous master root is provided to clear all four DIAGRAMS
flipflops simultaneously independent of the clock or disable inputs. 16
ThreeState Outputs with Gated Control Lines PDIP16
MC14076BCP
P SUFFIX
Fully Independent Clock Allows Unrestricted Operation for the Two CASE 648 AWLYYWW
Modes: Parallel Load and Do Nothing 1
Asynchronous Master Reset
Four Bus Buffer Registers
16
SOIC16
Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
14076B
AWLYWW
Capable of Driving Two LowPower TTL Loads or One LowPower CASE 751B
WL or L = Wafer Lot
YY or Y = Year
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) WW or W = Work Week

VDD DC Supply Voltage Range 0.5 to +18.0 V ORDERING INFORMATION
(DC or Transient)
Iin, Iout Input or Output Current 10 mA MC14076BCP PDIP16 2000/Box
(8Second Soldering)
may occur.

MC14076B
PIN ASSIGNMENT
{B
OUTPUT A 1 16 VDD
DISABLE 2 15 R
Q0 3 14 D0
Q1 4 13 D1
Q2 5 12 D2
Q3 6 11 D3
C 7 10 B
} DATA
DISABLE
VSS 8 9 A
BLOCK DIAGRAM
15 RESET Q0 3
14 D0
13 D1
12 D2 Q1 4
11 D3
10 B DATA
9 A DISABLE Q2 5
7 CLOCK
2 B OUTPUT
1 A DISABLE Q3 6
VDD = PIN 16
VSS = PIN 8
FUNCTION TABLE
Inputs
Data Disable
Data Output
Reset Clock A B D Q
1 X X X X 0
0 0 X X X Qn
0 1 X X Qn
0 X 1 X Qn
0 0 0 0 0
0 0 0 1 1
When either output disable A or B (or both) is (are) high the
output is disabled to the highimpedance state; however
sequential operation of the flipflops is not affected.
X = Dont Care.
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192
MC14076B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0


buffers switching)

ThreeState Leakage Current

ITL 15 0.1 0.0001 0.1 3.0
Adc

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193
MC14076B

VDD





Clock to Q


Reset to Q



to High Impedance

3State Propagation Delay, Output 1 or 0

tPHZ, tPLZ 5.0
10
15

150
60
45
300
120
90
ns

to 1 or 0 Level

3State Propagation Delay, High Impedance tPZH, tPZL 5.0
10

200
80
400
160
ns

15 60 120

10 110 55

Reset Pulse Width

tWH
15
5.0
80
370
40
185

ns

10 150 75
15 110 55

Data Setup Time

tsu 5.0
10
30
10
15
5

ns

15 4 2

Data Hold Time th 5.0 130 65 ns
10 60 30

Data Disable Setup Time

tsu
15
5.0
50
220
25
110

ns

10 80 40
15 50 25

Clock Pulse Rise and Fall Time

tTLH, tTHL 5.0
10

15
5
s

15 4

10 9.0 4.5

15 12 6.0
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194
MC14076B
20 ns 20 ns
OUTPUT VDD
90%
DISABLE 50% 50% 10%
INPUT RISE AND FALL 20 ns A OR B VSS
INPUT 90% VDD tPLZ tPZL
D 50% ANY Q VOH
INFORMATION 90%
10% 2.5 V @ VDD = 5 V,
VSS OUTPUT
th th 10% 10 V, AND 15 V
tsu tsu tPHZ tPZH 2 V @ VDD = 5 V
20 ns
VDD ANY Q 90% 6 V @ VDD = 10 V
90%
50% OUTPUT 10% 10 V @ VDD = 15 V
10% VSS VOL
tWH tWL
OUTPUTS OUTPUTS OUTPUTS
fcl
tPHL CONNECTED DISCONNECTED CONNECTED
tPLH
VOH
90% ANY Q
Q OUTPUT 50%
10% OUTPUT
VOL
tTLH tTHL OTHER RL = 1 k VDD FOR tPLZ AND tPZL
INPUTS MC14076B VSS FOR tPHZ AND tPZH
RESET = 0
OUTPUT CL
DATA DISABLE A AND B = 0
DISABLE
OUTPUT DISABLE A AND B = 0
A OR B
Figure 1. Timing Diagram Figure 2. ThreeState Propagation Delay

Waveshape and Circuit
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A 1
OUTPUT DISABLE B 2
D Q
D0 14
C
R Q 3 Q0
DATA DISABLE A 9
DATA DISABLE B 10
D Q
D1 13
C
R Q 4 Q1
CLOCK 7
D Q
D2 12
C
R Q 5 Q2
D Q
D3 11
C
R Q 6 Q3
RESET 15
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195
MC14093B
Quad 2-Input NAND"

Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B http://onsemi.com
may be used in place of the MC14011B quad 2input NAND gate for
enhanced noise immunity or to square up slowly changing MARKING
waveforms. DIAGRAMS

14
PDIP14
Capable of Driving Two LowPower TTL Loads or One LowPower P SUFFIX MC14093BCP
CASE 646 AWLYYWW
Triple Diode Protection on All Inputs 1
PinforPin Compatible with CD4093 14
Can be Used to Replace MC14011B

SOIC14
D SUFFIX
14093B
AWLYWW
Independent SchmittTrigger at each Input CASE 751A
1
14
TSSOP14 14
CASE 948G ALYW
14
F SUFFIX MC14093B
Iin, Iout Input or Output Current 10 mA CASE 965 AWLYWW
1
per Package (Note 3.) A = Assembly Location
WL or L = Wafer Lot
TA Ambient Temperature Range 55 to +125 C YY or Y = Year
Tstg Storage Temperature Range 65 to +150 C WW or W = Work Week

(8Second Soldering) ORDERING INFORMATION
may occur.
3. Temperature Derating: MC14093BCP PDIP14 2000/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14093BDR2 SOIC14 2500/Tape & Reel
highimpedance circuit. For proper operation, Vin and Vout should be constrained MC14093BDT TSSOP14 96/Rail


MC14093B
PIN ASSIGNMENT
IN 1A 1 14 VDD
IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D
OUTB 4 11 OUTD
IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C
VSS 7 8 IN 1C
LOGIC DIAGRAM
1
3
2
5
6 4
8
9 10
12
11
13
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC

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197
MC14093B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

0.25
0.5

0.0005
0.0010
0.25
0.5

7.5
15
Adc

15 1.0 0.0015 1.0 30

IT 5.0


buffers switching)

Hysteresis Voltage

VH 5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Vdc

Threshold Voltage
PositiveGoing

VT+ 5.0 2.2 3.6 2.2 2.9 3.6 2.2 3.6
Vdc

10 4.6 7.1 4.6 5.9 7.1 4.6 7.1
15 6.8 10.8 6.8 8.8 10.8 6.8 10.8

NegativeGoing

VT 5.0
10
0.9
2.5
2.8
5.2
0.9
2.5
1.9
3.9
2.8
5.2
0.9
2.5
2.8
5.2
Vdc

15 4.0 7.4 4.0 5.8 7.4 4.0 7.4
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198
MC14093B

VDD


Output Rise Time tTLH 5.0 100 200 ns
10 50 100

15 40 80

Output Fall Time tTHL 5.0 100 200 ns

10 50 100
15 40 80


tPLH, tPHL 5.0
10
15

125
50
40
250
100
80
ns
7. Data labeled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
VDD
20 ns 20 ns
14 VDD
INPUT 90%
50%
PULSE OUTPUT 10% VSS
GENERATOR tPHL tPLH
INPUT VOH
7 VSS CL 90%
OUTPUT 50%
10% VOL
tTHL tTLH
VH VDD VH VDD
Vin Vin
VSS VSS
VDD VDD
Vout Vout
VSS VSS
(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
(a) inputs with slow rise and fall times. (b) noise immunity in gate applications.
Figure 2. Typical Schmitt Trigger Applications
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199
MC14093B
14 14
IOH IOL
VGS
Vout Vout
7 7
All unused inputs All unused inputs
connected to ground. VGS connected to ground.
0 10
c a b c 15 Vdc
b
VGS = 5.0 Vdc a
IOH, DRAIN CURRENT (mAdc)
IOL , DRAIN CURRENT (mAdc)

2.0 a 8.0 VGS = 10 Vdc
b
a TA = 55C
b TA = + 25C
4.0 6.0 c
b TA = + 125C
a TA = 55C
c b TA = + 25C
6.0 4.0 c TA = + 125C
10 Vdc b c b 15 Vdc a
8.0 2.0 b 5.0 Vdc
c
a a
10 0
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10

VDD
0
0 VT VT+ VDD
VH
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200
MC14094B
8-Stage Shift/Store Register

with Three-State Outputs
The MC14094B combines an 8stage shift register with a data latch
for each stage and a threestate output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in http://onsemi.com
highspeed cascaded systems. The QS output data is shifted on the
following negative clock transition for use in lowspeed cascaded MARKING
systems. DIAGRAMS
16
Data from each stage of the shift register is latched on the negative
PDIP16
transition of the strobe input. Data propagates through the latch while P SUFFIX MC14094BCP
strobe is high. CASE 648 AWLYYWW
Outputs of the eight data latches are controlled by threestate 1
buffers which are placed in the highimpedance state by a logic Low
on Output Enable. 16
ThreeState Outputs SOIC16
14094B
Capable of Driving Two LowPower TTL Loads or One LowPower
D SUFFIX AWLYWW
CASE 751B
Input Diode Protection 16
Data Latch
TSSOP16 14
Dual Outputs for Data Out on Both Positive and DT SUFFIX 094B
Negative Clock Transitions CASE 948F ALYW
Useful for SerialtoParallel Data Conversion 1
PinforPin Compatible with CD4094B 16
SOEIAJ16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) F SUFFIX MC14094B
CASE 966 AWLYWW

(DC or Transient)
WL or L = Wafer Lot

(8Second Soldering)
may occur.
3. Temperature Derating: MC14094BDT TSSOP16 96/Rail
applications of any voltage higher than maximum rated voltages to this 1. For ordering information on the EIAJ version of the
highimpedance circuit. For proper operation, Vin and Vout should be constrained SOIC packages, please contact your local ON
to the range VSS v (Vin or Vout) vVDD. Semiconductor representative.

MC14094B
PIN ASSIGNMENT
STROBE 1 16 VDD
DATA 2 15 OUTPUT
ENABLE
CLOCK 3 14 Q5
Q1 4 13 Q6
Q2 5 12 Q7
Q3 6 11 Q8
Q4 7 10 QS
VSS 8 9 QS
Parallel Outputs Serial Outputs

Output
Clock Enable Strobe Data Q1 QN QS * QS
0 X X Z Z Q7 No Chg.
0 X X Z Z No Chg. Q7
1 0 X No Chg. No Chg. Q7 No Chg.
1 1 0 0 QN1 Q7 No Chg.
1 1 1 1 QN1 Q7 No Chg.
1 1 1 No Chg. No Chg. No Chg. Q7
Z = High Impedance X = Dont Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.
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202
MC14094B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0
(Dynamic plus Quiescent, 10 IT = (14 A/kHz) f + IDD

Per Package) 15 IT = (140 A/kHz) f + IDD

buffers switching)

3State Output Leakage Current ITL 15 0.1 0.0001 0.1 3.0
A

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203
MC14094B

VDD

Typ (8.)

Characteristic Symbol Vdc Min Max Unit


tTHL 5.0
10
15

100
50
40
200
100
80


Clock to Serial out QS

tPLH,
tPHL
5.0 350 600
ns


tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
10
15

125
95
250
190

Clock to Serial out QS


10
15

110
75
220
150

Clock to Parallel out



Strobe to Parallel out

tPLH, tPHL = (0.36 ns/pF) C L + 127 ns 10 145 290


Output Enable to Output
tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns tPHZ, 5.0 140 280

tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns tPZL 10 75 150

tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns 15 55 110

tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns tPLZ, 5.0 225 450
tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns tPZH 10 95 190

tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns 15 70 140

Setup Time tsu 5.0 125 60 ns

Data in to Clock 10 55 30
15 35 20


Clock to Data 10 20 10
15 20 0

Clock Pulse Width, High

tWH 5.0
10
15
200
100
83
100
50
40

ns


tr(cl)
tf(cl)
5
10

15
5.0
s

15 4.0

10
15

5.0
6.0
2.5
3.0

Strobe Pulse Width tWL 5.0 200 100 ns
10 80 40

15 70 35
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204
MC14094B
3STATE TEST CIRCUIT

FOR tPHZ AND tPZH FOR tPLZ AND tPZL
VSS VDD
O.E.
1k
DATA
OUTPUT
ST
50 pF
CLOCK
BLOCK DIAGRAM
REGISTER STAGE 1 LATCH 1 3STATE BUFFER 1

CLOCK CLOCK STROBE VDD
2 *
SERIAL CLOCK CLOCK STROBE STROBE 4 Q1
DATA IN
CLOCK CLOCK STROBE
15 *
2 5 Q2
OUTPUT REGISTER STAGE 2 LATCH 2 3STATE BUFFER 2
ENABLE 3
REGISTER STAGE 3 LATCH 3 3STATE BUFFER 3 6 Q3
4 7 Q4
5 14 Q5
6 13 Q6
7 12 Q7
8 REGISTER STAGE 8 LATCH 8 3STATE BUFFER 8 11 Q8
CLOCK
CLOCK CLOCK STROBE STROBE
10 QS
3 * CLOCK
CLOCK CLOCK
CLOCK
CLOCK
1 STROBE *Input Protection Diodes

* CLOCK
STROBE 9 QS
STROBE
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205
MC14094B
DYNAMIC TIMING DIAGRAM
tWH
tr tf
90%
3 CLOCK 50% 50%
10%
tsu th
2 DATA IN
tWL
1 STROBE
15
OUTPUT 50% 50%
ENABLE
tPLH tPHL tPLH tPHZ tPZH tPLZ tPZL
N Q1 Q7 90% 90%
10%
90%
10%
90%
10% 10%
tTLH tTHL tPLH tPHL
9 QS 50% 50%
tPLH tPHL
10 QS 50% 50%
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206
MC14099B
8-Bit Addressable Latches

The MC14099B is an 8bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
http://onsemi.com
independently of the state of Write Disable, Write/Read or Chip
Enable. MARKING
A Master Reset capability is available on both parts. DIAGRAMS
Serial Data Input 16
Parallel Output PDIP16
MC14099BCP
P SUFFIX
Master Reset CASE 648 AWLYYWW
Capable of Driving Two Lowpower TTL Loads or One LowPower 16
Schottky TTL Load over the Rated Temperature Range
MC14099B pin for pin compatible with CD4099B SOIC16 14099B
DW SUFFIX
CASE 751G
AWLYYWW

F SUFFIX MC14099B
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V CASE 966 AWLYWW
(DC or Transient)
1
WW or W = Work Week
(8Second Soldering)
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14099BDW SOIC16 2350/Box
This device contains protection circuitry to guard against damage due to high MC14099BDWR2 SOIC16 1000/Tape & Reel
v v
to the range VSS (Vin or Vout) VDD.

MC14099B
PIN ASSIGNMENT
Q7 1 16 VDD
RESET 2 15 Q6
MC14099B
4 9
DATA 3 14 Q5 WRITE DISABLE Q0
DATA 3 10 Q1
WRITE 11
5 Q2
DISABLE 4 13 Q4 A0 8 8 12
Q3
6 13 Q4
A1 DECODER LATCHES 14
A0 5 12 Q3 A2 7
15
Q5
1 Q6
2 Q7
A1 6 11 Q2 RESET
VDD = 16
A2 7 10 Q1 VSS = 8
VSS 8 9 Q0

Characteristic

Symbol
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit

Output Voltage

Vin = VDD or 0

0 Level

VOL 5.0
10

0.05
0.05

0
0
0.05
0.05

0.05
0.05
Vdc

15 0.05 0 0.05 0.05

1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95

15 14.95 14.95 15 14.95


(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc

(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4



Input Capacitance Cin 15 22.5 pF

MC14599B Data (pin 3)
(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0


buffers switching)
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208
MC14099B

VDD





Propagation Delay Time tPHL, ns
Data to Output Q tPLH 5.0 200 400

10 75 150

15 50 100

Write Disable to Output Q 5.0 200 400 ns
10 80 160

15 60 120

Reset to Output Q 5.0 175 350 ns

10 80 160
15 65 130

CE to Output Q (MC14599B only)

5.0
10
15

225
100
75
450
200
150
ns

Propagation Delay Time, MC14599B only
Chip Enable, Write/Read to Data
tPHL,
tPLH 5.0 200 400
ns

10 80 160
15 65 130

Address to Data

5.0
10

200
90
400
180
ns

15 75 150

Pulse Widths tw(H) ns
Reset tw(L) 5.0 150 75

10
15
75
50
40
25

Write Disable 5.0 320 160 ns
10 160 80

15 120 60

Set Up Time tsu ns

Data to Write Disable 5.0 100 50
10 50 25

15 35 20

Hold Time th ns

Write Disable to Data 5.0 150 75
10 75 40

15 50 25

Set Up Time tsu 5.0 100 45 ns

Address to Write Disable 10 80 30
15 40 10
Removal Time

Write Disable to Address

trem 5.0
10
15
0
0
0
80
40
40

ns
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209
MC14099B
MC14099B
FUNCTION DIAGRAM
RESET 2
9 Q0
DATA 3
WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES ZERO
SELECT
10 Q1
A0 5
11 Q2
12 Q3
ADDRESS OTHER LATCHES 13 Q4
A1 6
DECODER
14 Q5
15 Q6
A2 7
(M.S.B.) 1 Q7
TRUTH TABLE
Write Addressed Unaddressed
Disable Reset Latch Latches
0 0 Data Qn* CAUTION: To avoid unintentional data changes in the latches, Write
0 1 Data Reset { Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
1 0 Qn* Qn*
1 1 Reset Reset
*Qn is previous state of latch.
Reset to zero state.
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210
MC14099B
SWITCHING WAVEFORMS
VDD
DATA OR
50%
WRITE DISABLE
VSS
tPLH tPHL
VDD
90% 50%
ADDRESS
50%
OUTPUT Q VSS
10%
tsu tw(L) trem
tTLH tTHL VDD
WRITE
50%
DISABLE
VSS
tw(H) tsu th
VDD VDD
RESET 50% DATA 50%
VSS VSS
tPHL
OUTPUT Q
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211
MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS
dissipation and/or high noise immunity is desired. The MC14106B
may be used in place of the MC14069UB hex inverter for enhanced
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noise immunity or to square up slowly changing waveforms.
Increased Hysteresis Voltage Over the MC14584B MARKING
PDIP14
Schottky TTL Load Over the Rated Temperature Range MC14106BCP
P SUFFIX
PinforPin Replacement for CD40106B and MM74C14 CASE 646 AWLYYWW
Can Be Used to Replace the MC14584B or MC14069UB 1
14
SOIC14
14106B
D SUFFIX AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) CASE 751A
1
14
TSSOP14 14
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V DT SUFFIX 106B
(DC or Transient) CASE 948G ALYW
TA Ambient Temperature Range 55 to +125 C WW or W = Work Week

(8Second Soldering)
applications of any voltage higher than maximum rated voltages to this MC14106BDT TSSOP14 96/Rail
to the range VSS v (Vin or Vout) vVDD. MC14106BDTR2 TSSOP14 2500/Tape & Reel

MC14106B
LOGIC DIAGRAM
1 2
3 4
5 6
9 8
11 10
13 12
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC

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213
MC14106B

VDD
55_C 25_C 125_C



Vin = VDD 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

Hysteresis Voltage VH (6.) 5.0 0.3 2.0 0.3 1.1 2.0 0.3 2.0 Vdc
10 1.2 3.4 1.2 1.7 3.4 1.2 3.4

15 1.6 5.0 1.6 2.1 5.0 1.6 5.0

Threshold Voltage

PositiveGoing VT+ 5.0 2.2 3.6 2.2 2.9 3.6 2.2 3.6 Vdc
10 4.6 7.1 4.6 5.9 7.1 4.6 7.1

15 6.8 10.8 6.8 8.8 10.8 6.8 10.8

NegativeGoing VT 5.0 0.9 2.8 0.9 1.9 2.8 0.9 2.8 Vdc

10 2.5 5.2 2.5 3.9 5.2 2.5 5.2
15 4.0 7.4 4.0 5.8 7.4 4.0 7.4


(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)

Source
IOH
5.0
5.0
3.0
0.64

2.4
0.51
4.2
0.88

1.7
0.36

mAdc

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

10
15
1.6
4.2

1.3
3.4
2.25
8.8

0.9
2.4

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

Input Current

(VOL = 1.5 Vdc)

Iin
15
15
4.2

0.1
3.4

8.8
0.00001

0.1
2.4

1.0 Adc

(Vin = 0)
Input Capacitance

Cin 5.0 7.5 pF

Quiescent Current IDD 5.0 0.25 0.0005 0.25 7.5 Adc
(Per Package) 10 0.5 0.0010 0.5 15

15 1.0 0.0015 1.0 30


Per Package)

IT 5.0
10
15
Adc

buffers switching)


where IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.
6. VH = VT+ VT (But maximum variation of VH is specified as less that VT+ max VT min).
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214
MC14106B

VDD

Typ (7.)

Characteristic Symbol Vdc Min Max Unit

10
15

50
40
100
80

10 50 100

15 40 80

Propagation Delay Time tPLH, tPHL 5.0 125 250 ns
10 50 100

15
40 80
VDD 20 ns 20 ns
14
INPUT VDD
PULSE OUTPUT 90%
50%
GENERATOR INPUT 10% VSS
7 VSS CL tPHL tPLH
90% VOH
OUTPUT 50%
10%
VOL
tf tr
VDD
0
0 VT VT+ VDD
VH
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215
MC14106B
APPLICATIONS
Vin Vout
VH VDD VH VDD
Vin Vin
VSS VSS
VDD VDD
Vout Vout
VSS VSS
(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
inputs with slow rise and fall times. noise immunity in gate applications.
Figure 3.
VDD VDD
R
tw C
tw
Rs Rs
Vout Vout
C R
VDD
tw = RC IN
VT+
Useful as Pushbutton/Keyboard Debounce Circuit.
Figure 4. Monostable Multivibrator
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216
MC14106B
1
f
R A
Vin Vout
R t1
C
t2
VDD
Vin VT+
VSS
C
[ RC ln VTT)
V
* t1 VDD
VT+
A

[ RC ln VVDDDD VTT)
V VSS
* t2
VT )
[ RC ln VDD VT VDD
1
Vout VT+
f VDD VT ) VT
VSS
*t1 + t2 & tPHL + tPLH Useful in discriminating against short pulse durations.
Figure 5. Astable Multivibrator Figure 6. Integrator
C
Vin
Vin
R + EDGE
EDGE C C C
EDGE + EDGE
VDD Vin
tw R R R
VDD
tw = RC ln
VT+
Useful as an edge detector circuit.
Figure 7. Differentiator Figure 8. Positive Edge Time Delay Circuit
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217
MC14174B
Hex Type D Flip-Flop

The MC14174B hex type D flipflop is constructed with MOS
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flipflops share common clock and reset inputs.
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The reset is active low, and independent of the clock.
Static Operation MARKING
All Inputs and Outputs Buffered DIAGRAMS

PDIP16
P SUFFIX MC14174BCP
Capable of Driving Two LowPower TTL Loads or One LowPower CASE 648 AWLYYWW
Schottky TTL Load over the Rated Temperature Range 1
Functional Equivalent to TTL 74174
16
SOIC16
14174B
D SUFFIX AWLYWW
CASE 751B
16
SOEIAJ16
F SUFFIX MC14174B
CASE 966 AWLYWW
(DC or Transient)
WW or W = Work Week
(8Second Soldering)

MC14174B
PIN ASSIGNMENT
R 1 16 VDD
Q0 2 15 Q5
D0 3 14 D5
D1 4 13 D4
Q1 5 12 Q4
D2 6 11 D3
Q2 7 10 Q3
VSS 8 9 C
BLOCK DIAGRAM
9 CLOCK Q0 2
1 RESET
Q1 5
3 D0
4 Q2 7
D1
6 D2 Q3 10
11 D3
Q4 12
13 D4
14 D5 Q5 15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
(Positive Logic)
Inputs Output
Clock Data Reset Q
0 1 0
1 1 1
No
X 1 Q
Change
X X 0 0
X = Dont Care
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219
MC14174B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0


buffers switching)
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220
MC14174B

VDD All Types





Propagation Delay Time Clock to Q tPLH, tPHL ns


Propagation Delay Time Reset to Q

tPHL
5.0 250 500
ns

tPHL = (0.36 ns/pF) CL + 79 ns 10 100 200
tPHL = (0.26 ns/pF) CL + 62 ns 15 75 150

Clock Pulse Width

tWH 5.0
10
15
150
90
70
75
45
35

ns

Reset Pulse Width

tWL 5.0
10
200
100
100
50

ns

15 80 40
Clock Pulse Frequency fcl 5.0 7.0 2.0 mHz

10
15

12
15.5
5.0
6.5

Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 15 ms
10 5.0

15 4.0

Data Setup Time tsu 5.0 40 20 ns
10 20 10

Data Hold Time

th
15
5.0
15
80
0
40

ns

10 40 20
15 30 15

Reset Removal Time

trem 5.0
10
15
250
100
80
125
50
40

ns
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221
MC14174B
TIMING DIAGRAM
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222
MC14175B
Quad Type D Flip-Flop

The MC14175B quad type D flipflop is constructed with MOS
monolithic structure. Each of the four flipflops is positiveedge
triggered by a common clock input (C). An activelow reset input (R)
asynchronously resets all flipflops. Each flipflop has independent
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Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flipflops for
MARKING
counter and toggle applications.
DIAGRAMS
Complementary Outputs 16
Static Operation PDIP16
MC14175BCP
All Inputs and Outputs Buffered P SUFFIX
CASE 648 AWLYYWW
16
Output Compatible with Two LowPower TTL Loads or One
SOIC16
LowPower Schottky TTL Load 14175B
D SUFFIX AWLYWW
Functional Equivalent to TTL 74175 CASE 751B
1
16

F SUFFIX MC14175B

(DC or Transient)
WL or L = Wafer Lot

(8Second Soldering) MC14175BD SOIC16 48/Rail
may occur.
static voltages or electric fields. However, precautions must be taken to avoid 1. For ordering information on the EIAJ version of
applications of any voltage higher than maximum rated voltages to this the SOIC packages, please contact your local
highimpedance circuit. For proper operation, Vin and Vout should be constrained ON Semiconductor representative.

MC14175B
PIN ASSIGNMENT
R 1 16 VDD
Q0 2 15 Q3
Q0 3 14 Q3
D0 4 13 D3
D1 5 12 D2
Q1 6 11 Q2
Q1 7 10 Q2
VSS 8 9 C
BLOCK DIAGRAM
9 CLOCK Q0 2
Q0 3
1 RESET
Q1 7
4 D0 Q1 6
5 D1 Q2 10
Q2 11
12 D2
Q3 15
13 D3 Q3 14
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs Outputs
Clock Data Reset Q Q
0 1 0 1
1 1 1 0
No
X 1 Q Q
Change
X X 0 0 1
X = Dont Care
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224
MC14175B

VDD
55_C 25_C 125_C



Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = 0 or VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36

(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

Sink IOL 5.0
10
0.64
1.6

0.51
1.3
0.88
2.25

0.36
0.9

mAdc

(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
0.1 0.00001 0.1 1.0 Adc


(Vin = 0)

Quiescent Current

(Per Package)

IDD 5.0
10

5.0
10

0.005
0.010
5.0
10

150
300
Adc

15 20 0.015 20 600

IT 5.0


buffers switching)
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225
MC14175B

VDD All Types





Propagation Delay Time Clock to Q, Q tPLH, tPHL ns


Propagation Delay Time Reset to Q, Q

tPHL, tPLH
5.0 325 500
ns

tPHL = (0.36 ns/pF) CL + 112 ns 10 130 200
tPHL = (0.26 ns/pF) CL + 87 ns 15 100 150

Clock Pulse Width

tWH 5.0
10
15
250
100
75
110
45
35

ns

Reset Pulse Width

tWL 5.0
10
200
80
100
40

ns

15 60 30
Clock Pulse Frequency fcl 5.0 4.5 2.0 mHz

10
15

11
14
5.0
6.5

Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 15 ms
10 5.0

15 4.0

Data Setup Time tsu 5.0 120 60 ns
10 50 25

Data Hold Time

th
15
5.0
40
80
20
40

ns

10 40 20
15 30 15

Reset Removal Time

trem 5.0
10
15
250
100
80
125
50
40

ns
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226
MC14175B
TIMING DIAGRAM
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227
MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS
enhancement mode devices, and is used for the elimination of
extraneous level changes that result when interfacing with mechanical
contacts. The digital contact bounce eliminator circuit takes an input http://onsemi.com
signal from a bouncing contact and generates a clean digital signal
four clock periods after the input has stabilized. The bounce eliminator MARKING
circuit will remove bounce on both the make and the break of a DIAGRAMS
contact closure. The clock for operation of the MC14490 is derived 16
from an internal RC oscillator which requires only an external PDIP16
P SUFFIX MC14490P
capacitor to adjust for the desired operating frequency (bounce delay). AWLYYWW
CASE 648
The clock may also be driven from an external clock source or the
1
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after powerup, the outputs of the MC14490 16
are in indeterminate states. 14490
SOIC16
Diode Protection on All Inputs DW SUFFIX
Six Debouncers Per Package
CASE 751G
AWLYYWW
Internal Pullups on All Data Inputs 1
Can Be Used as a Digital Integrator, System Synchronizer, or Delay 16
Line SOEIAJ16
Internal Oscillator (RC), or External Clock Source F SUFFIX MC14490
AWLYWW
TTL Compatible Data Inputs/Outputs CASE 966
Single Line Input, Debounces Both Make and Break Contacts 1
Does Not Require Form C (Single Pole Double Throw) Input A = Assembly Location
WL or L = Wafer Lot
Signal YY or Y = Year
Cascadable for Longer Time Delays WW or W = Work Week
Schmitt Trigger on Clock Input (Pin 7)
Supply Voltage Range = 3.0 V to 18 V ORDERING INFORMATION
Chip Complexity: 546 FETs or 136.5 Equivalent Gates Device Package Shipping
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) MC14490DW SOIC16 47/Rail
Symbol Parameter Value Unit MC14490DWR2 SOIC16 1000/Tape & Reel

VDD DC Supply Voltage Range 0.5 to +18.0 V MC14490F SOEIAJ16 See Note 1.
MC14490FEL SOEIAJ16 See Note 1.
(DC or Transient)
Iin Input Current 10 mA MC14490P PDIP16 25/Rail
(DC or Transient) per Pin 1. For ordering information on the EIAJ version of
PD Power Dissipation, 500 mW the SOIC packages, please contact your local
TA Ambient Temperature Range 55 to +125 C This device contains protection circuitry to guard
against damage due to high static voltages or electric
Tstg Storage Temperature Range 65 to +150 C fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this highimpedance circuit. For proper
(8Second Soldering)
operation, Vin and Vout should be constrained to the
2. Maximum Ratings are those values beyond which damage to the device range VSS v v
(Vin or Vout) VDD.
may occur. Unused inputs must always be tied to an appropriate
3. Temperature Derating: logic voltage level (e.g., either VSS or VDD). Unused out-
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C puts must be left open.

March, 2000 Rev. 3 MC14490/D
MC14490
PIN ASSIGNMENT
Ain 1 16 VDD
Bout 2 15 Aout
Cin 3 14 Bin
Dout 4 13 Cout
Ein 5 12 Din
Fout 6 11 Eout
OSCin 7 10 Fin
VSS 8 9 OSCout
BLOCK DIAGRAM
+VDD
DATA 15 Aout
1/2BIT
Ain 1 4BIT STATIC SHIFT REGISTER
DELAY
SHIFT LOAD
OSCILLATOR VDD = PIN 16

OSCin 7 1 1 2
AND 1 2 VSS = PIN 8
TWOPHASE
OSCout 9 CLOCK GENERATOR 2
1 2
Bin 14 IDENTICAL TO ABOVE STAGE 2 Bout
1 2
Cin 3 IDENTICAL TO ABOVE STAGE 13 Cout
1 2
Din 12 IDENTICAL TO ABOVE STAGE 4 Dout
1 2
Ein 5 IDENTICAL TO ABOVE STAGE 11 Eout
1 2
Fin 10 IDENTICAL TO ABOVE STAGE 6 Fout
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229
MC14490

VDD 55_C 25_C 125_C


Vin = VDD or 0 10 0.05 0 0.05 0.05

15 0.05 0 0.05 0.05

1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc

Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95

Input Voltage

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)

0 Level

VIL
5.0
10

1.5
3.0

2.25
4.50
1.5
3.0

1.5
3.0
Vdc

(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0


(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11


(VOH = 2.5 V)

Oscillator Output

Source
IOH
5.0 0.6 0.5 1.5 0.4

mAdc

(VOH = 4.6 V)

(VOH = 9.5 V)
(VOH = 13.5 V)

5.0
10
15
0.12
0.23
1.4

0.1
0.2
1.2
0.3
0.8
3.0

0.08
0.16
1.0

Debounce Outputs

(VOH = 2.5 V)

5.0 0.9 0.75 2.2 0.6

(VOH = 4.6 V) 5.0 0.19 0.16 0.46 0.12
(VOH = 9.5 V) 10 0.6 0.5 1.2 0.4

(VOH = 13.5 V) 15 1.8 1.5 4.5 1.2

Oscillator Output Sink IOL mAdc
(VOL = 0.4 V) 5.0 0.36 0.3 0.9 0.24

(VOL = 0.5 V) 10 0.9 0.75 2.3 0.6

(VOL = 1.5 V) 15 4.2 3.5 10 2.8

Debounce Outputs
(VOL = 0.4 V) 5.0 2.6 2.2 4.0 1.8

(VOL = 0.5 V) 10 4.0 3.3 9.0 2.7
(VOL = 1.5 V) 15 12 10 35 8.1

Input Current

Debounce Inputs (Vin = VDD)
IIH 15 2.0 0.2 2.0 11 Adc

Input Current Oscillator Pin 7 Iin 15 620 255 400 250 Adc

(Vin = VSS or VDD)
Pullup Resistor Source Current IIL 5.0 175 375 140 190 255 70 225 Adc

(Vin = VSS)

Debounce Inputs

10
15
340
505
740
1100
280
415
380
570
500
750
145
215
440
660

Adc

Quiescent Current ISS 5.0 150 40 100 90
(Vin = VSS or VDD, Iout = 0 A) 10 280 90 225 180

15 840 225 650 550
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230
MC14490


VDD


All Outputs

10
15

90
65
180
130

Output Fall Time Oscillator Output 5.0 100 200 ns
tTHL 10 50 100

15 40 80
Debounce Outputs tTHL 5.0 60 120

10 30 60

Oscillator Input to Debounce Outputs
tPHL
15
5.0

20
285
40
570 ns

10 120 240
15 95 190
tPLH 5.0 370 740

10 160 320
15 120 240
Clock Frequency (50% Duly Cycle) fcl 5.0 2.8 1.4 MHz

(External Clock) 10 6 3.0
15 9 4.5
Setup Time (See Figure 1)

tsu 5.0 100 50 ns

10 80 40
15 60 30
Maximum External Clock Input tr, tf 5.0 ns

Rise and Fall Time
Oscillator Input

10
15
No Limit

Oscillator Frequency fosc, typ Hz
OSCout 5.0

Cext 100 pF*
10

Note: These equations are intended to be a design guide.

Laboratory experimentation may be required. Formulas 15
are typically 15% of actual frequencies.
*POWERDOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turnoff time of the power supply must not be faster than t = (VDD VSS) Cext / (10 mA). For example, If VDD VSS = 15
V and Cext = 1 F, the power supply must turn off no faster than t = (15 V) (1 F) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this
possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
VDD
OSCin 50%
0V
tPLH
50% 90% D1 Cext D2
Aout
10% VDD VDD
tr
tPHL 7 9
90% 50% OSCin OSCout
Aout
10%
tf
VDD
OSCin 50% MC14490
0V
tsu
Ain 50% VDD
0V
Figure 1. Switching Waveforms Figure 2. Discharge Protection During Power Down
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MC14490
THEORY OF OPERATION
The MC14490 Hex Contact Bounce Eliminator is After some time period of N clock periods, the contact is
basically a digital integrator. The circuit can integrate both opened and at N +1 a low is loaded into the first bit. Just after
up and down. This enables the circuit to eliminate bounce on N+1, when the input bounces low, all bits are set to a high.
both the leading and trailing edges of the signal, shown in the At N +2 nothing happens because the input and output are
timing diagram of Figure 3. low and all bits of the shift register are high. At time N +3
Each of the six Bounce Eliminators is composed of a and thereafter the input signal is a high, clean signal. At the
41/2bit register (the integrator) and logic to compare the positive edge of N +6 the output goes high as a result of four
input with the contents of the shift register, as shown in lows being shifted into the shift register.
Figure 4. The shift register requires a series of timing pulses Assuming the input signal is long enough to be clocked
in order to shift the input signal into each shift register through the Bounce Eliminator, the output signal will be no
location. These timing pulses (the clock signal) are longer or shorter than the clean input signal plus or minus
represented in the upper waveform of Figure 3. Each of the one clock period.
six Bounce Eliminator circuits has an internal resistor as The amount of time distortion between the input and
shown in Figure 4. A pullup resistor was incorporated rather output signals is a function of the difference in bounce
than a pulldown resistor in order to implement switched characteristics on the edges of the input signal and the clock
ground input signals, such as those coming from relay frequency. Since most relay contacts have more bounce
contacts and push buttons. By switching ground, rather than when making as compared to breaking, the overall delay,
a power supply lead, system faults (such as shorts to ground counting bounce period, will be greater on the leading edge
on the signal input leads) will not cause excessive currents of the input signal than on the trailing edge. Thus, the output
in the wiring and contacts. Signal lead shorts to ground are signal will be shorter than the input signal if the leading
much more probable than shorts to a power supply lead. edge bounce is included in the overall timing calculation.
When the relay contact is closed, (see Figure 4) the low The only requirement on the clock frequency in order to
level is inverted, and the shift register is loaded with a high obtain a bounce free output signal is that four clock periods
on each positive edge of the clock signal. To understand the do not occur while the input signal is in a false state.
operation, we assume all bits of the shift register are loaded Referring to Figure 3, a false state is seen to occur three times
with lows and the output is at a high level. at the beginning of the input signal. The input signal goes
At clock edge 1 (Figure 3) the input has gone low and a low three times before it finally settles down to a valid low
high has been loaded into the first bit or storage location of state. The first three low pulses are referred to as false states.
the shift register. Just after the positive edge of clock 1, the If the user has an available clock signal of the proper
input signal has bounced back to a high. This causes the shift frequency, it may be used by connecting it to the oscillator
register to be reset to lows in all four bits thus starting the input (pin 7). However, if an external clock is not available
timing sequence over again. the user can place a small capacitor across the oscillator
During clock edges 3 to 6 the input signal has stayed low. input and output pins in order to start up an internal clock
Thus, a high has been shifted into all four shift register bits source (as shown in Figure 4). The clock signal at the
and, as shown, the output goes low during the positive edge oscillator output pin may then be used to clock other
of clock pulse 6. MC14490 Bounce Eliminator packages. With the use of the
It should be noted that there is a 31/2 to 41/2 clock MC14490, a large number of signals can be cleaned up, with
period delay between the clean input signal and output the requirement of only one small capacitor external to the
signal. In this example there is a delay of 3.8 clock periods Hex Bounce Eliminator packages.
from the beginning of the clean input signal.
1 2 3 4 5 6 N+1 N+3 N+5 N+7

OSCin OR OSCout
INPUT
OUTPUT
CONTACT CONTACT CLOSED CONTACT OPEN

OPEN (VALID TRUE SIGNAL)
CONTACT CONTACT
BOUNCING BOUNCING
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232
MC14490
+VDD
PULLUP RESISTOR
(INTERNAL) DATA
Ain 1/2 BIT 15
1 4BIT STATIC SHIFT REGISTER Aout
DELAY
FORM A SHIFT LOAD
CONTACT
OSCin 7 OSCILLATOR 1 2
1 1 2
AND
Cext 9 TWOPHASE
CLOCK GENERATOR 2
OSCout
Figure 4. Typical Form A Contact Debounce Circuit

(Only One Debouncer Shown)
OPERATING CHARACTERISTICS
The single most important characteristic of the MC14490 paralleled standard gates or by the MC14049 or MC14050
is that it works with a single signal lead as an input, making buffers.
it directly compatible with mechanical contacts (Form A The clock input circuit (pin 7) has Schmitt trigger shaping
and B). such that proper clocking will occur even with very slow
The circuit has a builtin pullup resistor on each input. clock edges, eliminating any need for clock preshaping. In
The worst case value of the pullup resistor (determined from addition, other MC14490 oscillator inputs can be driven
the Electrical Characteristics table) is used to calculate the from a single oscillator output buffered by an MC14050 (see
contact wetting current. If more contact current is required, Figure 5). Up to six MC14490s may be driven by a single
an external resistor may be connected between VDD and the buffer.
input. The MC14490 is TTL compatible on both the inputs and
Because of the builtin pullup resistors, the inputs cannot the outputs. When VDD is at 4.5 V, the buffered outputs can
be driven with a single standard CMOS gate when VDD is sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as
below 5 V. At this voltage, the input should be driven with a result of the internal input pullup resistors.
NO CONNECTION
OSCin 7 9 OSCout
Cext 1/6 MC14050
FROM TO SYSTEM
MC14490
OSCin 7 9 OSCout CONTACTS LOGIC
TO SYSTEM
FROM CONTACTS MC14490 NO CONNECTION
LOGIC
OSCin 7 9 OSCout
TO SYSTEM
FROM CONTACTS MC14490
LOGIC
Figure 5. Typical Single Oscillator Debounce System
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MC14490
ASYMMETRICAL TIMING MULTIPLE TIMING SIGNALS

In applications where different leading and trailing edge As shown in Figure 8, the Bounce Eliminator circuits can
delays are required (such as a fast attack/slow release timer.) be connected in series. In this configuration each output is
Clocks of different frequencies can be gated into the delayed by four clock periods relative to its respective input.
MC14490 as shown in Figure 6. In order to produce a slow This configuration may be used to generate multiple timing
attack/fast release circuit leads A and B should be signals such as a delay line, for programming other timing
interchanged. The clock out lead can then be used to feed operations.
clock signals to the other MC14490 packages where the One application of the above is shown in Figure 9, where
asymmetrical input/output timing is required. it is required to have a single pulse output for a single
operation (make) of the push button or relay contact. This
IN OUT only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in order
MC14490 OSCout
to generate the signal AB as shown in Figures 9 and 10. The
OSCin signal AB is four clock periods in length. If the inverter is
switched to the A output, the pulse AB will be generated
upon release or break of the contact. With the use of a few
MC14011B additional parts many different pulses and waveshapes may
be generated.
1 15
B.E. 1 Aout
A B Ain
EXTERNAL fC
N fC/N
CLOCK 14 2
B.E. 2 Bout
Bin
Figure 6. Fast Attack/Slow Release Circuit
3 13
B.E. 3 Cout
LATCHED OUTPUT Cin
The contents of the Bounce Eliminator can be latched by
using several extra gates as shown in Figure 7. If the latch
12 4
lead is high the clock will be stopped when the output goes B.E. 4 Dout
low. This will hold the output low even though the input has Din
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock 5 11
periods earlier. B.E. 5 Eout
Ein
IN OUT
10 6
B.E. 6 Fout
MC14490 Fin
OSCin
OSCout
MC14011B
7 9
CLOCK OSCin CLOCK OSCout
LATCH = 1
UNLATCH = 0 Figure 8. Multiple Timing Circuit Connections
Figure 7. Latched Output Circuit
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MC14490
IN OUT
BE 1
A A
AB
IN OUT B
BE 2
B
A ACTIVE LOW
B ACTIVE LOW
Figure 9. Single Pulse Output Circuit
OSCin OR
OSCout
INPUT
AB
AB
Figure 10. Multiple Output Signal Timing Diagram
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235
MC14503B
Hex Non-Inverting 3-State

Buffer
The MC14503B is a hex noninverting buffer with 3state outputs,
and a high current source and sink capability. The 3state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of http://onsemi.com
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into a MARKING
high impedance state. DIAGRAMS
3State Outputs PDIP16
16
TTL Compatible Will Drive One TTL Load Over Full P SUFFIX MC14503BCP
CASE 648 AWLYYWW
Temperature Range
Two Disable Controls for Added Versatility 16

Pin for Pin Replacement for MM80C97 and 340097 SOIC16
14503B
D SUFFIX AWLYWW
CASE 751B
1

F SUFFIX MC14503B
CASE 966
(DC or Transient) 1
Iin Input Current 10 mA A = Assembly Location

YY or Y = Year
Iout Output Current 25 mA WW or W = Work Week
(8Second Soldering) MC14503BD SOIC16 48/Rail
may occur.
3. Temperature Derating: MC14503BF SOEIAJ16 See Note 1.
static voltages or electric fields. However, precautions must be taken to avoid 1. For ordering information on the EIAJ version of

MC14503B
PIN ASSIGNMENT
DIS A 1 16 VDD
IN 1 2 15 DIS B
OUT 1 3 14 IN 6
IN 2 4 13 OUT 6
OUT 2 5 12 IN 5
IN 3 6 11 OUT 5
OUT 3 7 10 IN 4
VSS 8 9 OUT 4
TRUTH TABLE LOGIC DIAGRAM

Appropriate 15
Disable DISABLE B
Inn Input Outn 12 11
IN 5 OUT 5
0 0 0
14 13
1 0 1 IN 6 OUT 6
X 1 High 2 3
Impedance IN 1 OUT 1
4 5
X = Dont Care IN 2 OUT 2
6 7
IN 3 OUT 3
10 9
IN 4 OUT 4
1
DISABLE A
VDD = PIN 16
VSS = PIN 8
CIRCUIT DIAGRAM
ONE OF TWO/FOUR BUFFERS
VDD
* INn OUTn
* DISABLE
* INPUT
VSS
TO OTHER BUFFERS
*Diode protection on all inputs (not shown)
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MC14503B

VDD
55_C 25_C 125_C



Vin = 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05

Vin = VDD

1 Level

VOH 5.0
10
4.95
9.95

4.95
9.95
5.0
10

4.95
9.95

Vdc

15 14.95 14.95 15 14.95

(VO = 3.6 or 1.4 Vdc) 5.0 1.5 2.25 1.5 1.5

(VO = 7.2 or 2.8 Vdc) 10 3.0 4.50 3.0 3.0

(VO = 11.5 or 3.5 Vdc) 15 4.0 6.75 4.0 4.0

1 Level VIH Vdc
(VO = 1.4 or 3.6 Vdc) 5.0 3.5 3.5 2.75 3.5

(VO = 2.8 or 7.2 Vdc) 10 7.0 7.0 5.50 7.0

(VO = 3.5 or 11.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 4.5 4.3 3.6 5.0 2.5

(VOH = 2.5 Vdc) 5.0 5.8 4.8 6.1 3.0

(VOH = 4.6 Vdc) 5.0 1.2 1.02 1.4 0.7
(VOH = 9.5 Vdc) 10 3.1 2.6 3.7 1.8

(VOH = 13.5 Vdc) 15 8.2 6.8 14.1 4.8


(VOL = 0.4 Vdc) 5.0 2.6 2.1 2.3 1.3
(VOL = 0.5 Vdc) 10 6.5 5.5 6.2 3.8

(VOL = 1.5 Vdc) 15 19.2 16.1 25 11.2



(Vin = 0)
Adc

Quiescent Current IQ 5.0 1.0 0.002 1.0 30
(Per Package) 10 2.0 0.004 2.0 60

15 4.0 0.006 4.0 120


Per Package) 15 IT = (10 A/kHz) f + IDD

(CL = 50 pF on all outputs)

(All outputs switching,
50% Duty Cycle)

Current

ThreeState Output Leakage

ITL 15 0.1 0.0001 0.1 3.0
Adc
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MC14503B


All Types
VDD

Characteristic Symbol VCC Typ (8.) Max Unit


tTLH = (0.5 ns/pF) CL + 20 ns 5.0 45 90
tTLH = (0.3 ns/pF) CL + 8.0 ns 10 23 45

tTLH = (0.2 ns/pF) CL + 8.0 ns 15 18 35


tTHL = (0.5 ns/pF) CL + 20 ns 5.0 45 90
tTHL = (0.3 ns/pF) CL + 8.0 ns 10 23 45

tTHL = (0.2 ns/pF) CL + 8.0 ns 15 18 35

TurnOff Delay Time, all Outputs tPLH ns

tPLH = (0.3 ns/pF) CL + 60 ns 5.0 75 150
tPLH = (0.15 ns/pF) CL + 27 ns 10 35 70

tPLH = (0.1 ns/pF) CL + 20 ns 15 25 50

TurnOn Delay Time, all Outputs tPHL ns
tPHL = (0.3 ns/pF) CL + 60 ns 5.0 75 150


10
15
35
25
70
50

3State Propagation Delay Time tPHZ 5.0 75 150 ns
Output 1 to High Impedance 10 40 80

Output 0 to High Impedance tPLZ
15
5.0
35
80
70
160 ns

10 40 80
15 35 70

High Impedance to 1 Level

tPZH 5.0
10
65
25
130
50
ns

15 20 40

High Impedance to 0 Level tPZL 5.0 100 200 ns
10 35 70

15 25 50
DISABLE 20 ns 20 ns
INPUT VDD
VDD 90%
INPUT 50%
16 10%
VSS
INPUT tPLH tPHL
PULSE
OUTPUT VOH
GENERATOR 90%
OUTPUT 50%
VSS CL 10%
VOL
tTLH tTHL
tPLH tPHL

(tTLH, tTHL, tPHL, and tPLH)
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MC14503B
DISABLE INPUT DISABLE INPUT

PULSE PULSE tPLZ, tPZL CIRCUIT
GENERATOR GENERATOR
VDD VDD
tPHZ, tPZH CIRCUIT 16

16 1k
INPUT OUTPUT INPUT OUTPUT
1k CL
VSS CL
8 8 VSS
20 ns 20 ns
VDD
90%
50%
10%
DISABLE INPUT VSS
tPLZ tPZL
VOH
90%
10%
OUTPUT FOR tPZH, tPZL CIRCUIT VOL + 0.05 V
tPHZ tPZH
OUTPUT FOR tPHZ, tPLZ CIRCUIT 90% VOH 0.15 V
10%
VOL
Figure 2. 3State AC Test Circuit and Waveforms

(tPLZ, tPHZ, tPZH, tPZL)
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MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex noninverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to http://onsemi.com
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC. The MARKING
VCC level sets the input signal levels while VDD selects the output DIAGRAMS
voltage levels. 16
UP Translates from a Low to a High Voltage or DOWN Translates PDIP16

P SUFFIX MC14504BCP
from a High to a Low Voltage CASE 648 AWLYYWW
Input Threshold Can Be Shifted for TTL Compatibility 1
No Sequencing Required on Power Supplies or Inputs for Power Up
16
or Power Down SOIC16
3 to 18 Vdc Operation for VDD and VCC D SUFFIX
14504B
AWLYWW
Diode Protected Inputs to VSS CASE 751B
Capable of Driving Two LowPower TTL Loads or One LowPower

1
TSSOP16 14
DT SUFFIX 504B
CASE 948F ALYW
1
VCC DC Supply Voltage Range 0.5 to +18.0 V 16

F SUFFIX MC14504B
Vin Input Voltage Range 0.5 to +18.0 V CASE 966 AWLYWW
(DC or Transient)
1
Vout Output Voltage Range 0.5 to VDD + 0.5 V
(DC or Transient) A = Assembly Location
WL or L = Wafer Lot
(8Second Soldering)
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14504BDT TSSOP16 96/Rail
This device contains protection circuitry to guard against damage due to high MC14504BF SOEIAJ16 See Note 1.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., ON Semiconductor representative.

MC14504B
PIN ASSIGNMENT
VCC 1 16 VDD
Aout 2 15 Fout
Ain 3 14 Fin
Bout 4 13 MODE
Bin 5 12 Eout
Cout 6 11 Ein
Cin 7 10 Dout
VSS 8 9 Din
LOGIC DIAGRAM
VCC VDD
LEVEL
INPUT OUTPUT
SHIFTER
TTL/CMOS
MODE
MODE SELECT
Input Logic Output Logic

Mode Select Levels Levels
1 (VCC) TTL CMOS
0 (VSS) CMOS CMOS
1/6 of package shown.
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MC14504B

VCC VDD
55_C 25_C 125_C

Characteristic Symbol Vdc Vdc Min Max Min Typ (4.) Max Min Max Unit

Vin = 0 V

10

0.05

0.05

0.05

Vin = VCC

1 Level
VOH

15
5.0 4.95
0.05

4.95
0
5.0
0.05

4.95
0.05
Vdc

10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95

Input Voltage

0 Level

VIL Vdc

(VOL = 1.0 Vdc) TTLCMOS 5.0 10 0.8 1.3 0.8 0.8

(VOL = 1.5 Vdc) TTLCMOS 5.0 15 0.8 1.3 0.8 0.8
(VOL = 1.0 Vdc) CMOSCMOS 5.0 10 1.5 2.25 1.5 1.4

(VOL = 1.5 Vdc) CMOSCMOS 5.0 15 1.5 2.25 1.5 1.5
(VOL = 1.5 Vdc) CMOSCMOS 10 15 3.0 4.5 3.0 2.9

Input Voltage 1 Level VIH Vdc
(VOH = 9.0 Vdc) TTLCMOS 5.0 10 2.0 2.0 1.5 2.0

(VOH = 13.5 Vdc) TTLCMOS 5.0 15 2.0 2.0 1.5 2.0
(VOH = 9.0 Vdc) CMOSCMOS 5.0 10 3.6 3.5 2.75 3.5

(VOH = 13.5 Vdc) CMOSCMOS 5.0 15 3.6 3.5 2.75 3.5

(VOH = 13.5 Vdc) CMOSCMOS 10 15 7.1 7.0 5.5 7.0

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7

(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc)

Sink IOL

15
5.0
4.2
0.64

3.4
0.51
8.8
0.88

2.4
0.36

mAdc

(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4

Input Current

Iin 15 0.1 0.00001 0.1 1.0 Adc

Adc

Quiescent Current IDD or 5.0 0.05 0.0005 0.05 1.5
(Per Package) ICC 10 0.10 0.0010 0.10 3.0

CMOSCMOS Mode 15 0.20 0.0015 0.20 6.0

Quiescent Current IDD 5.0 5.0 0.5 0.0005 0.5 3.8 Adc
(Per Package) 5.0 10 1.0 0.0010 1.0 7.5

TTLCMOS Mode 5.0 15 2.0 0.0015 2.0 15

Quiescent Current ICC 5.0 5.0 5.0 2.5 5.0 6.0 mAdc

(Per Package) 5.0 10 5.0 2.5 5.0 6.0
TTLCMOS Mode 5.0 15 5.0 2.5 5.0 6.0
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MC14504B

VCC VDD Limits

Characteristic Symbol Shifting Mode Vdc Vdc Min Typ (5.) Max Unit
Propagation Delay, High to Low tPHL ns

TTL CMOS 5.0 10 140 280
VDD > VCC 5.0 15 140 280

CMOS CMOS 5.0 10 120 240

VDD > VCC 5.0 15 120 240
10 15 70 140

CMOS CMOS
VCC > VDD
10
15
15
5.0
5.0
10

185
185
175
370
370
350

Propagation Delay, Low to High

tPLH TTL CMOS
VDD > VCC
5.0
5.0
10
15

170
160
340
320
ns

CMOS CMOS 5.0 10 170 340
VDD > VCC 5.0 15 170 340

CMOS CMOS
10
10
15
5.0

100
275
200
550

VCC > VDD 15 5.0 275 550
15 10 145 290

Output Rise and Fall Time tTLH, tTHL ALL 5.0 100 200 ns

10 50 100
15 40 80
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MC14504B
7 7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)

6 6
VCC = 10 V
5 5
4 4
3 VCC = 5 V 3
2 2 VCC = 5 V
1 1
0 0
0 5 10 15 20 0 5 10 15 20
VDD, SUPPLY VOLTAGE (Vdc) VDD, SUPPLY VOLTAGE (Vdc)
Figure 1. Input Switchpoint CMOS to CMOS Mode Figure 2. Input Switchpoint TTL to CMOS Mode
20 20

15 15
VDD, SUPPLY VOLTAGE (Vdc)
VDD, SUPPLY VOLTAGE (Vdc)

10 10

5 5
0 0
0 5 10 15 20 0 5 10 15 20
VCC, SUPPLY VOLTAGE (Vdc) VCC, SUPPLY VOLTAGE (Vdc)
Figure 3. Operating Boundary CMOS to CMOS Mode Figure 4. Operating Boundary TTL to CMOS Mode
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MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCDtoseven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4bit storage latch, an 8421 http://onsemi.com
BCDtoseven segment decoder, and an output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the MARKING
display, to turnoff or pulse modulate the brightness of the display, and DIAGRAMS
16
to store a BCD code, respectively. It can be used with sevensegment PDIP16
lightemitting diodes (LED), incandescent, fluorescent, gas discharge, P SUFFIX MC14511BCP
AWLYYWW
or liquid crystal readouts either directly or indirectly. CASE 648
Applications include instrument (e.g., counter, DVM, etc.) display 1
driver, computer/calculator display driver, cockpit display driver, and 16
various clock, watch, and timer uses. SOIC16
14511B
Low Logic Circuit Power Dissipation D SUFFIX
CASE 751B
AWLYWW
HighCurrent Sourcing Outputs (Up to 25 mA) 1
Latch Storage of Code 16
Blanking Input
Lamp Test Provision SOIC16 14511B
DW SUFFIX
Readout Blanking on all Illegal Input Combinations CASE 751G
Lamp Intensity Modulation Capability AWLYYWW
Time Share (Multiplexing) Facility 1

Supply Voltage Range = 3.0 V to 18 V 16
Capable of Driving Two Lowpower TTL Loads, One Lowpower SOEIAJ16
Schottky TTL Load or Two HTL Loads Over the Rated Temperature F SUFFIX MC14511B
CASE 966 AWLYWW
Range
Chip Complexity: 216 FETs or 54 Equivalent Gates 1
Triple Diode Protection on all Inputs A = Assembly Location
WL or L = Wafer Lot
MAXIMUM RATINGS (Voltages Referenced to VSS) (2.) YY or Y = Year
Symbol Parameter Value Unit WW or W = Work Week

Vin Input Voltage Range, All Inputs 0.5 to VDD + 0.5 V ORDERING INFORMATION
I DC Current Drain per Input Pin 10 mA Device Package Shipping
per Package (3.)
TA Operating Temperature Range 55 to +125 C MC14511BD SOIC16 48/Rail
Tstg Storage Temperature Range 65 to +150 C MC14511BDW SOIC16 47/Rail
IOHmax Maximum Output Drive Current 25 mA MC14511BDWR2 SOIC16 1000/Tape & Reel
(Source) per Output
POHmax Maximum Continuous Output 50 mA
Power (Source) per Output (4.) MC14511BFEL SOEIAJ16 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device 1. For ordering information on the EIAJ version of
may occur. the SOIC packages, please contact your local
3. Temperature Derating: ON Semiconductor representative.
4. POHmax = IOH (VDD VOH)

MC14511B
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. A
destructive high current mode may occur if Vin and Vout are not constrained to the range VSS (Vin or Vout) VDD. v v
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a
logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
PIN ASSIGNMENT
B 1 16 VDD
C 2 15 f
LT 3 14 g a
f g b
BI 4 13 a
e c
LE 5 12 b
d
D 6 11 c
A 7 10 d
VSS 8 9 e
DISPLAY
0 1 2 3 4 5 6 7 8 9
TRUTH TABLE
Inputs Outputs
LE BI LT D C B A a b c d e f g Display
X X 0 X X X X 1 1 1 1 1 1 1 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
0 1 1 0 0 0 0 1 1 1 1 1 1 0 0
0 1 1 0 0 0 1 0 1 1 0 0 0 0 1
0 1 1 0 0 1 1 1 1 1 1 0 0 1 2
0 1 1 0 0 1 1 1 1 1 1 0 0 1 3
0 1 1 0 1 0 0 0 1 1 0 0 1 1 4
0 1 1 0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 1 0 0 0 1 1 1 1 1 6
0 1 1 0 1 1 1 1 1 1 0 0 0 0 7
0 1 1 1 0 0 0 1 1 1 1 1 1 1 8
0 1 1 1 0 0 1 1 1 1 0 0 1 1 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
1 1 1 X X X X * *
X = Dont Care
* Depends upon the BCD code previously applied when LE = 0
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247
MC14511B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (5.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.1 4.1 4.57 4.1 Vdc
Vin = 0 or VDD 10 9.1 9.1 9.58 9.1
15 14.1 14.1 14.59 14.1
Input Voltage # 0 Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 8.8 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.8 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 3.8 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 8.8 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.8 Vdc) 15 11 11 8.25 11
Output Drive Voltage VOH Vdc
(IOH = 0 mA) Source 5.0 4.1 4.1 4.57 4.1
(IOH = 5.0 mA) 4.24
(IOH = 10 mA) 3.9 3.9 4.12 3.5
(IOH = 15 mA) 3.94
(IOH = 20 mA) 3.4 3.4 3.70 3.0
(IOH = 25 mA) 3.54
(IOH = 0 mA) 10 9.1 9.1 9.58 9.1 Vdc
(IOH = 5.0 mA) 9.26
(IOH = 10 mA) 9.0 9.0 9.17 8.6
(IOH = 15 mA) 9.04
(IOH = 20 mA) 8.6 8.6 8.90 8.2
(IOH = 25 mA) 8.70
(IOH = 0 mA) 15 14.1 14.1 14.59 14.1 Vdc
(IOH = 5.0 mA) 14.27
(IOH = 10 mA) 14 14 14.18 13.6
(IOH = 15 mA) 14.07
(IOH = 20 mA) 13.6 13.6 13.95 13.2
(IOH = 25 mA) 13.70
Output Drive Current IOL mAdc
(VOL = 0.4 V) Sink 5.0 0.64 0.51 0.88 0.36
(VOL = 0.5 V) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 V) 15 4.2 3.4 8.8 2.4
(Per Package) Vin = 0 or VDD, 10 10 0.010 10 300
Iout = 0 A 15 20 0.015 20 600
buffers switching)
Noise Margin for both 1 and 0 level =
1.0 Vdc min @ VDD = 5.0 Vdc
IT(CL) = IT(50 pF) + 3.5 x 103 (CL 50) VDDf
where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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MC14511B
VDD
Vdc Min Typ Max Unit
tTLH = (0.40 ns/pF) CL + 20 ns 5.0 40 80
tTLH = (0.25 ns/pF) CL + 17.5 ns 10 30 60
tTLH = (0.20 ns/pF) CL + 15 ns 15 25 50
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 65 130
Data Propagation Delay Time tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 175 350
tPHL = (1.3 ns/pF) CL + 655 ns tPHL 5.0 720 1440
tPHL = (0.60 ns/pF) CL + 260 ns 10 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 200 400
Blank Propagation Delay Time tPLH ns

tPLH = (0.30 ns/pF) CL + 585 ns 5.0 600 750
tPLH = (0.25 ns/pF) CL + 187.5 ns I0 200 300
tPLH = (0.15 ns/pF) CL + 142.5 ns 15 150 220
tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 485 970

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 160 320
Lamp Test Propagation Delay Time tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 90 180
tPHL = (1.3 ns/pF) CL + 248 ns tPHL 5.0 313 625

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 90 180
Setup Time tsu 5.0 100 ns

10 40
15 30
Hold Time th 5.0 60 ns
10 40
15 30
Latch Enable Pulse Width tWL 5.0 520 260 ns
10 220 110
15 130 65
8. The formulas given are for the typical characteristics only.
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249
MC14511B
Input LE low, and Inputs D, BI and LT high.

f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
50%
ANY OUTPUT
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns 20 ns
90% VDD
INPUT C 50%
10%
VSS
tPLH tPHL
VOH
90%
OUTPUT g 50%
10% VOL
tTLH tTHL
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
20 ns
VDD
90%
50%
LE 10%
VSS
th
tsu
VDD
INPUT C 50%
VSS
VOH
OUTPUT g
VOL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
LE 50%
10% VSS
tWL
(c) Data DCBA strobed into latches.
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250
MC14511B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT

VDD VDD
COMMON
ANODE LED
COMMON 1.7 V
CATHODE LED
1.7 V
VSS
VSS
INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD
** DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
VSS
VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V)
GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)
1/4 OF MC14070B
VSS VSS
** A filament prewarm resistor is recommended to reduce filament Direct dc drive of LCDs not recommended for life of
thermal shock and increase the effective cold resistance of the LCD readouts.
filament.
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251
MC14511B
LOGIC DIAGRAM
BI 4
13 a
A 7
12 b
11 c
B 1
10 d
9 e
15 f
C 2
14 g
LT 3
D 6
VDD = PIN 16
LE 5 VSS = PIN 8
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252
MC14512B
8-Channel Data Selector

The MC14512B is an 8channel data selector constructed with
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
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sequence generation.
Single Supply Operation MARKING
DIAGRAMS
3State Output (Logic 1, Logic 0, High Impedance)
16
AWLYYWW
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOIC16
14512B
D SUFFIX AWLYWW
CASE 751B
(DC or Transient) per Pin F SUFFIX MC14512B
CASE 966 AWLYWW
per Package (Note 3.) 1
WL or L = Wafer Lot
TL Lead Temperature 260 C YY or Y = Year
(8Second Soldering) WW or W = Work Week
may occur.
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C ORDERING INFORMATION
This device contains protection circuitry to guard against damage due to high Device Package Shipping
applications of any voltage higher than maximum rated voltages to this MC14512BCP PDIP16 2000/Box
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14512BDR2 SOIC16 2500/Tape & Reel
MC14512BFL1 SOEIAJ16 See Note 1.


MC14512B
TRUTH TABLE
C B A Inhibit Disable Z
0 0 0 0 0 X0
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3
1 0 0 0 0 X4
1 0 1 0 0 X5
1 1 0 0 0 X6
1 1 1 0 0 X7
X X X 1 0 0
X X X X 1 High
Impedance
X = Dont Care
PIN ASSIGNMENT
X0 1 16 VDD
X1 2 15 DIS
X2 3 14 Z
X3 4 13 C
X4 5 12 B
X5 6 11 A
X6 7 10 INH
VSS 8 9 X7
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254
MC14512B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
ThreeState Leakage Current ITL 15 0.1 0.0001 0.1 3.0 Adc
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255
MC14512B
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C, See Figure 1)

All Types
Characteristic Symbol VDD Typ (8.) Max Unit
Propagation Delay Time (Figure 2) tPLH ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
Propagation Delay Time (Figure 2) tPHL ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
3State Output Delay Times (Figure 3) tPHZ, tPLZ, 5.0 60 150 ns
1 or 0 to High Z, and tPZH, tPZL 10 35 100
High Z to 1 or 0 15 30 75
ID VDD
DISABLE
INHIBIT Z
A CL
B
C
X0
X1
PULSE X2
Vin 50% GENERATOR
50% X3
DUTY X4
CYCLE X5
X6
X7
VSS
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256
MC14512B
VDD
20 ns 20 ns
90% VDD
DISABLE DATA 50%
INHIBIT Z 10% VSS
A tPLH tPHL
CL 90% VOH
B 50%
C Z 10%
VOL
X0 tTLH tTHL
PULSE X1
GENERATOR TEST CONDITIONS:
X2 INHIBIT = VSS
X3 A, B, C = VSS
X4
X5 20 ns 20 ns
X6 INHIBIT, VDD
90%
X7 A, B, OR C 50%
10% VSS
tPHL tPLH
VSS Parameter Test Conditions 90% VOH
50%
Inhibit to Z A, B, C = VSS, XO = VDD Z 10% VOL
A, B, C to Z Inh = VSS, XO = VDD tTHL tTLH
Figure 2. AC Test Circuit and Waveforms
VDD
PULSE 20 ns
VDD 20 ns
GENERATOR VDD
DISABLE 90%
VDD 50%
INHIBIT Z DISABLE 10%
CL VSS
A INPUT
B 1k S1 tPZL
S3 tPLZ
C VOH
90%
X0 S2 OUTPUT 10% VOL 2.5 V @ VDD = 5 V,
S4 X1 10 V, AND 15 V
tPHZ tPZH
X2 2 V @ VDD = 5 V
X3 VSS OUTPUT
90%
VOH 6 V @ VDD = 10 V
VSS X4 10% 10 V @ VDD = 15 V
VOL
X5
X6 Switch Positions for 3State Test
X7 Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
VSS
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
Figure 3. 3State AC Test Circuit and Waveform
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257
MC14512B
LOGIC DIAGRAM
13
C
12
B 15
11 DISABLE
A
1 10 DATA
X0 SELECTED
BUS
INHIBIT DEVICE
2 VDD IOD
X1
MC14512B
3 IL
X2
14 LOAD
Z ITL
4
X3 MC14512B
5
X4
ITL
6 MC14512B
X5
7 VSS
X6
9
X7 1 1
OUT
IN IN OUT
2 2
TRANSMISSION
GATE
3STATE MODE OF OPERATION
Output terminals of several MC14512B 8Bit Data (including fanout to other device inputs), and can be
Selectors can be connected to a single date bus as shown. calculated by:
One MC14512B is selected by the 3state control, and the IOD IL
remaining devices are disabled into a highimpedance off N= +1
ITL
state. The number of 8bit data selectors, N, that may be
connected to a bus line is determined from the output drive N must be calculated for both high and low logic state of the
current, IOD, 3state or disable output leakage current, ITL, bus line.
and the load current, IL, required to drive the bus line
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258
MC14513B
BCD-To-Seven Segment
Latch/Decoder/Driver
CMOS MSI
(LowPower Complementary MOS)
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constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4bit storage latch, an 8421
BCDtoseven segment decoder, and has output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turnoff or pulse modulate the brightness of the display, and
to store a BCD code, respectively. The Ripple Blanking Input (RBI) and
Ripple Blanking Output (RBO) can be used to suppress either leading
or trailing zeroes. It can be used with sevensegment light emitting MARKING
diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal DIAGRAMS
readouts either directly or indirectly. 18
PDIP18
Applications include instrument (e.g., counter, DVM, etc.) display MC14513BCP
P SUFFIX
driver, computer/calculator display driver, cockpit display driver, and AWLYYWW
CASE 707
various clock, watch, and timer uses. 1
Low Logic Circuit Power Dissipation
Highcurrent Sourcing Outputs (Up to 25 mA) A = Assembly Location
WL or L = Wafer Lot
Latch Storage of Binary Input YY or Y = Year
Blanking Input WW or W = Work Week
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Capability Device Package Shipping
Adds Ripple Blanking In, Ripple Blanking Out to MC14511B MC14513BCP PDIP18 20/Rail
Supply Voltage Range = 3.0 V to 18 V
This device contains protection circuitry to protect
Capable of Driving Two LowPower TTL Loads, One Lowpower the inputs against damage due to high static voltages
Schottky TTL Load to Two HTL Loads Over the Rated Temperature or electric fields. However, it is advised that normal
Range. precautions be taken to avoid application of any volt-
age higher than maximum rated voltages to this high
MAXIMUM RATINGS (Voltages Referenced to VSS) (1.) impedance circuit. A destructive high current mode
may occur if Vin and Vout are not constrained to the
v v
range VSS (Vin or Vout) VDD.
VDD DC Supply Voltage Range 0.5 to +18.0 V Due to the sourcing capability of this circuit, dam-
Vin Input Voltage Range, All Inputs 0.5 to VDD + 0.5 V age can occur to the device if VDD is applied, and the
outputs are shorted to VSS and are at a logical 1 (See
I DC Current Drain per Input Pin 10 mA Maximum Ratings).
PD Power Dissipation, 500 mW Unused inputs must always be tied to an appropri-
per Package (2.) ate logic voltage level (e.g., either VSS or VDD).

1. Maximum Ratings are those values beyond which
IOHmax Maximum Continuous Output 25 mA damage to the device may occur.
Drive Current (Source) per Output 2. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C
POHmax Maximum Continuous Output 50 mW From 65_C To 125_C
Power (Source) per Output (3.) 3. POHmax = IOH (VDD VOH)

MC14513B
PIN ASSIGNMENT
B 1 18 VDD
C 2 17 f
LT 3 16 g
a
BI 4 15 a f g b
LE 5 14 b e c
D 6 13 c d
A 7 12 d
RBI 8 11 e
VSS 9 10 RBO
DISPLAY
0 1 2 3 4 5 6 7 8 9
TRUTH TABLE
Inputs Outputs
RBI LE BI LT D C B A RBO a b c d e f g Display
X X X 0 X X X X + 1 1 1 1 1 1 1 8
X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank
0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0
X 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1
X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2
X 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 3
X 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 4
X 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 5
X 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 6
X 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 7
X 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 8
X 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 9
X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
X 1 1 1 X X X X * *
X = Dont Care
RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0
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2
MC14513B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage Segment Outputs VOL Vdc
0 Level 5.0 0.05 0 0.05 0.05
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.1 4.1 5.0 4.1 Vdc
Vin = 0 or VDD 10 9.1 9.1 10 9.1
15 14.1 14.1 15 14.1
Output Voltage RBO Output VOL Vdc
0 Level 5.0 0.05 0 0.05 0.05
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
Input Voltage (4.) 0 Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 8.8 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.8 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
(VO = 1.0 or 8.8 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.8 Vdc) 15 11 11 8.25 11
Output Drive Voltage Segments VOH Vdc

(IOH = 0 mA) Source 5.0 4.1 4.1 4.57 4.1
(IOH = 5.0 mA) 4.24
(IOH = 10 mA) 3.9 3.9 4.12 3.5
(IOH = 15 mA) 3.94
(IOH = 20 mA) 3.4 3.4 3.70 3.0
(IOH = 25 mA) 3.54
(IOH = 0 mA) 10 9.1 9.1 9.58 9.1 Vdc
(IOH = 5.0 mA) 9.26
(IOH = 10 mA) 9.0 9.0 9.17 8.6
(IOH = 15 mA) 9.04
(IOH = 20 mA) 8.6 8.6 8.90 8.2
(IOH = 25 mA) 8.75
(IOH = 0 mA) 15 14.1 14.1 14.59 14.1 Vdc
(IOH = 5.0 mA) 14.27
(IOH = 10 mA) 14 14 14.18 13.6
(IOH = 15 mA) 14.07
(IOH = 20 mA) 13.6 13.6 13.95 13.2
(IOH = 25 mA) 13.80
(continued)
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261
MC14513B
ELECTRICAL CHARACTERISTICS continued (Voltages Referenced to VSS)
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Drive Current RBO Output IOH mAdc
(VOH = 2.5 V) Source 5.0 0.40 0.32 0.64 0.22
(VOH = 9.5 V) 10 0.21 0.17 0.34 0.12
(VOH = 13.5 V) 15 0.81 0.66 1.30 0.46
(VOL = 0.4 V) Sink IOL 5.0 0.18 0.15 0.29 0.10 mAdc
(VOL = 0.5 V) 10 0.47 0.38 0.75 0.26
(VOL = 1.5 V) 15 1.80 1.50 2.90 1.0
Output Drive Current Segments IOL mAdc

(VOL = 0.4 V) Sink 5.0 0.64 0.51 0.88 0.36
(VOL = 0.5 V) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 V) 15 4.2 3.4 8.8 2.4
Iout = 0 A 15 20 0.015 20 600
buffers switching)
Noise Margin for both 1 and 0 level =
1.0 Vdc min @ VDD = 5.0 Vdc
where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.
20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
ANY OUTPUT 50%
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
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262
MC14513B
VDD
Vdc Min
All Types
Typ Max Unit
Output Rise Time Segment Outputs tTLH ns
5.0 40 80
10 30 60
15 25 50
Output Rise Time RBO Output tTLH ns
5.0 480 960
10 240 480
15 190 380
Output Fall Time Segment Outputs (7.) tTHL ns
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 65 130
Output Fall Time RBO Outputs tTHL ns
tTHL = (3.25 ns/pF) CL + 107.5 ns 5.0 270 540
tTHL = (1.35 ns/pF) CL + 67.5 ns 10 135 270
tTHL = (0.95 ns/pF) CL + 62.5 ns 15 110 220
Propagation Delay Time A, B, C, D Inputs (7.) tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 175 350
tPHL = (0.60 ns/pF) CL + 260 ns 10 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 200 400
Propagation Delay Time RBI and BI Inputs (7.) tPLH ns

tPLH = (1.05 ns/pF) CL + 547.5 ns 5.0 600 750
tPLH = (0.45 ns/pF) CL + 177.5 ns 10 200 300
tPLH = (0.30 ns/pF) CL + 135 ns 15 150 220
tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 485 970 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 160 320
Propagation Delay Time LT Input (7.) tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 90 180

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 90 180

10 40
15 30
10 40
15 30
Latch Enable Pulse Width tWL(LE) 5.0 520 260 ns
10 220 110
15 130 65
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MC14513B
20 ns 20 ns
90% VDD
INPUT C 50%
10% VSS
tPLH tPHL
VOH
OUTPUT g
VOL
tTLH tTHL
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.
20 ns 20 ns
90% VDD
INPUT C 50%
10% VSS
tPLH tPHL
VOH
90%
OUTPUT RBO 50%
10% VOL
tTLH tTHL
b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.
20 ns
VDD
90%
LE 50%
10% VSS
th
tsu
VDD
INPUT C 50%
VSS
VOH
OUTPUT g
VOL
c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
50%
10%
LE VSS
tWL(LE)
d. Pulse Width: Data DCBA strobed into latches.
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MC14513B
LIGHT EMITTING DIODE (LED) READOUT

VDD VDD
COMMON
COMMON ANODE LED
CATHODE LED 1.7 V
1.7 V
VSS
VSS
INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
(SUPPLY)
VSS VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
GAS DISCHARGE READOUT LIQUID CRYSTAL (LC) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)
1/4 OF MC14070B
VSS VSS
** A filament prewarm resistor is recommended to reduce
filament thermal shock and increase the effective cold Direct dc drive of LCs not recommended for life of LC readouts.
resistance of the filament.
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MC14513B
LOGIC DIAGRAM
BI 4
15 a
A 7
14 b
13 c
B 1 12 d
11 e
17 f
C 2
16 g
LT 30
RBI 8 10 RBO
D 6
LE 5
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MC14513B
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
DISPLAYS
a g a g a g a g a g a g
CONNECT TO
RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO
VDD (1) D C B A 1 D C B A 1 D C B A 0 D C B A 0 D C B A 0 D C B A 0
MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

INPUT 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1
CODE (0) (0) (5) (0) (1) (3)
TRAILING EDGE ZERO SUPPRESSION
DISPLAYS
a g a g a g a g a g a g CONNECT TO
0
RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI
D C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A VDD (1)
MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
(5) (0) (1) (3) (0) (0) INPUT CODE
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MC14514B, MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical 1 at the selected output, whereas the
MC14515B (output active low option) presents a logical 0 at the http://onsemi.com
selected output. The latches are RS type flipflops which hold the
last input data presented prior to the strobe transition from 1 to 0.
These high and low options of a 4bit latch/4 to 16 line decoder are
constructed with Nchannel and Pchannel enhancement mode
devices in a single monolithic structure. The latches are RS type MARKING
flipflops and data is admitted upon a signal incident at the strobe 24 DIAGRAMS
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding PDIP24
MC145XXBCP
applications where low power dissipation and/or high noise immunity P SUFFIX
AWLYYWW
CASE 709
is desired.
Symbol Parameter Value Unit SOIC24 145XXB

VDD DC Supply Voltage Range 0.5 to +18.0 V DW SUFFIX AWLYYWW
CASE 751E
(DC or Transient) 1

(DC or Transient) per Pin XX = Specific Device Code
WW or W = Work Week
(8Second Soldering)
may occur. MC14514BCP PDIP24 15/Rail
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14514BDW SOIC24 30/Rail
applications of any voltage higher than maximum rated voltages to this MC14515BCP PDIP24 15/Rail
MC14515BDW SOIC24 30/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14515BDWR2 SOIC24 1000/Tape & Reel

MC14514B, MC14515B
PIN ASSIGNMENT
ST 1 24 VDD
D1 2 23 INH
D2 3 22 D4
S7 4 21 D3
S6 5 20 S10
S5 6 19 S11
S4 7 18 S8
S3 8 17 S9
S1 9 16 S14
S2 10 15 S15
S0 11 14 S12
VSS 12 13 S13
DECODE TRUTH TABLE (Strobe = 1)*

Data Inputs Selected Output
MC14514 = Logic 1
Inhibit D C B A MC14515 = Logic 0
0 0 0 0 0 S0
0 0 0 0 1 S1
0 0 0 1 0 S2
0 0 0 1 1 S3
0 0 1 0 0 S4
0 0 1 0 1 S5
0 0 1 1 0 S6
0 0 1 1 1 S7
0 1 0 0 0 S8
0 1 0 0 1 S9
0 1 0 1 0 S10
0 1 0 1 1 S11
0 1 1 0 0 S12
0 1 1 0 1 S13
0 1 1 1 0 S14
0 1 1 1 1 S15
1 X X X X All Outputs = 0, MC14514
All Outputs = 1, MC14515
X = Dont Care
*Strobe = 0, Data is latched
BLOCK DIAGRAM 11
S0 ABCD
9
S1 ABCD
VDD = PIN 24 S2 10 ABCD
VSS = PIN 12 S3 8 ABCD
S4 7 ABCD
2 A 6
DATA 1 S5 ABCD
5
S6 ABCD
3 B 4
DATA 2 S7 ABCD
TRANSPARENT 4 TO 16 18
21 LATCH C DECODER S8 ABCD
DATA 3 17
S9 ABCD
22 D 20
DATA 4 S10 ABCD
19
S11 ABCD
S12 14 ABCD
1
STROBE 13
S13 ABCD
S14 16 ABCD
15
S15 ABCD
23
INHIBIT
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MC14514B, MC14515B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) 5.0 0.25 0.2 0.36 0.14
(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
Total Supply Current (4.) (5.) ITL 5.0 IT = (1.35 A/kHz) f + IDD Adc
buffers switching)
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270
MC14514B, MC14515B
Characteristic Symbol VDD Min

All Types
Typ (7.) Max Unit
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 65 130
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Propagation Delay Time; Data, Strobe to S tPLH, ns
Inhibit Propagation Delay Times tPLH, ns
Setup Time tsu ns
Data to Strobe 5.0 250 125
10 100 50
15 75 38
Strobe to Data 10 0 40
15 10 30
Strobe Pulse Width tWH ns
5.0 350 175
10 100 50
15 75 38
VDD
VDS
S0
STROBE S1
S2 For MC14515B
S3 1. For Pchannel: Inhibit = VDD
INHIBIT S4 2. For Nchannel: Inhibit = VSS
For MC14514B S5 2. and D1D4 constitute binary
1. For Pchannel: Inhibit = VSS D1 S6 2. code for output under test.
1. and D1D4 constitute S7
1. binary code for output S8
D2 S9
1. under test. ID
S10
2. For Nchannel: Inhibit = VDD D3 S11
S12
S13 EXTERNAL
D4 S14 POWER SUPPLY
S15
VSS
Figure 1. Drain Characteristics Test Circuit
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MC14514B, MC14515B
VDD
0.01 F
ID
500 CERAMIC
F
24 VDD
20 ns 20 ns
PULSE VDD
D1 S0 90%
GENERATOR
D2 CL Vin
D3 10% VSS
D4
STROBE
INHIBIT S15
12 CL
VSS
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
VDD
STROBE OUTPUT S0
S0
S1 OUTPUT S1 tTLH tTHL
INHIBIT 20 ns
CL CL
VDD
90%
D1 INPUT 50%
PROGRAMMABLE 10%
PULSE VSS
GENERATOR tPLH tPHL
D2
VDD
OUTPUT
90%
50%
D3 10% VSS
S15 OUTPUT S15

D4 tTLH tTHL
VSS CL
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LOGIC DIAGRAM
AB CD
11 S0
AB CD
9 S1
AB CD
10 S2
AB CD
DATA 1 2 A 8 S3
S Q
AB CD
7 S4
R Q AB CD
6 S5
DATA 2 3 B
S Q AB CD
5 S6
AB CD
4 S7
R Q
273
AB CD
DATA 3 21 C 18 S8
S Q
AB CD
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17 S9
R Q AB CD
20 S10
MC14514B, MC14515B
DATA 4 22 D AB CD
S Q 19 S11
AB CD
14 S12
R Q
STROBE 1 AB CD
13 S13
AB CD
16 S14
INHIBIT 23
AB CD
15 S15
IN MC14515B ONLY
MC14514B, MC14515B
COMPLEX DATA ROUTING
Two MC14512 eightchannel data selectors are used here times faster then the shift frequency of the input registers,
with the MC14514B fourbit latch/decoder to effect a the most significant bit (MSB) from each register could be
complex data routing system. A total of 16 inputs from data selected for transfer to the data bus. Therefore, all of the
registers are selected and transferred via a 3state data bus most significant bits from all of the registers can be
to a data distributor for rearrangement and entry into 16 transferred to the data bus before the next most significant
output registers. In this way sequential data can be rerouted bit is presented for transfer by the input registers.
or intermixed according to patterns determined by data Information from the 3state bus is redistributed by the
select and distribution inputs. MC14514B fourbit latch/decoder. Using the fourbit
Data is placed into the routing scheme via the eight inputs address, D1 thru D4, the information on the inhibit line can
on both MC14512 data selectors. One register is assigned to be transferred to the addressed output line to the desired
each input. The signals on A0, A1, and A2 choose one of output registers, A thru P. This distribution of data bits to the
eight inputs for transfer out to the 3state data bus. A fourth output registers can be made in many complex patterns. For
signal, labelled Dis, disables one of the MC14512 selectors, example, all of the most significant bits from the input
assuring transfer of data from only one register. registers can be routed into output register A, all of the next
In addition to a choice of input registers, 1 thru 16, the rate most significant bits into register B, etc. In this way
of transfer of the sequential information can also be varied. horizontal, vertical, or other methods of data slicing can be
That is, if the MC14512 were addressed at a rate that is eight implemented.
DATA ROUTING SYSTEM
INPUT DATA 3STATE DATA OUTPUT

REGISTERS TRANSFER DATA BUS DISTRIBUTION REGISTERS
DIS
REGISTER 1 D0 Q
D1
D2
D1 D2 D3 D4
MC14512
D3
S0 REGISTER A
D4
STROBE S1
D5
S2
D6
S3
REGISTER 8 D7 S4
A0 A1 A2
S5
S6
MC14514B
DATA S7
SELECT S8
S9
S10
A0 A1 A2
D0 Q S11
REGISTER 9
D1 S12
D2 S13
MC14512
INHIBIT S14
D3
D4 S15 REGISTER P
D5
D6
REGISTER 16 D7
DIS
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MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is

constructed with MOS Pchannel and Nchannel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
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Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
MARKING
UP/DOWN input. The state of the counter changes on the positive
DIAGRAMS
transition of the clock input.
16
Cascading can be accomplished by connecting the Carry Out to the PDIP16
Carry In of the next stage while clocking each counter in parallel. The P SUFFIX MC14516BCP
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high CASE 648 AWLYYWW
to the reset (R) pin. 1
This CMOS counter finds primary use in up/down and difference
16
counting. Other applications include: (1) Frequency synthesizer
SOIC16
applications where low power dissipation and/or high noise immunity 14516B
D SUFFIX AWLYWW
is desired, (2) Analogtodigital and digitaltoanalog conversions, CASE 751B
and (3) Magnitude and sign generation. 1
Supply Voltage Range = 3.0 Vdc to 18 Vdc SOEIAJ16
Internally Synchronous for High Speed F SUFFIX MC14516B
AWLYWW
Logic EdgeClocked Design Count Occurs on Positive Going CASE 966
Edge of Clock 1
Single Pin Reset A = Assembly Location
Asynchronous Preset Enable Operation WL or L = Wafer Lot
YY or Y = Year
Capable of Driving Two LowPower TTL Loads or One LowPower WW or W = Work Week
Schottky Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Device Package Shipping
(DC or Transient) MC14516BDR2 SOIC16 2500/Tape & Reel
Iin, Iout Input or Output Current 10 mA MC14516BF SOEIAJ16 See Note 1.

per Package (Note 3.) 1. For ordering information on the EIAJ version of
TA Ambient Temperature Range 55 to +125 C ON Semiconductor representative.
TL Lead Temperature 260 C against damage due to high static voltages or electric
(8Second Soldering) fields. However, precautions must be taken to avoid ap-
may occur. voltages to this highimpedance circuit. For proper
operation, Vin and Vout should be constrained to the
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C range VSS v v
(Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.

MC14516B
PIN ASSIGNMENT
PE 1 16 VDD
Q3 2 15 C
P3 3 14 Q2
P0 4 13 P2
CARRY IN 5 12 P1
Q0 6 11 Q1
CARRY OUT 7 10 U/D
VSS 8 9 R
BLOCK DIAGRAM
1 PE Q0 6
5 CARRY IN
9 RESET Q1 11
10 UP/DOWN
15 CLOCK Q2 14
4 P0
12 P1 Q3 2
13 P2
CARRY
3 P3 7
OUT
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Preset
Carry In Up/Down Enable Reset Clock Action
1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset
X = Dont Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
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MC14516B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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MC14516B

All Types
Typ (8.) Max Unit
Clock to Q tPHL
Clock to Carry Out tPLH, ns
Carry In to Carry Out tPLH, ns
Preset or Reset to Q tPLH, ns
Preset or Reset to Carry Out tPLH, ns
10 200 100
15 160 80
10 170 100
15 140 75
10 6.0 3.0
15 8.0 4.0
8. Data labelled Typ is not to be used for design purposes but is intended as an Indication of the ICs potential performance.
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MC14516B
SWITCHING CHARACTERISTICS (9.) (CL = 50 pF, TA = 25_C) (continued)

All Types
Typ (10.) Max Unit
Preset or Reset Removal Time trem 5.0 650 325 ns
The Preset or Reset signal must be low prior to a 10 230 115
positivegoing transition of the clock. 15 180 90
Clock Rise and Fall Time tTLH, 5.0 15 s
tTHL 10 5
15 4
Carry In to Clock 10 120 60
15 100 50
Clock to Carry In 10 20 20
15 20 0
Up/Down to Clock 10 200 100
15 150 75
Clock to Up/Down 10 10 60
15 0 40
Pn to PE 10 30 70
15 25 50
PE to Pn 10 420 210
15 420 210
Preset Enable Pulse Width tWH 5.0 200 100 ns
10 100 50
15 80 40
10. Data labelled Typ is not to be used for design purposes but is intended as an Indication of the ICs potential performance.
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MC14516B
VDD
500 pF ID 0.01 F
CERAMIC
PE Q0
CARRY IN
20 ns 20 ns
R Q1 VDD
UP/DOWN 90%
CL CLOCK 50%
PULSE CLOCK Q2 10% VSS
GENERATOR CL VARIABLE
P0 WIDTH
P1 Q3
CL
P2
CARRY
P3 CL
OUT
CL
LOGIC DIAGRAM
P0 Q0 P1 Q1 P2 Q2 P3 Q3
4 6 12 11 13 14 3 2
RESET 9
PRESET
1
ENABLE
CLOCK 15
P P P P
PE Q PE Q PE Q PE Q
C C C C
CARRY OUT 7
T Q T Q T Q T Q
CARRY IN 5
UP/DOWN 10
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280
MC14516B
TOGGLE FLIPFLOP FLIPFLOP FUNCTIONAL TRUTH TABLE

PARALLEL IN Preset
Enable Clock T Qn+1
P
PE Q 1 X X Parallel In
C 0 0 Qn
T Q 0 1 Qn
0 X Qn
X = Dont Care
tsu trem
1
th fcl
CARRY IN OR VDD
UP/DOWN 50%
VSS
VDD
50%
CLOCK VSS
tw(H) tw(H)
VDD
PRESET ENABLE VSS
tTLH
CARRY OUT ONLY
Q0 OR CARRY OUT VOH
90% 90%
10% 10% VOL
tPHL
tTHL tPLH tPLH
trem
VDD
50%
RESET VSS
tw
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
INPUTS CONTROLS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) Data PE, Preset Enable, (Pin 1) Asynchronously loads data
on these inputs is loaded into the counter when PE is taken on the Preset Inputs. This pin is active high and inhibits the
high. clock when high.
Carry In, (Pin 5) This activelow input is used when R, Reset, (Pin 9) Asynchronously resets the Q out
Cascading stages. Carry In is usually connected to Carry Out puts to a low state. This pin is active high and inhibits the
of the previous stage. While high, Clock is inhibited. clock when high.
Clock, (Pin 15) Binary data is incremented or Up/Down, (Pin 10) Controls the direction of count,
decremented, depending on the direction of count, on the high for up count, low for down count.
positive transition of this input.
SUPPLY PINS
OUTPUTS VSS, Negative Supply Voltage, (Pin 8) This pin is
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) usually connected to ground.
Binary data is present on these outputs with Q0 VDD, Positive Supply Voltage, (Pin 16) This pin is
corresponding to the least significant bit. connected to a positive supply voltage ranging from 3.0
Carry Out, (Pin 7) Used when cascading stages, Carry volts to 18.0 volts.
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
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MC14516B
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PRESET
ENABLE
0 = COUNT Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
PE PE
1 = PRESET TERMINAL COUNT
Cin Cout Cin Cout
L.S.D. M.S.D. INDICATOR
CLOCK CLOCK
1 = UP MC14516B MC14516B
U/D U/D
0 = DOWN R R
P0 P1 P2 P3 P0 P1 P2 P3
P0 P1 P2 P3 P4 P5 P6 P7
+VDD +VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
CLOCK RESISTORS = 10 kW
RESET
+VDD
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8Bit Up/Down Counter
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282
CLOCK
UP/DOWN
CARRY IN
(MSD)
PE
P7
P6
P5
P4
P3
P2
P1
P0
CARRY OUT
(MSD)
283
Q7
Q6
MC14516B
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Q5
Q4
Q3
Q2
Q1
Q0
CARRY OUT
(LSD)
RESET
COUNT 13 14 15 16 17 18 19 18 17 16 15 14 13 251 252 253 254 255 0 1 2 3 2 1 0 1 2

TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8BIT UP/DOWN COUNTER
PRESET RESET
PRESET ENABLE ENABLE
UP COUNT DOWN COUNT UP COUNT DOWN UP COUNT
COUNT
MC14516B
fout
BUFFER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
PE PE
Cin Cout Cin Cout
CLOCK L.S.D. CLOCK M.S.D.
MC14516B MC14516B
U/D U/D
R R
P0 P1 P2 P3 P0 P1 P2 P3
P0 P1 P2 P3 P4 P5 P6 P7
+VDD +VDD
THUMBWHEEL SWITCHES
CLOCK (fin) (OPEN FOR 0) RESISTORS = 10 k W
RESET fin
+VDD fout =
n
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
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284
MC14517B
Dual 64-Bit Static Shift

Register
The MC14517B dual 64bit static shift register consists of two
identical, independent, 64bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write http://onsemi.com
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as MARKING
the 16bit, 32bit, and 48bit taps may be entered into the device by DIAGRAMS
application of a clock pulse. This feature permits the register to be loaded 16
with 64 bits in 16 clock periods, and also permits bus logic to be used. PDIP16
P SUFFIX MC14517BCP
This device is useful in time delay circuits, temporary memory storage AWLYYWW
circuits, and other serial shift register applications. CASE 648
1
Fully Static Operation 16
Output Transitions Occur on the Rising Edge of the Clock Pulse

SOIC16 14517B
Exceedingly Slow Input Transition Rates May Be Applied to the DW SUFFIX
Clock Input CASE 751G
AWLYYWW
3State Output at 64thBit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock 1
Pulses
WL or L = Wafer Lot
Capable of Driving Two Lowpower TTL Loads or One Lowpower YY or Y = Year
Schottky TTL Load Over the Rated Temperature Range WW or W = Work Week

Symbol Parameter Value Unit ORDERING INFORMATION
(DC or Transient) MC14517BCP PDIP16 2000/Box
Iin, Iout Input or Output Current 10 mA MC14517BDW SOIC16 47/Rail

(8Second Soldering)
may occur.

MC14517B
PIN ASSIGNMENT
Q16A 1 16 VDD
Q48A 2 15 Q16B
WEA 3 14 Q48B
CA 4 13 WEB
Q64A 5 12 CB
Q32A 6 11 Q64B
DA 7 10 Q32B
VSS 8 9 DB
FUNCTIONAL TRUTH TABLE (X = Dont Care)

Write
Clock Enable Data 16Bit Tap 32Bit Tap 48Bit Tap 64Bit Tap
0 0 X Content of 16Bit Content of 32Bit Content of 48Bit Content of 64Bit
Displayed Displayed Displayed Displayed
0 1 X High Impedance High Impedance High Impedance High Impedance
1 0 X Content of 16Bit Content of 32Bit Content of 48Bit Content of 64Bit
1 1 X High Impedance High Impedance High Impedance High Impedance
0 Data entered Content of 16Bit Content of 32Bit Content of 48Bit Content of 64Bit
into 1st Bit Displayed Displayed Displayed Displayed
1 Data entered Data at tap Data at tap Data at tap High Impedance
into 1st Bit entered into 17Bit entered into 33Bit entered into 49Bit
0 X Content of 16Bit Content of 32Bit Content of 48Bit Content of 64Bit
1 X High Impedance High Impedance High Impedance High Impedance
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286
MC14517B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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287
MC14517B

Characteristic
Symbol
tTLH, tTHL
VDD Min Typ (7.) Max Unit
ns
10 125 75
15 100 60
10 6.7 4.0
15 8.3 5.3
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0
10 See Note (8.)
15
Data to Clock Setup Time tsu 5.0 0 40 ns
10 10 15
15 15 0
Data to Clock Hold Time th 5.0 150 75 ns
10 75 25
15 35 10
Write Enable to Clock Setup Time tsu 5.0 400 170 ns
10 200 65
15 110 50
Write Enable to Clock Release Time trel 5.0 380 160 ns
10 180 55
15 100 40
8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
VDD
CL
CL
Q16 Q32 Q48 Q64
D D
REPETITIVE WAVEFORM C C CL
VDD WE
fo
VSS CL
C
VDD D
C
D VSS
WE
(f = 1/2 fo)
Q16 Q32 Q48 Q64
VSS
50 F CL CL CL CL
ID
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288
MC14517B
Vout = VOH Vout = VOL

VDD = VGS VDD = VGS
Q16 Q32 Q48 Q64 Q16 Q32 Q48 Q64

D D
C C
WE WE
D D
C C
IOH IOL
WE WE
Q16 Q32 Q48 Q64 Q16 Q32 Q48 Q64
EXTERNAL EXTERNAL
POWER POWER
SUPPLY VSS SUPPLY
VSS
(Output being tested should be in the highlogic state) (Output being tested should be in the lowlogic state)
Figure 2. Typical Output Source Current Figure 3. Typical Output Sink Current
tWH
tWL VDD
PIN NOS 1 2 16 17 18 19 90% 33
50%
CLOCK 4 (12) 10% VSS
trel tsu
WRITE 3 (13) VDD
th1 th0 VSS
20 ns
tsu1 tsu0 VDD
DATA IN 7 (9) 90%
th1 50% 50%
10% VSS
tsu1 tsu0 tPHL tPLH
VOH VDD
16BIT OUTPUT 1 (15) th0 VDD 90%
th1 10%
17BIT INPUT tTLH V VSS
tsu1 tsu0 20 ns tPHL tTHL OL
tPLH VOH VDD
32BIT OUTPUT 6 (10) th0 VDD 90% 50%
th1 10%
33BIT INPUT tPHL tTLH VOL VSS
tsu1 tsu0 20 ns tTHL
tPLH VDD
VOH
48BIT OUTPUT 2 (14) th0 VDD
49BIT INPUT VOL VSS
20 ns tPHL tTLH tTHL
tPLH VDD
64BIT OUTPUT 5 (11)
VSS
tTLH
tTHL
Figure 4. AC Test Waveforms
EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
CLOCK
D Q D Q D Q D Q D Q D Q D Q D Q D
DATA C 1 C 2 C 16 C 17 C 32 C 33 C 48 C 49 C 64 Q
3STATE WE 3STATE WE 3STATE WE 3STATE
WRITE
WRITE ENABLE = 0, 16BIT OUTPUT 32BIT OUTPUT 48BIT OUTPUT 64BIT OUTPUT
ENABLE
WRITE ENABLE = 1, 17BIT INPUT 33BIT INPUT 49BIT INPUT HIGH IMPEDANCE
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289
MC14518B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS Pchannel and Nchannel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4stage
counters. The counter stages are type D flipflops, with
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interchangeable Clock and Enable lines for incrementing on either the
positivegoing or negativegoing transition as required when
cascading multiple stages. Each counter can be cleared by applying a MARKING
high level on the Reset line. In addition, the MC14518B will count out DIAGRAMS
of all undefined states within two clock periods. These complementary 16
MOS up counters find primary use in multistage synchronous or PDIP16
P SUFFIX MC14518BCP
ripple counting applications requiring low power dissipation and/or CASE 648 AWLYYWW
high noise immunity.
1
16
Internally Synchronous for High Internal and External Speeds SOIC16 14518B
Logic EdgeClocked Design Incremented on Positive Transition DW SUFFIX

CASE 751G
of Clock or Negative Transition on Enable AWLYYWW
1
16
SOEIAJ16
F SUFFIX MC14518B
CASE 966 AWLYWW
1
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V WL or L = Wafer Lot
(DC or Transient) YY or Y = Year
WW or W = Work Week
TL Lead Temperature 260 C MC14518BDW SOIC16 47/Rail

(8Second Soldering)
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14518BFEL SOEIAJ16 See Note 1.
This device contains protection circuitry to guard against damage due to high 1. For ordering information on the EIAJ version of
static voltages or electric fields. However, precautions must be taken to avoid the SOIC packages, please contact your local
applications of any voltage higher than maximum rated voltages to this ON Semiconductor representative.

MC14518B
PIN ASSIGNMENT
CA 1 16 VDD
EA 2 15 RB
Q0A 3 14 Q3B
Q1A 4 13 Q2B
Q2A 5 12 Q1B
Q3A 6 11 Q0B
RA 7 10 EB
VSS 8 9 CB
BLOCK DIAGRAM
CLOCK
Q0 3
1
Q1 4
C
2 Q2 5
ENABLE Q3 6
R
7
CLOCK 11
Q0
9
Q1 12
C
10 Q2 13
ENABLE Q3 14
R
15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Clock Enable Reset Action
1 0 Increment Counter
0 0 Increment Counter
X 0 No Change
X 0 No Change
0 0 No Change
1 0 No Change
X X 1 Q0 thru Q3 = 0
X = Dont Care
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291
MC14518B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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MC14518B

All Types
Typ (8.) Max Unit
Clock to Q/Enable to Q tPHL
Reset to Q tPHL ns
tPHL = (1.7 ns/pF) CL + 265 ns 5.0 330 650
tPHL = (0.66 ns/pF) CL + 117 ns 10 130 230
tPHL = (0.66 ns/pF) CL + 95 ns 15 90 170
Clock Pulse Width tw(H) 5.0 200 100 ns
tw(L) 10 100 50
15 70 35
10 6.0 3.0
15 8.0 4.0
Clock or Enable Rise and Fall Time tTHL, tTLH 5.0 15 s
10 5
15 4
Enable Pulse Width tWH(E) 5.0 440 220 ns
10 200 100
15 140 70
Reset Pulse Width tWH(R) 5.0 280 125 ns
10 120 55
15 90 40
10 15 15
15 20 5
VDD
0.01 F
500 F ID CERAMIC
PULSE
C Q0
GENERATOR Q1
Q2 CL
E Q3 CL
R CL
CL
VSS
20 ns 20 ns
90%
50%
10%
VSS
VARIABLE
WIDTH
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293
MC14518B
VDD 20 ns 20 ns
90% VDD
CLOCK 50%
PULSE Q0 INPUT 10%
C VSS
GENERATOR tWH tWL
Q1
tPLH tPHL
Q2 CL
E CL 90%
R Q3 CL 50%
CL 10%
VSS Q
tr tf
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLOCK
ENABLE
RESET
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
Q0
Q1
MC14518B
Q2
Q3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
Q0
Q1
MC14520B
Q2
Q3
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294
MC14518B
Q0 Q1 Q2 Q3
D Q D Q D Q D Q
C Q C Q C Q C Q
R R R R
RESET
ENABLE
CLOCK
Figure 4. Decade Counter (MC14518B) Logic Diagram

Q0 Q1 Q2 Q3
D Q D Q D Q D Q
C Q C Q C Q C Q
R R R R
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram

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295
MC14521B
24-Stage Frequency Divider

The MC14521B consists of a chain of 24 flipflops with an input
circuit that allows three modes of operation. The input will function as
a crystal oscillator, an RC oscillator, or as an input buffer for an
external oscillator. Each flipflop divides the frequency of the
previous flipflop by two, consequently this part will count up to 224 =
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16,777,216. The count advances on the negative going edge of the
clock. The outputs of the last sevenstages are available for added
flexibility. MARKING
DIAGRAMS
All Stages are Resettable 16
Reset Disables the RC Oscillator for Low Standby Power Drain PDIP16
MC14521BCP
RC and Crystal Oscillator Outputs Are Capable of Driving External P SUFFIX
AWLYYWW
CASE 648
Loads
1
Test Mode to Reduce Test Time
VDD and VSS Pins Brought Out on Crystal Oscillator Inverter to 16
SOIC16
Allow the Connection of External Resistors for LowPower 14521B
D SUFFIX AWLYWW
Operation CASE 751B
16
Schottky TTL Load over the Rated Temperature Range.
SOEIAJ16
F SUFFIX MC14521B
CASE 966 AWLYWW
1
Symbol Parameter Value Unit A = Assembly Location
WL or L = Wafer Lot
WW or W = Work Week
(DC or Transient)
Iin, Iout Input or Output Current 10 mA ORDERING INFORMATION
(8Second Soldering) MC14521BF SOEIAJ16 See Note 1.
may occur.
3. Temperature Derating: MC14521BFR2 SOEIAJ16 See Note 1.
This device contains protection circuitry to guard against damage due to high the SOIC packages, please contact your local
static voltages or electric fields. However, precautions must be taken to avoid ON Semiconductor representative.

MC14521B
PIN ASSIGNMENT
Q24 1 16 VDD
RESET 2 15 Q23
VSS 3 14 Q22
OUT 2 4 13 Q21
VDD 5 12 Q20
IN 2 6 11 Q19
7 10 Q18
VSS 8 9 IN 1
BLOCK DIAGRAM
RESET
2
Output Count Capacity
Q18 218 = 262,144
Q19 219 = 524,288
STAGES STAGES
9 6 1 THRU 17 18 THRU 24 Q20 220 = 1,048,576
IN 1 IN 2 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q21 221 = 2,097,152
Q22 222 = 4,194,304
VDD = PIN 16 Q23 223 = 8,388,608
VSS = PIN 8
5 4 Q24 224 = 16,777,216
7 VDD 3 OUT2 10 11 12 13 14 15 1
OUT 1 VSS
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297
MC14521B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) Pins 4 & 7 5.0 0.25 0.2 0.36 0.14
(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7 mAdc
(VOH = 4.6 Vdc) Pins 1, 10, 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 11, 12, 13, 14 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) and 15 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4

(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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298
MC14521B
VDD
Output Rise and Fall Time (Counter Outputs) tTLH, tTHL ns
Propagation Delay Time tPHL, tPLH s
Clock to Q18
tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns 5.0 4.5 9.0
tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns 10 1.7 3.5
Clock to Q24
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns 5.0 6.0 12
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns 5.0 1300 2600
tPHL = (0.66 ns/pF) CL + 467 ns 10 500 1000
tPHL = (0.5 ns/pF) CL + 350 ns 15 375 750
Clock Pulse Width tWH(cl) 5.0 385 140 ns
10 150 55
15 120 40
10 9.0 5.0
15 12 6.5
Clock Rise and Fall Time tTLH, tTHL 5.0 15 s
10 5.0
15 4.0
Reset Pulse Width tWH(R) 5.0 1400 700 ns
10 600 300
15 450 225
10 0 160
15 40 110
VDD
500 F 0.01 F
ID
CERAMIC
VDD VDD
Q18 20 ns 20 ns
PULSE CL VDD
IN 2 Q19 Vin 90%
GENERATOR CL 50%
Q20 10% 0V
CL
Q21 50% DUTY CYCLE
Q22 CL
Q23 CL
R
Q24 CL
CL
VSS VSS
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299
MC14521B
VDD
VDD VDD
20 ns 20 ns 20 ns
IN 2
Q18
PULSE IN 2 CL 90%
GENERATOR Q19 50%
CL 10%
Q20
CL tWL tWH
Q21
Q22 CL
90%
Q23 CL 50%
R Qn
CL 10%
Q24
CL tPLH tPHL
VSS VSS tTLH tTHL
500 kHz 50 kHz

Characteristic Circuit Circuit Unit
Crystal Characteristics
Resonant Frequency 500 50 kHz
Equivalent Resistance, RS 1.0 6.2 k
External Resistor/Capacitor Values
VDD
Ro 47 750 k
Ro CT 82 82 pF
R* CS 20 20 pF
VDD VDD
18 M Frequency Stability
IN 1 OUT 1 Frequency Change as a Function
OUT 2 of VDD (TA = 25_C)
Q18 VDD Change from 5.0 V to 10 V
Q19 + 6.0 + 2.0 ppm
VDD Change from 10 V to 15 V
IN 2 Q20 + 2.0 + 2.0 ppm
Q21 Frequency Change as a Function
Q22 of Temperature (VDD = 10 V)
4.0 2.0 ppm
Q23 TA Change from 55_C to + 25_C
CS CT + 100 + 120 ppm
R Q24 MC14521 only
Complete Oscillator*
VSS VSS
TA Change from + 25_C to + 125_C
R*
MC14521 only
2.0 2.0 ppm
Complete Oscillator*

160 560 ppm
*Optional for low power operation,

10 k R 70 k. *Complete oscillator includes crystal, capacitors, and resistors.

Figure 3. Crystal Oscillator Circuit Figure 4. Typical Data for Crystal Oscillator Circuit
http://onsemi.com
300
MC14521B
100
VDD = 10 V TEST CIRCUIT
50

8.0 FIGURE 7
TEST CIRCUIT
VDD = 15 V 20 f AS A FUNCTION
FIGURE 7
4.0 OF RTC
10 (C = 1000 pF)
5.0 (RS 2RTC)
0 f AS A FUNCTION
OF C
10 V 2.0 (RTC = 56 k)
4.0
1.0 (RS = 120 k)
8.0 0.5
5.0 V
0.2
12
RTC = 56 k, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C 0.1
C = 1000 pF
{ RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
1.0 k 10 k 100 k 1.0 m
16 RTC, RESISTANCE (OHMS)
55 25 0 25 50 75 100 125 0.0001 0.001 0.01 0.1
TA, AMBIENT TEMPERATURE (C), DEVICE ONLY C, CAPACITANCE (F)

RS RTC VDD VDD

C
VDD
VDD VDD
IN 1 Q18
IN 1 OUT 1 Q19
OUT 2 Q20
Q18 Q21
Q19 PULSE IN 2 Q22
IN 2 Q20 GENERATOR Q23
Q21 Q24
Q22 OUT 1
Q23 R OUT 2
R Q24
VSS VSS
VSS VSS
Figure 7. RC Oscillator Circuit Figure 8. Functional Test Circuit
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301
MC14521B
FUNCTIONAL TEST SEQUENCE
Reset
Inputs
In 2 Out 2 VSS
Outputs
VDD Q18 thru
Comments
Counter is in three 8stage
Q24 sections in parallel mode
Counter is reset. In 2 and
1 0 0 VDD Gnd 0 Out 2 are connected
together
A test function (see Figure 8) has been 0 1 1 First 0 to 1 transition

included for the reduction of test time required to on In 2, Out 2 node.
exercise all 24 counter stages. This test function 0 0 255 0 to 1 transitions
divides the counter into three 8stage sections, 1 1 are clocked into this In 2,
and 255 counts are loaded in each of the Out 2 node.
8stage sections in parallel. All flipflops are
now at a logic
g 1. The counter is now returned
to the normal 24stages in series configuration. The 255th 0 to 1
1 1 1
One more pulse is entered into Input 2 (In 2) transition.
which will cause the counter to ripple from an all 0 0 1
1 state to an all 0 state. 0 0 1
G d
Gnd
Counter converted back to
1 0 VDD 1
24stages in series mode.
Out 2 converts back to an
1 0 1
output.
Counter ripples from an all
0 1 0 1 state to an all 0 stage.
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302
MC14521B
LOGIC DIAGRAM
VDD RESET
5 2
9 STAGES
1 2 8
3 THRU 7
IN 1
6 4
IN 2 OUT 2
7 3
OUT 1 VSS
9 10 STAGES 16
11 THRU 15
17 18 19 20 21 22 23 24
10 11 12 13 14 15 1 VDD = PIN 16
Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS = PIN 8
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303
MC14526B
Presettable 4-Bit Down

Counters
The MC14526B binary counter is constructed with MOS Pchannel
and Nchannel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded 0 state output for dividebyN applications. In http://onsemi.com
single stage applications the 0 output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade dividebyN MARKING
operation with no additional gates required. The Inhibit input allows DIAGRAMS
disabling of the pulse counting function. Inhibit may also be used as a 16
negative edge clock. PDIP16
P SUFFIX MC14526BCP
This complementary MOS counter can be used in frequency AWLYYWW
synthesizers, phaselocked loops, and other frequency division CASE 648
applications requiring low power dissipation and/or high noise 1
immunity. 16
14526B
Logic EdgeClocked Design Incremented on Positive Transition SOIC16
DW SUFFIX
of Clock or Negative Transition of Inhibit CASE 751G
Asynchronous Preset Enable AWLYYWW

SOEIAJ16
F SUFFIX MC14526B
CASE 966 AWLYWW
1
WL or L = Wafer Lot
(8Second Soldering) MC14526BDWR2 SOIC16 1000/Tape & Reel
may occur.

MC14526B
PIN ASSIGNMENT
Q3 1 16 VDD
P3 2 15 Q2
PE 3 14 P2
INHIBIT 4 13 CF
P0 5 12 0
CLOCK 6 11 P1
7 10 RESET
VSS 8 9 Q1
FUNCTION TABLE
Inputs Output
Preset Cascade Resulting
Clock Reset Inhibit Enable Feedback 0 Function
X H X L L L Asynchronous
y reset*
X H X H L H Asynchronous reset
X H X X H H A
Asynchronous
h reset
X L X H X L Asynchronous preset
L H L X L Decrement inhibited
L L L X L Decrement inhibited
L L L L L No change**
g (inactive
( edge)
g )
H L L L L No change** (inactive edge)
L L L L L D
Decrement**
**
H L L L L Decrement**
X = Dont Care
NOTES:
** Output 0 is low when reset goes high only it PE and CF are low.
** Output 0 is high when reset is low, only if CF is high and count is 0000.
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305
MC14526B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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306
MC14526B

Characteristic
Symbol
tTLH,
ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns (Figures 4, 5) 10 50 100
Propagation Delay Time (Inhibit Used as Negative tPLH, ns
Edge Clock) tPHL
Clock or Inhibit to Q (Figures 4, 5, 6)
Clock or Inhibit to 0
Propagation Delay Time tPLH, 5.0 260 520 ns

Pn to Q tPHL 10 120 240
(Figures 4, 7) 15 100 200
Propagation Delay Time tPHL 5.0 250 500 ns
Reset to Q 10 110 220
(Figure 8) 15 80 160
Propagation Delay Time tPHL, 5.0 220 440 ns
Preset Enable to 0 tPLH 10 100 200
(Figures 4, 9) 15 80 160
Clock or Inhibit Pulse Width tw 5.0 250 125 ns
10 100 50
(Figures 5, 6) 15 80 40
Clock Pulse Frequency (with PE = low) fmax 5.0 2.0 1.5 MHz
10 5.0 3.0
(Figures 4, 5, 6) 15 6.6 4.0
Clock or Inhibit Rise and Fall Time tr, 5.0 15 s
tf 10 5
(Figures 5, 6) 15 4
Pn to Preset Enable 10 50 15
(Figure 10) 15 40 10
Preset Enable to Pn 10 30 5
(Figure 10) 15 30 0
Preset Enable Pulse Width tw 5.0 250 125 ns
10 100 50
(Figure 10) 15 80 40
10 250 125
(Figure 8) 15 200 100
10 20 30
(Figure 8) 15 30 20
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307
MC14526B
VOH VOL
VDD = VGS VDD = VGS
CF Q0 CF Q0
PE PE
P0 Q1 P0 Q1
P1 P1
P2 Q2 P2 Q2
P3 IOH P3 IOL
RESET Q3 RESET Q3
INHIBIT INHIBIT
CLOCK 0 CLOCK 0
EXTERNAL EXTERNAL
VSS VSS
POWER POWER
SUPPLY SUPPLY

VDD
CF Q0
PE
P0 Q1
P1
P2 Q2
P3 CL
RESET Q3 TEST POINT
CL
INHIBIT CL
CLOCK 0 Q or 0
CL DEVICE
VSS CL UNDER
TEST CL*
PULSE
GENERATOR 20 ns 20 ns
90% VDD
CLOCK 50%
10% VSS
VARIABLE
WIDTH 50% DUTY CYCLE *Includes all probe and jig capacitance.
Figure 3. Power Dissipation Figure 4. Test Circuit
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308
MC14526B
SWITCHING WAVEFORMS
tr tf tf tr
VDD VDD
90% 90%
CLOCK 50% INHIBIT 50%
10% VSS 10%
VSS
tw tw
1/fmax 1/fmax
tPLH tPHL tPLH tPHL
ANY Q 90% 90%

ANY Q
OR 0 50% OR 0 50%
10% 10%
tTLH tTHL tTLH tTHL
Figure 5. Figure 6.
tw
VDD
RESET 50%
VSS
tr tf
tPHL
VDD
90%
ANY P 50%
10% ANY Q 50%
VSS
tPLH tPHL
trem
ANY Q VDD
50%
CLOCK
50%
VSS
Figure 7. Figure 8.
VALID
tr tf VDD
VDD ANY P 50%
PRESET 90%
ENABLE 50% VSS
10% GND
tsu th
tPHL tPLH VDD
PRESET
ENABLE 50%
0 50% VSS
tw
Figure 9. Figure 10.
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309
MC14526B
PIN DESCRIPTIONS
Preset Enable (Pin 3) If Reset is low, a high level on other than all zeroes, the 0 output is valid after the rising
the Preset Enable input asynchronously loads the counter edge of Preset Enable (when Cascade Feedback is high). See
with the programmed values on P0, P1, P2, and P3. the Function Table.
Inhibit (Pin 4) A high level on the Inhibit input pre Cascade Feedback (Pin 13) If the Cascade Feedback
vents the Clock from decrementing the counter. With Clock input is high, a high level is generated at the 0 output when
(pin 6) held high, Inhibit may be used as a negative edge the count is all zeroes. If Cascade Feedback is low, the 0
clock input. output depends on the Preset Enable input level. See the
Clock (Pin 6) The counter decrements by one for each Function Table.
rising edge of Clock. See the Function Table for level P0, P1, P2, P3 (Pins 5, 11, 14, 2) These are the preset
requirements on the other inputs. data inputs. P0 is the LSB.
Reset (Pin 10) A high level on Reset asynchronously Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) These are the
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is synchronous counter outputs. Q0 is the LSB.
high, causes the 0 output to go high. VSS (Pin 8) The most negative power supply potential.
0 (Pin 12) The 0 (Zero) output issues a pulse one This pin is usually ground.
clock period wide when the counter reaches terminal count VDD (Pin 16) The most positive power supply
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and potential. VDD may range from 3 to 18 V with respect to VSS.
Preset Enable is low. When presetting the counter to a value
STATE DIAGRAM
MC14526B
0 1 2 3 4
15 5
14 6
13 7
12 11 10 9 8
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310
MC14526B
MC14526B LOGIC DIAGRAM (Binary Down Counter)
P0 Q0 P1 Q1 P2 Q2 P3 Q3
5 7 11 9 14 15 2 1
D R D RQ D RQ D RQ
C C C C
T PE Q T PE Q T PE Q T PE Q
VDD VDD
13
CF
PE 3
INHIBIT 4
12
0
CLOCK 6
10
RESET
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311
MC14526B
DivideByN, Single Stage Cascaded, Presettable DivideByN

Figure 11 shows a single stage dividebyN application. Figure 12 shows a three stage cascade application. Taking
To initialize counting a number, N is set on the parallel Reset high loads N. Only the first stages Reset pin (least
inputs (P0, P1, P2, and P3) and reset is taken high significant counter) must be taken high to cause the preset
asynchronously. A zero is forced into the master and slave for all stages, but all pins could be tied together, as shown.
of each bit and, at the same time, the 0 output goes high. When the first stages Reset pin goes high, the 0 output
Because Preset Enable is tied to the 0 output, preset is is latched in a high state. Reset must be released while Clock
enabled. Reset must be released while the Clock is high so is high and time allowed for Preset Enable to load N into all
the slaves of each bit may receive N before the Clock goes stages before Clock goes low.
low. When the Clock goes low and Reset is low, the 0 When Preset Enable is high and Clock is low, time must
output goes low (if P0 through P3 are unequal to zero). be allowed for the zero digits to propagate a Cascade
The counter downcounts with each rising edge of the Feedback to the first nonzero stage. Worst case is from the
Clock. When the counter reaches the zero state, an output most significant bit (M.S.B.) to the L.S.B., when the L.S.B.
pulse occurs on 0 which presets N. The propagation delays is equal to one (i.e. N = 1).
from the Clocks rising and falling edges to the 0 outputs After N is loaded, each stage counts down to zero with
rising and falling edges are about equal, making the 0 each rising edge of Clock. When any stage reaches zero and
output pulse approximately equal to that of the Clock pulse. the leading stages (more significant bits) are zero, the 0
The Inhibit pin may be used to stop pulse counting. When output goes high and feeds back to the preceding stage.
this pin is taken high, decrementing is inhibited. When all stages are zero, the Preset Enable automatically
loads N while the Clock is high and the cycle is renewed.
P0 Q0
P1 Q1
N
P2 Q2
P3 Q3 BUFFER
VDD fin
CF
0 N
RESET
VSS INHIBIT
fin CLOCK
PE
Figure 11. N Counter
LSB MSB
N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
VDD
P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3
fin CLOCK CLOCK CLOCK
CF CF CF
INHIBIT INHIBIT INHIBIT
VSS RESET 0 PE VSS RESET 0 PE VSS RESET 0 PE
VDD
LOAD
N BUFFER
10 K
VSS fin
N
Figure 12. 3 Stages Cascaded
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312
MC14528B
Dual Monostable
Multivibrator
The MC14528B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an output pulse over a wide range of widths, the duration
of which is determined by the external timing components, CX and http://onsemi.com
RX.
Separate Reset Available MARKING
DIAGRAMS
16
Triggerable from Leading or Trailing Edge Pulse PDIP16
AWLYYWW
CASE 648
1
PinforPin Replacement with the MC14538B 16
SOIC16
14528B
D SUFFIX AWLYWW
CASE 751B
1
SOEIAJ16
VDD DC Supply Voltage Range 0.5 to +18.0 V MC14528B
F SUFFIX
CASE 966 AWLYWW
(DC or Transient)
1
WL or L = Wafer Lot
(8Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device MC14528BCP PDIP16 2000/Box
may occur.
3. Temperature Derating: MC14528BD SOIC16 48/Rail
applications of any voltage higher than maximum rated voltages to this MC14528BFEL SOEIAJ16 See Note 1.
to the range VSS v (Vin or Vout) vVDD. 1. For ordering information on the EIAJ version of

MC14528B
PIN ASSIGNMENT
VSS 1 16 VDD
CX1/RX1 2 15 VSS
RESET 1 3 14 CX2/RX2
A1 4 13 RESET 2
B1 5 12 A2
Q1 6 11 B2
Q1 7 10 Q2
VSS 8 9 Q2
BLOCK DIAGRAM
CX1 RX1
VDD
1 2
4 6
A1 Q1
5 7
B1 Q1
3
RESET 1
CX2 RX2
VDD
15 14
12 10
A2 Q2
11 9
B2 Q2
13
RESET 2
VDD = PIN 16
VSS = PIN 1, PIN 8, PIN 15
RX AND CX ARE EXTERNAL COMPONENTS
ONESHOT SELECTION GUIDE
100 ns 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1s 10 s

MC14528B
MC14536B 23 HR
MC14538B
MC14541B 5 MIN.
MC4538A*
*LIMITED OPERATING VOLTAGE (26 V)
TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE
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314
MC14528B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
Output Drive Current mAdc

(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) IOH 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.4 Vdc) Sink 5.0 0.64 0.51 0.88 0.36 mAdc
(VOL = 0.5 Vdc) IOL 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
Total Supply Current at an IT IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x108 Adc
external load Capacitance (CL) RXCX(VDD2)2f] x 103
and at external timing where: IT in A (per circuit), CL and CX in pF, RX in megohms,
capacitance (CX), use the VDD in Vdc, f in kHz is input frequency.
formula (5.)
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315
MC14528B

CX RX VDD
Characteristic Symbol pF k Vdc Min Typ (9.) Max Unit
TurnOff, TurnOn Delay Time A or B to Q or Q tPLH, 15 5.0 ns
TurnOff, TurnOn Delay Time A or B to Q or Q tPLH, 1000 10 ns
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns tPHL 5.0 705
tPLH, tPHL = (0.66 ns/pF) CL + 257 ns 10 290
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns 15 210
Input Pulse Width A or B tWH 15 5.0 5.0 150 70 ns
10 75 30
15 55 30
tWL 1000 10 5.0 70 ns
10 30
15 30
Output Pulse Width Q or Q tW 15 5.0 5.0 550 ns
(For CX < 0.01 F use graph for 10 350
appropriate VDD level.) 15 300
Output Pulse Width Q or Q tW 10,000 10 5.0 15 30 45 s
(For CX > 0.01 F use formula: 10 10 50 90
tW = 0.2 RX CX Ln [VDD VSS]) (6.) 15 15 55 95
Pulse Width Match between Circuits in the same t1 t2 10,000 10 5.0 6.0 25 %
package 10 8.0 35
15 8.0 35
Reset Propagation Delay Reset to Q or Q tPLH, 15 5.0 5.0 325 600 ns
tPHL 10 90 225
15 60 170
1000 10 5.0 1000 ns
10 300
15 250
Retrigger Time trr 15 5.0 5.0 0 ns
10 0
15 0
1000 10 5.0 0 ns
10 0
15 0
External Timing Resistance RX 5.0 1000 k
External Timing Capacitance CX No Limits (7.) F
6. RX is in Ohms, CX is in farads, VDD and VSS in volts, PWout in seconds.
7. If CX > 15 F, Use Discharge Protection Diode DX, per Fig. 9.
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316
MC14528B
FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H L Not Triggered
H H Not Triggered
H L, H, H Not Triggered
H L L, H, Not Triggered
L X X L H
X X Not Triggered
VDD VDD
16 16
IOL
A Q OPEN A Q
VOL
B B
VOH
RESET Q RESET Q OPEN
IOH
8 VSS 8 VSS
Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit
VDD
0.1 mF
500 pF ID
CERAMIC
RX RX
CX CX
20 ns 20 ns
VDD
Vin 90%
A
B Q Vin 10% 0V
CL
RESET Q DUTY CYCLE = 50%
CL
A Q
CL
B Q
CL
RESET
VSS
Figure 3. Power Dissipation Test Circuit and Waveforms
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317
MC14528B

VDD

INPUT CONNECTIONS
*CX = 15 pF
RX RX *CL = 15 pF Characteristics Reset A B
CX CX
RX = 5.0 k W tPLH, tPHL, tTLH, tTHL VDD PG1 VDD
tW
tPLH, tPHL, tTLH, tTHL VDD VSS PG2
A tW
PULSE
GENERATOR tPLH(R), tPHL(R), tW PG3 PG1 PG2
B Q
CL
RESET Q
PULSE
CL
GENERATOR PG1 =
A Q *Includes capacitance of probes,
CL wiring, and fixture parasitic.
B Q PG2 =
PULSE NOTE: AC test waveforms for
CL
GENERATOR
RESET PG1, PG2, and PG3 on
next page. PG3 =
VSS
Figure 4. AC Test Circuit
90% VDD
50% 10% 50%
A VSS
tWH tTLH tTHL
tTHL tTLH
B VDD
50% 90%
10% VSS
tWL
tTHL tTLH
RESET VDD
90% 50%
10% VSS
tTHL tWL
tW
tPLH tTLH tPHL trr
90% VOH
50% 50% 50% 10% 50%
Q VOL
tTLH tTHL
tPHL tPHL tPHL
Q VOH
50% 50% 90% 50% 50%
10% VOL
Figure 5. AC Test Waveforms
1000
VDD = 15 V
10 V 15 V
5.0 V 10 V
100 5.0 V
t W, PULSE WIDTH ( m s)
RX = 100 k W 15 V
10 V
10
5.0 V
RX = 10 k W
1.0 RX = 5.0 k W
15 V
10 V
5.0 V
0.1
10 100 1000 10,000 100,000
CX, EXTERNAL CAPACITANCE (pF)
Figure 6. Pulse Width versus CX
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318
MC14528B
Cx Rx Cx Rx
VDD VDD
RISING EDGE RISING EDGE

Q A Q
TRIGGER A TRIGGER
B Q B Q
RESET RESET
VDD
VDD VDD
Cx Rx
Cx Rx
VDD
VDD
A Q
A Q
FALLING EDGE B Q
FALLING EDGE B Q TRIGGER RESET
TRIGGER RESET
VDD
VDD
Figure 7. Retriggerable Figure 8. NonRetriggerable

Monostables Circuitry Monostables Circuitry
DX
Cx VDD
NC
Rx 1, 15 2, 14
VDD
Q NC
A
Q
B Q NC
Q RESET
RESET
VDD
VDD VDD
VDD
Figure 9. Use of a Diode to Limit Figure 10. Connection of Unused Sections

Power Down Current Surge
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319
MC14532B
8-Bit Priority Encoder

The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(Ein) are provided. Five outputs are available, three are address outputs
http://onsemi.com
(Q0 thru Q2), one group select (GS) and one enable output (Eout).
Schottky TTL Load over the Rated Temperature Range PDIP16
P SUFFIX MC14532BCP
CASE 648 AWLYYWW

Symbol Parameter Value Unit SOIC16
14532B
D SUFFIX AWLYWW
VDD DC Supply Voltage Range 0.5 to +18.0 V CASE 751B
(DC or Transient)
16
(DC or Transient) per Pin F SUFFIX MC14532B
CASE 966 AWLYWW
1
YY or Y = Year
TL Lead Temperature 260 C WW or W = Work Week
(8Second Soldering)
applications of any voltage higher than maximum rated voltages to this MC14532BD SOIC16 48/Rail
MC14532BFR1 SOEIAJ16 See Note 1.


MC14532B
PIN ASSIGNMENT
D4 1 16 VDD
D5 2 15 Eout
D6 3 14 GS
D7 4 13 D3
Ein 5 12 D2
Q2 6 11 D1
Q1 7 10 D0
VSS 8 9 Q0
TRUTH TABLE
Input Output
Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout
0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 1 X X X X X X X 1 1 1 1 0
1 0 1 X X X X X X 1 1 1 0 0
1 0 0 1 X X X X X 1 1 0 1 0
1 0 0 0 1 X X X X 1 1 0 0 0
1 0 0 0 0 1 X X X 1 0 1 1 0
1 0 0 0 0 0 1 X X 1 0 1 0 0
1 0 0 0 0 0 0 1 X 1 0 0 1 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0
X = Dont Care
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321
MC14532B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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322
MC14532B

Characteristic
Symbol
tTLH,
ns
Propagation Delay Time Ein to Eout tPLH, ns
Propagation Delay Time Ein to GS tPLH, ns
tPLH, tPHL = (0.66 ns/pF) CL 57 ns 10 90 180
Propagation Delay Time Ein to Qn tPHL, ns
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH 5.0 280 560
Propagation Delay Time Dn to Qn tPLH, ns
Propagation Delay Time Dn to GS tPLH, ns
Vout
Ein
D0
D1 Eout
D2 Q0
SWITCH
MATRIX D3 Q1
D4 Q2 VDD
ID
D5 GS
D6 500 F ID 0.01 F
D7
EXTERNAL
POWER
SUPPLY Ein Eout
D0 CL
VGS = VDD VGS = VDD D1 Q0

VDS = Vout VDS = Vout VDD D2 CL
Output
Sink Current Source Current D3 Q1
Under
D4 CL
Test D0 thru D7 Ein D0 thru D6 D7 Ein
D5 Q2
Eout X 0 0 0 1 CL
Q0 X 0 0 1 1 PULSE D6
Q1 X 0 0 1 1 GENERATOR D7 GS
Q2 X 0 0 1 1 (fo) CL
VSS
GS X 0 0 1 1
Figure 1. Typical Sink and Source

Current Characteristics Figure 2. Typical Power Dissipation Test Circuit
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323
MC14532B
VDD
Ein Eout
D0 CL
D1 Q0
PROGRAMMABLE D2 CL
PULSE D3 Q1
GENERATOR D4 CL
D5 Q2
D6 CL
D7 GS
VSS CL
NOTE: Input rise and fall times are 20 ns

PIN
NO.
50%
D0 10
50%
D1 11
50%
D2 12
50%
D3 13
50%
D4 1
50%
D5 2
50%
D6 3
50%
D7 4
50%
Ein 5
tPLH tPHL
90%
50%
Eout 15 10%
tTHL
tTLH tPLH tPHL
90%
50%
GS 14 10%
tTLH tPLH tPLH tPLH tTHL
tPLH tPHL tPHL tPHL tPHL
90%
50%
Q0 9 10%
tPLH tPLH tTLH tTHL
tPHL tPHL
90%
50%
Q1 7 10%
tTLH tTHL
tPLH tPHL
90%
50%
10%
Q2 6
tTLH tTHL
Figure 3. AC Test Circuit and Waveforms
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324
MC14532B
LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS
Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7
Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7)
10 Q2 = Ein (D4 + D5 + D6 + D7)
D0
GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
11
D1 9
Q0
12
D2
13
D3
1
D4
7
Q1
2
D5
3
D6
4
D7
6
5 Q2
Ein
14
GS
15
Eout
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325
MC14532B
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
VDD Ein Eout Ein Eout Eout = 1

WITH Din = 0
GS Q2 Q1 Q0 Q2 Q1 Q0
3/4 MC14071B
Q3 Q2 Q1 Q0
Figure 4. Two MC14532Bs Cascaded for 4Bit Output
VDD VSS
CLOCK
INPUT
C E R C E R
1/2 MC14520B 1/2 MC14520B
DIGITAL TO ANALOG CONVERSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
The digital eightbit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between Ibias for the MC1710 and R
between N and Pchannel outputs gives a value of R of
[
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 F). DIGITAL INPUT/OUTPUT
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz. D0 D1 D2 D3 D4 D5 D6 D7 8BIT WORD
Ein TO BE CONVERTED
ANALOG TO DIGITAL CONVERSION VDD
Q2 Q1 Q0
An analog signal is applied to the analog input of the
X7 X6 X5 X4 X3 X2 X1 X0
MC1710. A digital eightbit word known to represent a dig- A
itized level less than the analog input is applied to the B MC14512
C Z
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
MC1710
between incrementations (i.e. 3.0 ms). The output of the R
MC1710 will change when the digital input represents the ANALOG
STOP OUTPUT
first digitized level above the analog input. This word is the WORD C
digital representation of the analog word. INCREMENTATION
ANALOG
INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
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326
MC14536B
Programmable Timer
The MC14536B programmable timer is a 24stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
onchip RC oscillator or an external clock are provided. An onchip
monostable circuit incorporating a pulsetype output has been
included. By selecting the appropriate counter stage in conjunction
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with the appropriate input clock frequency, a variety of timing can be
achieved.
24 FlipFlop Stages Will Count From 20 to 224 MARKING
DIAGRAMS
Last 16 Stages Selectable By FourBit Select Code 16
8Bypass Input Allows Bypassing of First Eight Stages PDIP16
MC14536BCP
Set and Reset Inputs P SUFFIX
CASE 648 AWLYYWW
Clock Inhibit and Oscillator Inhibit Inputs 1
OnChip RC Oscillator Provisions
16
OnChip Monostable Output Provisions
Clock Conditioning Circuit Permits Operation With Very Long Rise SOIC16 14536B
and Fall Times DW SUFFIX
Test Mode Allows Fast Test Sequence CASE 751G
AWLYYWW
1

SOEIAJ16
F SUFFIX MC14536B
CASE 966 AWLYWW

YY or Y = Year
WW or W = Work Week
(DC or Transient)
TA Operating Temperature Range 55 to +125 C MC14536BCP PDIP16 2000/Box

Tstg Storage Temperature Range 65 to +150 C MC14536BDW SOIC16 47/Rail
(8Second Soldering)
may occur. 1. For ordering information on the EIAJ version of
3. Temperature Derating: the SOIC packages, please contact your local
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C ON Semiconductor representative.

MC14536B
PIN ASSIGNMENT
SET 1 16 VDD
RESET 2 15 MONO IN
IN 1 3 14 OSC INH
OUT 1 4 13 DECODE
OUT 2 5 12 D
8BYPASS 6 11 C
CLOCK INH 7 10 B
VSS 8 9 A
BLOCK DIAGRAM
CLOCK INH. RESET SET 8 BYPASS
7 2 1 6
OSC. INHIBIT 14
STAGES STAGES 9 THRU 24

IN1 Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
3 1 THRU 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
4 5
OUT1 OUT2 A 9
B 10
C 11 DECODER
VDD = PIN 16 D 12
VSS = PIN 8
MONOSTABLE DECODE
MONOIN 15 13
MULTIVIBRATOR OUT
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328
MC14536B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) Pins 4 & 5 5.0 0.25 0.25 0.36 0.14
(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1
(VOH = 4.6 Vdc) Pin 13 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.020 10 300
15 20 0.030 20 600
buffers switching)
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329
MC14536B

Characteristic
Output Rise and Fall Time (Pin 13)
Symbol
tTLH,
ns
Clock to Q1, 8Bypass (Pin 6) High tPHL
Clock to Q1, 8Bypass (Pin 6) Low tPLH, s
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns tPHL 5.0 3.8 7.6
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns 10 1.5 3.0
Clock to Q16 tPLH, s
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns tPHL 5.0 7.0 14
Reset to Qn tPHL ns
tPHL = (1.7 ns/pF) CL + 1415 ns 5.0 1500 3000
tPHL = (0.66 ns/pF) CL + 567 ns 10 600 1200
tPHL = (0.5 ns/pF) CL + 425 ns 15 450 900
10 200 100
15 170 85
(50% Duty Cycle) 10 3.0 1.5
15 5.0 2.0
Clock Rise and Fall Time tTLH, 5.0
tTHL 10 No Limit
15
Reset Pulse Width tWH 5.0 1000 500 ns
10 400 200
15 300 150
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330
MC14536B
PIN DESCRIPTIONS
INPUTS OSC INHIBIT (Pin 14) A high level on this pin stops
SET (Pin 1) A high on Set asynchronously forces the RC oscillator which allows for very lowpower standby
Decode Out to a high level. This is accomplished by setting operation. May also be used, in conjunction with an external
an output conditioning latch to a high level while at the same clock, with essentially the same results as the Clock Inhibit
time resetting the 24 flipflop stages. After Set goes low input.
(inactive), the occurrence of the first negative clock MONOIN (Pin 15) Used as the timing pin for the
transition on IN1 causes Decode Out to go low. The onchip monostable multivibrator. If the MonoIn input is
counters flipflop stages begin counting on the second connected to VSS, the monostable circuit is disabled, and
negative clock transition of IN1. When Set is high, the Decode Out is directly connected to the selected Q output.
onchip RC oscillator is disabled. This allows for very The monostable circuit is enabled if a resistor is connected
lowpower standby operation. between MonoIn and VDD. This resistor and the devices
RESET (Pin 2) A high on Reset asynchronously internal capacitance will determine the minimum output
forces Decode Out to a low level; all 24 flipflop stages are pulse widths. With the addition of an external capacitor to
also reset to a low level. Like the Set input, Reset disables VSS, the pulse width range may be extended. For reliable
the onchip RC oscillator for standby operation. operation the resistor value should be limited to the range of
IN1 (Pin 3) The devices internal counters advance on 5 k to 100 k and the capacitor value should be limited to
the negativegoing edge of this input. IN1 may be used as an a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
external clock input or used in conjunction with OUT1 and A, B, C, D (Pins 9, 10, 11, 12) These inputs select the
OUT2 to form an RC oscillator. When an external clock is flipflop stage to be connected to Decode Out. (See the truth
used, both OUT1 and OUT 2 may be left unconnected or tables.)
used to drive 1 LSTTL or several CMOS loads.
OUTPUTS
8BYPASS (Pin 6) A high on this input causes the first
8 flipflop stages to be bypassed. This device essentially OUT1, OUT2 (Pin 4, 5) Outputs used in conjunction
becomes a 16stage counter with all 16 stages selectable. with IN1 to form an RC oscillator. These outputs are
Selection is accomplished by the A, B, C, and D inputs. (See buffered and may be used for 20 frequency division of an
the truth tables.) external clock.
CLOCK INHIBIT (Pin 7) A high on this input DECODE OUT (Pin 13) Output function depends on
disconnects the first counter stage from the clocking source. configuration. When the monostable circuit is disabled, this
This holds the present count and inhibits further counting. output is a 50% duty cycle square wave during free run.
However, the clocking source may continue to run. TEST MODE
Therefore, when Clock Inhibit is brought low, no oscillator The test mode configuration divides the 24 flipflop
startup time is required. When Clock Inhibit is low, the stages into three 8stage sections to facilitate a fast test
counter will start counting on the occurrence of the first sequence. The test mode is enabled when 8Bypass, Set and
negative edge of the clocking source at IN1. Reset are at a high level. (See Figure 8.)
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331
MC14536B
TRUTH TABLES
Input Input
Stage Selected Stage Selected
8Bypass D C B A for Decode Out 8Bypass D C B A for Decode Out
0 0 0 0 0 9 1 0 0 0 0 1
0 0 0 0 1 10 1 0 0 0 1 2
0 0 0 1 0 11 1 0 0 1 0 3
0 0 0 1 1 12 1 0 0 1 1 4
0 0 1 0 0 13 1 0 1 0 0 5
0 0 1 0 1 14 1 0 1 0 1 6
0 0 1 1 0 15 1 0 1 1 0 7
0 0 1 1 1 16 1 0 1 1 1 8
0 1 0 0 0 17 1 1 0 0 0 9
0 1 0 0 1 18 1 1 0 0 1 10
0 1 0 1 0 19 1 1 0 1 0 11
0 1 0 1 1 20 1 1 0 1 1 12
0 1 1 0 0 21 1 1 1 0 0 13
0 1 1 0 1 22 1 1 1 0 1 14
0 1 1 1 0 23 1 1 1 1 0 15
0 1 1 1 1 24 1 1 1 1 1 16
FUNCTION TABLE
Clock OSC Decode
In1 Set Reset Inh Inh Out 1 Out 2 Out
0 0 0 0 No
Change
0 0 0 0 Advance to
next state
X 1 0 0 0 0 1 1
X 0 1 0 0 0 1 0
X 0 0 1 0 No
Change
X 0 0 0 1 0 1 No
Change
0 0 0 0 X 0 1 No
Change
1 0 0 0 Advance to
next state
X = Dont Care
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332
RESET
2 8BYPASS
6
OSC INHIBIT
14
3 STAGES
STAGES STAGES
T 1 8 T 9 10 THRU 16 17 18 THRU 24
2 THRU 7 15
IN1 23
4 OUT 2 5
333
OUT 1 A 9
S B 10
C C 11 DECODER
Q D 12
MC14536B
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LOGIC DIAGRAM
En R
SET DECODER
1 OUT
7 13
CLOCK
INHIBIT
15 VDD = PIN 16
MONOIN VSS = PIN 8
MC14536B

(For Circuit Diagram See Figure 11 In Application)
8.0 100
VDD = 15 V VDD = 10 V
50
f AS A FUNCTION

4.0
20 OF RTC
(C = 1000 pF)
0 10
(RS 2RTC)
10 V 5.0
4.0
2.0 f AS A FUNCTION
OF C
8.0 1.0 (RTC = 56 k)
5.0 V
0.5 (RS = 120 k)
12
16 0.1
55 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
*Device Only. RTC, RESISTANCE (OHMS)
TA, AMBIENT TEMPERATURE (C)*
0.0001 0.001 0.01 0.1
C, CAPACITANCE (F)
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100 100
FORMULA FOR CALCULATING tW IN FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS: MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX CX 0.85 tW = 0.00247 RX CX 0.85
t W, PULSE WIDTH ( s)
WHERE R IS IN k, CX IN pF. WHERE R IS IN k, CX IN pF.

10 10
RX = 100 k RX = 100 k
50 k 50 k
1.0 10 k 1.0
5 k 10 k
TA = 25C 5 k TA = 25C
VDD = 5 V VDD = 10 V
0.1 0.1
1.0 10 100 1000 1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF) CX, EXTERNAL CAPACITANCE (pF)
Figure 3. Typical CX versus Pulse Width Figure 4. Typical CX versus Pulse Width
@ VDD = 5.0 V @ VDD = 10 V
100
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX CX 0.85
WHERE R IS IN k, CX IN pF.
10
RX = 100 k
50 k
1.0
10 k
5 k TA = 25C
VDD = 15 V
0.1
1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF)
Figure 5. Typical CX versus Pulse Width
@ VDD = 15 V
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334
MC14536B
VDD
0.01 F
500 F ID
CERAMIC
SET 20 ns 20 ns
RESET OUT 1
8BYPASS CL VDD
PULSE IN1 50%
IN1
GENERATOR tWL tWH
C INH SET
MONO IN OUT OUT 1
RESET 90%
OSC INH 2 OUT 50%
CL 8BYPASS 10%
A PULSE
IN1 tPLH tPHL
B GENERATOR
C INH tTLH tTHL
C DECODE MONO IN OUT
D OUT CL 2
OSC INH
VSS A
B
C DECODE
20 ns 20 ns D OUT CL
90% VSS
50%
10%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test Figure 7. Switching Time Test Circuit and Waveforms
Circuit and Waveform
FUNCTIONAL TEST SEQUENCE VDD
Test function (Figure 8) has been included for the SET

PULSE RESET OUT 1
reduction of test time required to exercise all 24 counter
GENERATOR 8BYPASS
stages. This test function divides the counter into three IN1
8stage sections and 255 counts are loaded in each of the C INH
8stage sections in parallel. All flipflops are now at a 1. MONO IN OUT
OSC INH 2
The counter is now returned to the normal 24stages in
A
series configuration. One more pulse is entered into In1
B
which will cause the counter to ripple from an all 1 state C DECODE
to an all 0 state. D OUT
VSS
Figure 8. Functional Test Circuit
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335
MC14536B
FUNCTIONAL TEST SEQUENCE

Inputs Outputs Comments
Decade Out
In1 Set Reset 8Bypass Q1 thru Q24 g are in Reset mode.
All 24 stages
1 0 1 1 0
1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.
0 1 1 1 0 First 1 to 0 transition of clock.
1
0
1 1 1 255 1 to 0 transitions are clocked in the counter.
0 1 1 1 1 The 255 1 to 0 transition.

0 0 0 0 1 Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from 1 to 0.
1 0 0 0 1 In1 Switches to a 1.
0 0 0 0 0 Counter Ripples from an all 1 state to an all 0 state.
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336
MC14536B
+V
16
6 VDD
8BYPASS
9 4
A OUT 1
10 B
11 C
12
D
2 OUT 2 5
RESET
14
OSC INH
15
MONOIN
PULSE 1
SET
GEN. 7
CLOCK INH
3 DECODE OUT 13
PULSE IN1
VSS
GEN.
CLOCK 8
IN1
SET
CLOCK INH
DECODE OUT
POWER UP
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20divided
output of IN1 can be obtained at OUT1 and OUT2.
Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions
(Divideby2 Configured)
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337
MC14536B
+V
16
6 VDD
8BYPASS
RX 9 4
A OUT 1
10 B
11 C
12
D
PULSE 2 5
RESET OUT 2
GEN. 1
SET
7
CLOCK INH
15
MONOIN
14
CLOCK INH
3 DECODE OUT 13
CLOCK IN1
VSS
CX 8
IN1
RESET
*tw .00247 RX CX0.85
DECODE OUT tw in sec

RX in k
CX in pF
*tw
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chips internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the MonoIn input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output
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338
MC14536B
+V
RS
16
6 VDD
8BYPASS
9 4
A OUT 1
10 B C
11 C
RTC
12
D
PULSE 2 5
RESET OUT 2
GEN. 14
SET
15
CLOCK INH
1
MONOIN
7
CLOCK INH
3 DECODE OUT 13
IN1
VSS
8
RESET
OUT 1
OUT 2
fosc ^ 2.3 R1tc C

DECODE OUT
Rs Rtc
F = Hz
tw R = Ohms
POWER UP
C = FARADS
NOTE: This circuit is designed to use the onchip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the OscInh input, the oscillator is
disabled. This puts the device in a lowcurrent standby condition. The rising edge of the Reset pulse
will cause the output to go low. This in turn causes OscInh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
for 2n/2 of the oscillators period. After the part times out, the output again goes high.
Figure 11. Time Interval Configuration Using OnChip RC Oscillator and

Reset Input to Initiate Time Interval
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339
MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable

multivibrator. It may be triggered from either edge of an input pulse, http://onsemi.com
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing MARKING
components, CX and RX. DIAGRAMS
16
Output Pulse Width = (Cx) (Rx) where: PDIP16
Rx is in k W P SUFFIX MC14538BCP
m CASE 648 AWLYYWW

Cx is in F 1
Unlimited Rise and Fall Time Allowed on the A Trigger Input SOIC16
16
14538B
Pulse Width Range = 10 s to 10 s D SUFFIX AWLYWW
CASE 751B
Latched Trigger Inputs 1
Separate Latched Reset Inputs TSSOP16
16
14
3.0 Vdc to 18 Vdc Operational Limits DT SUFFIX 538B
Triggerable from Positive (A Input) or NegativeGoing Edge
CASE 948F
1
ALYW
(BInput) 16
Capable of Driving Two Lowpower TTL Loads or One Lowpower 14538B
SOIC16
Schottky TTL Load Over the Rated Temperature Range DW SUFFIX
Pinforpin Compatible with MC14528B and CD4528B (CD4098) CASE 751G
AWLYYWW
Use the MC54/74HC4538A for Pulse Widths Less Than 10 s with
1
Supplies Up to 6 V. 16
SOEIAJ16
F SUFFIX MC14538B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) AWLYWW
CASE 966
WL or L = Wafer Lot
(DC or Transient) per Pin ORDERING INFORMATION
PD Power Dissipation, 500 mW Device Package Shipping
(8Second Soldering) MC14538BDT TSSOP16 96/Rail
may occur.
3. Temperature Derating: MC14538BDW SOIC16 47/Rail
highimpedance circuit. For proper operation, Vin and Vout should be constrained MC14538BFEL SOEIAJ16 See Note 1.
to the range VSS v
(Vin or Vout) vVDD. 1. For ordering information on the EIAJ version of
Unused inputs must always be tied to an appropriate logic voltage level (e.g., the SOIC packages, please contact your local

MC14538B
PIN ASSIGNMENT
VSS 1 16 VDD
CX/RXA 2 15 VSS
RESET A 3 14 CX/RXB
AA 4 13 RESET B
BA 5 12 AB
QA 6 11 BB
QA 7 10 QB
VSS 8 9 QB
BLOCK DIAGRAM
CX RX
VDD
1 2
A
4
Q1 6
B
5 Q1 7
RESET
CX RX
VDD
15 14
A
12
Q2 10
B
11 Q2 9
RESET
13
RX AND CX ARE EXTERNAL COMPONENTS.
VDD = PIN 16
VSS = PIN 8, PIN 1, PIN 15
ONESHOT SELECTION GUIDE
100 ns 1 s 10 s 100 s 1 ms 10 ms 100 ms 1s 10 s

MC14528B
MC14536B 23 HR
MC14538B
MC14541B 5 MIN.
MC4538A*
*LIMITED OPERATING VOLTAGE (2 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE
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MC14538B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
Input Current, Pin 2 or 14 Iin 15 0.05 0.00001 0.05 0.5 Adc
Input Current, Other Inputs Iin 15 0.1 0.00001 0.1 1.0 Adc
Input Capacitance, Pin 2 or 14 Cin 25 pF
Input Capacitance, Other Inputs Cin 5.0 7.5 pF
(Vin = 0)
(Per Package) 10 10 0.010 10 300
Q = Low, Q = High 15 20 0.015 20 600
Quiescent Current, Active State IDD 5.0 2.0 0.04 0.20 2.0 mAdc
(Both) (Per Package) 10 2.0 0.08 0.45 2.0
Q = High, Q = Low 15 2.0 0.13 0.70 2.0
Total Supply Current at an external IT 5.0 IT = (3.5 x 102) RXCXf + 4CXf + 1 x 105 CLf Adc
load capacitance (CL) and at 10 IT = (8.0 x 102) RXCXf + 9CXf + 2 x 105 CLf
external timing network (RX, CX) (5.) IT = (1.25 x 101) RXCXf + 12CXf + 3 x 105 CLf
where: IT in A (one monostable switching only),
where: CX in F, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
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MC14538B
VDD
Vdc Min
All Types
Typ (7.) Max Unit
tTLH = (1.35 ns/pF) CL + 33 ns 5.0 100 200
tTLH = (0.60 ns/pF) CL + 20 ns 10 50 100
tTLH = (0.40 ns/pF) CL + 20 ns 15 40 80
tTHL = (1.35 ns/pF) CL + 33 ns 5.0 100 200
tTHL = (0.60 ns/pF) CL + 20 ns 10 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 40 80
A or B to Q or Q tPHL
Reset to Q or Q ns
Input Rise and Fall Times tr, tf 5 15 s
Reset 10 5
15 4
B Input 5 300 1.0 ms
10 1.2 0.1
15 0.4 0.05
A Input 5
10 No Limit
15
Input Pulse Width tWH, 5.0 170 85 ns
A, B, or Reset tWL 10 90 45
15 80 40
Retrigger Time trr 5.0 0 ns
10 0
15 0
Output Pulse Width Q or Q T s
Refer to Figures 8 and 9
CX = 0.002 F, RX = 100 k 5.0 198 210 230
10 200 212 232
15 202 214 234
CX = 0.1 F, RX = 100 k 5.0 9.3 9.86 10.5 ms
10 9.4 10 10.6
15 9.5 10.14 10.7
CX = 10 F, RX = 100 k 5.0 0.91 0.965 1.03 s
10 0.92 0.98 1.04
15 0.93 0.99 1.06
Pulse Width Match between circuits in 100 5.0 1.0 5.0 %
the same package. [(T1 T2)/T1] 10 1.0 5.0
CX = 0.1 F, RX = 100 k 15 1.0 5.0
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MC14538B
OPERATING CONDITIONS
External Timing Resistance
External Timing Capacitance
RX
CX

5.0
0

No
(8.) k
F
Limit (9.)
8. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board
layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 M..
9. If CX > 15 F, use discharge protection diode per Fig. 11.
VDD VDD
P1
RX
2 (14) ENABLE
+ +
C1 C2
CX Vref1 Vref2 R Q 6 (10)
ENABLE OUTPUT
1 (15) LATCH
N1 S Q 7 (9)
VSS CONTROL
4 (12)
A
5 (11)
B
QR QR NOTE: Pins 1, 8 and 15 must
3 (13)
RESET S RESET LATCH R be externally grounded
Figure 1. Logic Diagram

(1/2 of DevIce Shown)
VDD
0.1 F
500 pF ID
CERAMIC
RX RX
VSS CX CX
VSS
Vin CX/RX
A
B Q
CL 20 ns 20 ns
RESET Q VDD
CL 90%
A Q
CL 10%
B Q Vin 0V
CL
RESET
VSS
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MC14538B
VDD
INPUT CONNECTIONS
RX RX *CL = 50 pF Characteristics Reset A B
CX CX tPLH, tPHL, tTLH, tTHL, VDD PG1 VDD
VSS VSS T, tWH, tWL
CX/RX tPLH, tPHL, tTLH, tTHL, VDD VSS PG2
PULSE A
T, tWH, tWL
GENERATOR B Q tPLH(R), tPHL(R), PG3 PG1 PG2
CL tWH, tWL
PULSE RESET Q
GENERATOR CL
A Q *Includes capacitance of probes, PG1 =
CL wiring, and fixture parasitic.
PULSE B Q
CL NOTE: Switching test waveforms PG2 =
GENERATOR RESET for PG1, PG2, PG3 are shown
VSS In Figure 4. PG3 =
Figure 3. Switching Test Circuit
90%
50% 10% 50% VDD
A
tWH tTLH tTHL
tTHL tTLH
B
50% 90% VDD
10%
tWL
tTHL tPHL
RESET
90% VDD
50%
10%
tWL
tPLH tTHL tTLH
T
tPLH tPHL trr
90%
50% 50% 50% 10% 50%
Q
tTLH tTHL
tPHL tPHL tPLH
Q 90%
50% 50% 50% 50%
10%
Figure 4. Switching Test Waveforms

WITH RESPECT TO VALUE AT VDD = 10 V (%)
RELATIVE FREQUENCY OF OCCURRENCE
TA = 25C
NORMALIZED PULSE WIDTH CHANGE
RX = 100 k 0% POINT PULSE WIDTH RX = 100 k

CX = 0.1 F VDD = 5.0 V, T = 9.8 ms CX = 0.1 F
1.0 VDD = 10 V, T = 10 ms 2
VDD = 15 V, T = 10.2 ms
0.8 1
0
0.6 1
0.4 2
0.2
0
4 2 0 2 4 5 6 7 8 9 10 11 12 13 14 15
T, OUTPUT PULSE WIDTH (%) VDD, SUPPLY VOLTAGE (VOLTS)
Figure 5. Typical Normalized Distribution Figure 6. Typical Pulse Width Variation as

of Units for Output Pulse Width a Function of Supply Voltage VDD
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MC14538B
1000 FUNCTION TABLE

Inputs Outputs
TOTAL SUPPLY CURRENT ( A)
RX = 100 k, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY Reset A B Q Q
100
H H
H L
VDD = 15 V
10 5.0 V H L Not Triggered
10 V H H Not Triggered
H L, H, H Not Triggered
H L L, H, Not Triggered
1.0
L X X L H
X X Not Triggered
0.1
0.001 0.1 1.0 10 100
OUTPUT DUTY CYCLE (%)
Figure 7. Typical Total Supply Current

versus Output Duty Cycle
WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)

RX = 100 k
CX = .002 F
RX = 100 k 3.0
TYPICAL NORMALIZED ERROR
TYPICAL NORMALIZED ERROR

CX = 0.1 F VDD = 15 V
2 2.0
1 1.0 VDD = 15 V
VDD = 10 V
0 0
VDD = 5 V VDD = 10 V
1 1.0
2 2.0
VDD = 5.0 V
3.0
60 40 20 0 20 40 60 80 100 120 140 60 40 20 0 20 40 60 80 100 120 140

TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C)
Figure 8. Typical Error of Pulse Width Figure 9. Typical Error of Pulse Width
Equation versus Temperature Equation versus Temperature
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MC14538B
THEORY OF OPERATION
1 3 4
A
2
RESET
Vref 2 Vref 2 Vref 2 Vref 2

CX/RX Vref 1 Vref 1 Vref 1 Vref 1
T T T
1 Positive edge trigger 4 Positive edge retrigger (pulse lengthening)

2 Negative edge trigger 5 Positive edge retrigger (pulse lengthening)
3 Positive edge trigger
Figure 10. Timing Operation
TRIGGER OPERATION RETRIGGER OPERATION

The block diagram of the MC14538B is shown in The MC14538B is retriggered if a valid trigger occurs
Figure 1, with circuit operation following. followed by another valid trigger before the Q output has
As shown in Figure 1 and 10, before an input trigger returned to the quiescent (zero) state. Any retrigger, after the
occurs, the monostable is in the quiescent state with the Q timing node voltage at pin 2 or 14 has begun to rise from
output low, and the timing capacitor CX completely charged Vref 1, but has not yet reached Vref 2, will cause an increase
to VDD. When the trigger input A goes from VSS to VDD in output pulse width T. When a valid retrigger is initiated
(while inputs B and Reset are held to VDD) a valid trigger is , the voltage at CX/RX will again drop to Vref 1 before
recognized, which turns on comparator C1 and Nchannel progressing along the RC charging curve toward VDD. The
transistor N1 . At the same time the output latch is set. With Q output will remain high until time T, after the last valid
transistor N1 on, the capacitor CX rapidly discharges toward retrigger.
VSS until Vref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off. RESET OPERATION
Comparator C1 then turns off while at the same time The MC14538B may be reset during the generation of the
comparator C2 turns on. With transistor N1 off, the capacitor output pulse. In the reset mode of operation, an input pulse
CX begins to charge through the timing resistor, RX, toward on Reset sets the reset latch and causes the capacitor to be
VDD. When the voltage across CX equals Vref 2, comparator fast charged to VDD by turning on transistor P1 . When the
C2 changes state, causing the output latch to reset (Q goes voltage on the capacitor reaches Vref 2, the reset latch will
low) while at the same time disabling comparator C2 . This clear, and will then be ready to accept another pulse. It the
ends at the timing cycle with the monostable in the quiescent Reset input is held low, any trigger inputs that occur will be
state, waiting for the next trigger. inhibited and the Q and Q outputs of the output latch will not
In the quiescent state, CX is fully charged to VDD causing change. Since the Q output is reset when an input low level
the current through resistor RX to be zero. Both comparators is detected on the Reset input, the output pulse T can be made
are off with total device current due only to reverse significantly shorter than the minimum pulse width
junction leakages. An added feature of the MC14538B is specification.
that the output latch is set via the input trigger without regard POWERDOWN CONSIDERATIONS
to the capacitor voltage. Thus, propagation delay from Large capacitance values can cause problems due to the
trigger to Q is independent of the value of CX, RX, or the duty large amount of energy stored. When a system containing
cycle of the input waveform.
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MC14538B
the MC14538B is powered down, the capacitor voltage may Dx

discharge from VDD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should Cx Rx VDD
VSS
be limited to 10 mA and therefore the discharge time of the
VDD supply must not be faster than (VDD). (C) / (10 mA). VDD
For example, if VDD = 10 V and CX = 10 F, the VDD supply
should discharge no faster than (10 V) x (10 F) / (10 mA) Q
= 10 ms. This is normally not a problem since power
supplies are heavily filtered and cannot discharge at this rate. Q
When a more rapid decrease of VDD to zero volts occurs, RESET
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11. Figure 11. Use of a Diode to Limit
Power Down Current Surge
CX RX CX RX
RISINGEDGE VDD
VDD
TRIGGER
A Q RISINGEDGE
A Q
TRIGGER
B Q B Q
B = VDD
RESET = VDD RESET = VDD
CX RX CX RX
A = VSS VDD VDD
Q A Q
B Q B Q
FALLINGEDGE
FALLINGEDGE TRIGGER
TRIGGER
RESET = VDD RESET = VDD
Figure 12. Retriggerable Figure 13. NonRetriggerable

Monostables Circuitry Monostables Circuitry
NC
Q NC
A
B Q NC
CD
VDD
VDD
Figure 14. Connection of Unused Sections
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MC14541B
Programmable Timer
The MC14541B programmable timer consists of a 16stage binary
counter, an integrated oscillator for use with an external capacitor and
two resistors, an automatic poweron reset circuit, and output control
logic.
Timing is initialized by turning on power, whereupon the poweron
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reset is enabled and initializes the counter, within the specified VDD
range. With the power already on, an external reset pulse can be MARKING
applied. Upon release of the initial reset command, the oscillator will DIAGRAMS
14
oscillate with a frequency determined by the external RC network. The PDIP14
16stage counter divides the oscillator frequency (fosc) with the nth P SUFFIX MC14541BCP
AWLYYWW
stage frequency being fosc/2n. CASE 646
1
Available Outputs 28, 210, 213 or 216 14
Increments on Positive Edge Clock Transitions SOIC14
D SUFFIX
14541B
AWLYWW
Builtin Low Power RC Oscillator ( 2% accuracy over temperature CASE 751A
1
range and 20% supply and 3% over processing at < 10 kHz) 14
Oscillator May Be Bypassed if External Clock Is Available (Apply TSSOP14 14
DT SUFFIX 541B
external clock to Pin 3) CASE 948G ALYW
External Master Reset Totally Independent of Automatic Reset 1
Operation 14
SOEIAJ14
Operates as 2n Frequency Divider or Single Transition Timer F SUFFIX MC14541B
Q/Q Select Provides Output Logic Level Flexibility CASE 965 AWLYWW
Reset (auto or master) Disables Oscillator During Resetting to A

1
= Assembly Location
Provide No Active Power Dissipation WL or L = Wafer Lot
Clock Conditioning Circuit Permits Operation with Very Slow Clock YY or Y = Year
Rise and Fall Times WW or W = Work Week
Automatic Reset Initializes All Counters On Power Up ORDERING INFORMATION

Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset Device Package Shipping
Supply Voltage Range = Disabled (Pin 5 = VDD)
Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset MC14541BCP PDIP14 2000/Box
Supply Voltage Range = Enabled (Pin 5 = VSS) MC14541BD SOIC14 55/Rail
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) MC14541BDR2 SOIC14 2500/Tape & Reel
(DC or Transient) MC14541BF SOEIAJ14 See Note 1.
Iin Input Current (DC or Transient) 10 (per Pin) mA MC14541BFEL SOEIAJ14 See Note 1.
Iout Output Current (DC or Transient) 45 (per Pin) mA 1. For ordering information on the EIAJ version of
TA Ambient Temperature Range 55 to +125 C against damage due to high static voltages or electric
TL Lead Temperature 260 C voltages to this highimpedance circuit. For proper
(8Second Soldering) operation, Vin and Vout should be constrained to the
(Vin or Vout) VDD.

MC14541B
PIN ASSIGNMENT
Rtc 1 14 VDD
Ctc 2 13 B
RS 3 12 A
NC 4 11 NC
AR 5 10 MODE
MR 6 9 Q/Q SEL
VSS 7 8 Q
NC = NO CONNECTION

VDD 55_C 25_C 125_C
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 7.96 6.42 12.83 4.49
(VOH = 9.5 Vdc) 10 4.19 3.38 6.75 2.37
(VOH = 13.5 Vdc) 15 16.3 13.2 26.33 9.24
(VOL = 0.5 Vdc) 10 4.96 4.0 8.0 2.8
(VOL = 1.5 Vdc) 15 19.3 15.6 31.2 10.9
(Vin = 0)
(Pin 5 is High) 10 10 0.010 10 300
Auto Reset Disabled 15 20 0.015 20 600
Auto Reset Quiescent Current IDDR 10 250 30 250 1500 Adc
(Pin 5 is low) 15 500 82 500 2000
Supply Current (5.) (6.) ID 5.0 ID = (0.4 A/kHz) f + IDD Adc
(Dynamic plus Quiescent) 10 ID = (0.8 A/kHz) f + IDD
15 ID = (1.2 A/kHz) f + IDD
6. When using the on chip oscillator the total supply current (in Adc) becomes: IT = ID + 2 Ctc VDD f x 103 where ID is in A, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during poweron with automatic reset enabled is typically 50 A @ VDD = 10 Vdc.
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MC14541B

Characteristic
Symbol
tTLH,
ns
Propagation Delay, Clock to Q (28 Output) tPLH s
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns tPHL 5.0 3.5 10.5
Propagation Delay, Clock to Q (216 Output) tPHL s
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPLH 5.0 6.0 18
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns 10 3.5 10
10 300 100
15 225 85
Clock Pulse Frequency (50% Duty Cycle) fcl 5.0 1.5 0.75 MHz
10 4.0 2.0
15 6.0 3.0
MR Pulse Width tWH(R) 5.0 900 300 ns
10 300 100
15 225 85
Master Reset Removal Time trem 5.0 420 210 ns
10 200 100
15 200 100
VDD VDD
PULSE PULSE
RS RS
GENERATOR GENERATOR
AR AR
Q/Q SELECT Q/Q SELECT
MODE Q MODE Q
A CL A CL
B B
MR MR
VSS VSS
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN) 20 ns 20 ns
90% 50%
50%
20 ns 20 ns RS 10%
tPLH tPHL
90% 50%
10% 50% 90%
50%
50% Q 10%
DUTY CYCLE tTLH tTHL
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MC14541B
EXPANDED BLOCK DIAGRAM
A 12
B 13
1 OF 4
MUX
8 Q
Rtc 1 210 213 216
8STAGE 8
Ctc 2 OSC C 2 C 8STAGE
COUNTER
RS 3 RESET COUNTER
RESET RESET
AUTO RESET POWERON

5
RESET
6 10 9
MASTER RESET MODE Q/Q
SELECT
VDD = PIN 14
VSS = PIN 7
FREQUENCY SELECTION TABLE TRUTH TABLE

Number of State
Counter Stages Count
Pin 0 1
A B n 2n
Auto Reset, 5 Auto Reset Auto Reset Disabled
0 0 13 8192
Operating
0 1 10 1024
Master Reset, 6 Timer Operational Master Reset On
1 0 8 256
Q / Q, 9 Output Initially Low Output Initially High
1 1 16 65536 After Reset After Reset
Mode, 10 Single Cycle Mode Recycle Mode
3
TO CLOCK
CIRCUIT
INTERNAL
RESET
2 1
Ctc
RS RTC
Figure 3. Oscillator Circuit Using RC Configuration
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MC14541B
8.0 100
VDD = 10 V
VDD = 15 V 50
4.0
f AS A FUNCTION

20
OF RTC
0 10 (C = 1000 pF)
(RS 2RTC)
10 V 5.0
4.0 f AS A FUNCTION
2.0 OF C
8.0 (RTC = 56 k)
5.0 V 1.0
(RS = 120 k)
0.5
12
16 0.1
55 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 m
TA, AMBIENT TEMPERATURE (C) RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
Figure 4. RC Oscillator Stability C, CAPACITANCE (F)
Figure 5. RC Oscillator Frequency as a

Function of Rtc and Ctc
With Auto Reset pin set to a 0 the counter circuit is when B is 0, normal counting is interrupted and the 9th
initialized by turning on power. Or with power already on, counter stage receives its clock directly from the oscillator
the counter circuit is reset when the Master Reset pin is set (i.e., effectively outputting 28).
to a 1. Both types of reset will result in synchronously The Q/Q select output control pin provides for a choice of
resetting all counter stages independent of counter state. output level. When the counter is in a reset condition and
Auto Reset pin when set to a 1 provides a low power Q/Q select pin is set to a 0 the Q output is a 0,
operation. correspondingly when Q/Q select pin is set to a 1 the Q
The RC oscillator as shown in Figure 3 will oscillate with output is a 1.
a frequency determined by the external RC network i.e., When the mode control pin is set to a 1, the selected
f=
1
2.3 RtcCtc
if (1 kHz v f v 100 kHz) count is continually transmitted to the output. But, with
mode pin 0 and after a reset condition the RS flipflop (see
Expanded Block Diagram) resets, counting commences,
and RS 2 Rtc where RS 10 k and after 2n1 counts the RS flipflop sets which causes the
The time select inputs (A and B) provide a twobit address output to change state. Hence, after another 2n1 counts the
to output any one of four counter stages (28, 210, 213 and output will not change. Thus, a Master Reset pulse must be
216). The 2n counts as shown in the Frequency Selection applied or a change in the mode pin level is required to reset
Table represents the Q output of the Nth stage of the counter. the single cycle operation.
When A is 1, 216 is selected for both states of B. However,
DIGITAL TIMER APPLICATION
Rtc When Master Reset (MR) receives a positive pulse, the

1 14 VDD internal counters and latch are reset. The Q output goes high
Ctc
2 13 B and remains high until the selected (via A and B) number of
3 12 A clock pulses are counted, the Q output then goes low and
RS
NC 4 11 N.C. remains low until another input pulse is received.
AR MODE This one shot is fully retriggerable and as accurate as the
5 10
MR
6 9
Q/Q
VDD
input frequency. An external clock can be used (pin 3 is the
INPUT clock input, pins 1 and 2 are outputs) if additional accuracy
7 8
OUTPUT is needed.
tMR Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.
t + tMR
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353
MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
designed for use with liquid crystal readouts, and is constructed with http://onsemi.com
complementary MOS (CMOS) enhancement mode devices. The
circuit provides the functions of a 4bit storage latch and an 8421 MARKING
BCDtoseven segment decoder and driver. The device has the DIAGRAMS
capability to invert the logic levels of the output combination. The 16
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to PDIP16
reverse the truth table phase, blank the display, and store a BCD code, P SUFFIX MC14543BCP
AWLYYWW
respectively. For liquid crystal (LC) readouts, a square wave is applied CASE 648
to the Ph input of the circuit and the electrically common backplane of 1
the display. The outputs of the circuit are connected directly to the 16
segments of the LC readout. For other types of readouts, such as SOIC16
14543B
lightemitting diode (LED), incandescent, gas discharge, and D SUFFIX AWLYWW
fluorescent readouts, connection diagrams are given on this data sheet. CASE 751B
Applications include instrument (e.g., counter, DVM etc.) display 1
driver, computer/calculator display driver, cockpit display driver, and 16
various clock, watch, and timer uses. SOEIAJ16
F SUFFIX MC14543B
Latch Storage of Code CASE 966 AWLYWW
Blanking Input 1
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability WL or L = Wafer Lot
Supply Voltage Range = 3.0 V to 18 V YY or Y = Year
Capable of Driving 2 Lowpower TTL Loads, 1 Lowpower Schottky WW or W = Work Week
TTL Load or 2 HTL Loads Over the Rated Temperature Range

PinforPin Replacement for CD4056A (with Pin 7 Tied to VSS). ORDERING INFORMATION
Chip Complexity: 207 FETs or 52 Equivalent Gates
Vin Input Voltage Range, All Inputs 0.5 to VDD + 0.5 V
Iin DC Input Current per Pin 10 mA MC14543BF SOEIAJ16 See Note 1.
PD Power Dissipation, 500 mW MC14543BFEL SOEIAJ16 See Note 1.

TA Operating Temperature Range 55 to +125 C the SOIC packages, please contact your local
IOHmax Maximum Continuous Output 10 mA This device contains protection circuitry to guard
IOLmax Drive Current (Source or Sink) (per Output) against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
POHmax Maximum Continuous Output 70 mW
POLmax Power (Source or Sink) (4.) (per Output)
voltages to this highimpedance circuit. For proper
2. Maximum Ratings are those values beyond which damage to the device operation, Vin and Vout should be constrained to the
may occur. range VSS v v
(Vin or Vout) VDD.
3. Temperature Derating: Unused inputs must always be tied to an appropriate
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C logic voltage level (e.g., either VSS or VDD). Unused out-
4. POHmax = IOH (VOH VDD) and POLmax = IOL (VOL VSS) puts must be left open.

MC14543B
PIN ASSIGNMENT
LD 1 16 VDD
C 2 15 f
B 3 14 g
D 4 13 e
A 5 12 d
PH 6 11 c
BI 7 10 b
VSS 8 9 a
TRUTH TABLE
Inputs Outputs
LD BI Ph* D C B A a b c d e f g Display
X 1 0 X X X X 0 0 0 0 0 0 0 Blank
1 0 0 0 0 0 0 1 1 1 1 1 1 0 0
1 0 0 0 0 0 1 0 1 1 0 0 0 0 1
1 0 0 0 0 1 0 1 1 0 1 1 0 1 2
1 0 0 0 0 1 1 1 1 1 1 0 0 1 3
1 0 0 0 1 0 0 0 1 1 0 0 1 1 4
1 0 0 0 1 0 1 1 0 1 1 0 1 1 5
1 0 0 0 1 1 0 1 0 1 1 1 1 1 6
1 0 0 0 1 1 1 1 1 1 0 0 0 0 7
1 0 0 1 0 0 0 1 1 1 1 1 1 1 8
1 0 0 1 0 0 1 1 1 1 1 0 1 1 9
1 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank
0 0 0 X X X X ** **
Inverse of Output Display
Combinations as above
Above
X = Dont care
= Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
** = Depends upon the BCD code previously applied when LD = 1
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MC14543B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (5.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 0.5 Vdc) 10 10.1
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 9.5 Vdc) 10 10.1
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
Iout = 0 A 15 20 0.015 20 600
buffers switching)
Noise Margin for both 1 and 0 level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency.
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MC14543B
Output Rise Time

tTLH
VDD Min Typ Max Unit
ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 100 200
tTLH = (1.5 ns/pF) CL + 15 ns 10 50 100
tTLH = (1.1 ns/pF) CL + 10 ns 15 40 80
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTHL = (0.55 ns/pF) CL + 12.5 ns 15 40 80
TurnOff Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 520 ns 5.0 605 1210
tPLH = (0.66 ns/pF) CL + 217 ns 10 250 500
tPLH = (0.5 ns/pF) CL + 160 ns 15 185 370
TurnOn Delay Time tPHL ns
tPHL = (1.7 ns/pF) CL + 420 ns 5.0 505 1650
tPHL = (0.66 ns/pF) CL + 172 ns 10 205 660
tPHL = (0.5 ns/pF) CL + 130 ns 15 155 495
10 450
15 500
10 30
15 20
Latch Disable Pulse Width (Strobing Data) tWH 5.0 250 125 ns
10 100 50
15 80 40
LOGIC DIAGRAM
BI 7
VDD = PIN 16
VSS = PIN 8
9 a
A 5
10 b
B 3 11 c
12 d
13 e
C 2
15 f
14 g
D 4
LD 1 PHASE 6
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MC14543B
0 24
VDD = 5.0 Vdc VDD = 15 Vdc

POHmax = 70 mWdc
IOH, SOURCE CURRENT (mAdc)
IOL , SINK CURRENT (mAdc)

6.0 18
VDD = 10 Vdc VDD = 10 Vdc

12 12
18 6.0
VDD = 15 Vdc VDD = 5.0 Vdc POLmax = 70 mWdc
VSS = 0 Vdc VSS = 0 Vdc
24 0
16 12 8.0 4.0 0 0 4.0 8.0 12 16
(VOH VDD), SOURCE DEVICE VOLTAGE (Vdc) (VOL VSS), SINK DEVICE VOLTAGE (Vdc)

Characteristics Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns 20 ns
VDD
C 90%
50%
10% VSS
tPHL tPLH
VOH
90% 50%
g 10% VOL
tTHL tTLH
(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
VDD
LD 90%
50%
10% VSS
tsu
Inputs BI and Ph low, and Inputs D and LD high. th
VDD
f in respect to a system clock. C 50% 50%
VSS
VOH
20 ns 20 ns g
VDD VOL
A, B, AND C 90% 50%
10% 1 VSS
2f (c) Data DCBA strobed into latches
50% DUTY CYCLE
VDD
VOH LD 50%
ANY OUTPUT VSS
VOL tWH
Figure 3. Dynamic Power Dissipation Figure 4. Dynamic Signal Waveforms

Signal Waveforms
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MC14543B
LIQUID CRYSTAL (LC) READOUT INCANDESCENT READOUT
APPROPRIATE
MC14543B ONE OF SEVEN SEGMENTS VOLTAGE
OUTPUT
Ph COMMON
BACKPLANE
MC14543B
SQUARE WAVE OUTPUT
(VSS TO VDD) Ph
VSS
LIGHT EMITTING DIODE (LED) READOUT GAS DISCHARGE READOUT

APPROPRIATE
VDD VOLTAGE
COMMON COMMON
CATHODE LED ANODE LED
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
MC14543B
Ph
VSS OUTPUT
Ph
VDD
NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or Iout 10 mA). VSS
CONNECTIONS TO SEGMENTS
a
f g b
e c
d
VDD = PIN 16
VSS = PIN 8
DISPLAY
0 1 2 3 4 5 6 7 8 9
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MC14549B, MC14559B
Successive Approximation
Registers
The MC14549B and MC14559B successive approximation
registers are 8bit registers providing all the digital control and storage
necessary for successive approximation analogtodigital conversion
systems. These parts differ in only one control input. The Master Reset http://onsemi.com
(MR) on the MC14549B is required in the cascaded mode when more
than 8 bits are desired. The Feed Forward (FF) of the MC14559B is
used for register shortening where EndofConversion (EOC) is MARKING
required after less than eight cycles. DIAGRAMS
Applications for the MC14549B and MC14559B include 16
analogtodigital conversion, with serial and parallel outputs. PDIP16
P SUFFIX MC145XXBCP
Totally Synchronous Operation CASE 648 AWLYYWW
Single Supply Operation
Serial Output
Retriggerable
16
Compatible with a Variety of Digital and Analog Systems such as the SOIC16 145XXB
MC1408 8Bit D/A Converter DW SUFFIX
All Control Inputs PositiveEdge Triggered CASE 751G
AWLYYWW
Capable of Driving 2 LowPower TTL Loads, 1 LowPower Schottky 1
TTL Load or 2 HTL Loads Over the Rated Temperature Range

Chip Complexity: 488 FETs or 122 Equivalent Gates
WL or L = Wafer Lot
YY or Y = Year
Vin Input Voltage Range, All Inputs 0.5 to VDD + 0.5 V
Iin DC Input Current, per Pin 10 mA Device Package Shipping

PD Power Dissipation, 500 mW MC14549BCP PDIP16 25/Rail
Tstg Storage Temperature Range 65 to +150 C MC14559BCP PDIP16 25/Rail
1. Maximum Ratings are those values beyond which damage to the device MC14559BDWR2 SOIC16 1000/Tape & Reel
may occur.
either VSS or VDD).

MC14549B, MC14559B
PIN ASSIGNMENT
Q4 1 16 VDD
Q5 2 15 Q3
Q6 3 14 Q2
Q7 4 13 Q1
Sout 5 12 Q0
D 6 11 EOC
C 7 10 *
VSS 8 9 SC
*For MC14549B Pin 10 is MR input.

For MC14559B Pin 10 is FF input.
TRUTH TABLES
MC14549B MC14559B
SC SC(t1) MR MR(t1) Clock Action SC SC(t1) EOC Clock Action
X X X X None X X X None
X X 1 X Reset 1 0 0 Start
1 0 0 0 Start Conversion
Conversion X 1 0 Continue
1 X 0 1 Start Conversion
Conversion 0 0 0 Continue
1 1 0 0 Continue Conversion
Conversion 0 X 1 Retain
0 X 0 X Continue Conversion
Previous Result
Operation 1 X 1 Start
X = Dont Care t1 = State at Previous Clock Conversion
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MC14549B, MC14559B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
Input Voltage (3.) 0 Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) 5.0 0.25 0.2 0.36 0.14
(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1
(VOL = 0.5 Vdc) Q Outputs 10 3.2 2.6 4.5 1.8
(VOL = 1.5 Vdc) 15 8.4 6.8 17.6 4.8
(VOL = 0.4 Vdc) Sink 5.0 0.64 0.51 0.88 0.36 mAdc
(VOL = 0.5 Vdc) Pin 5, 11 only 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Per Package) 10 10 0.010 10 300
(Clock = 0 V, 15 20 0.015 20 600
Other Inputs = VDD
or 0 V, Iout = 0 A)
buffers switching)
Noise Margin for both 1 and 0 level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
IT(CL) = IT(50 pF) + 3.5 x 103 (CL = 50) VDDf
where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency.
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MC14549B, MC14559B
Output Rise Time

tTLH
VDD Min Typ Max Unit
ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 65 130
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Clock to Q tPHL
Clock to Sout
Clock to EOC
SC, D, FF or MR Setup Time tsu 5.0 250 125 ns
10 100 50
15 80 40
10 270 135
15 200 100
Pulse Width D, SC, FF or MR tWH 5.0 500 250 ns
10 200 100
15 160 80
Clock Rise and Fall Time tTLH, 5.0 15 s
tTHL 10 1.0
15 0.5
10 3.0 1.5
15 4.0 2.0
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MC14549B, MC14559B
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VDD
Q7
Q6
C CL
Q5
CL
Q4
SC CL
PROGRAMMABLE Q3
PULSE CL
Q2
GENERATOR FF(MR) CL
Q1
CL
Q0 CL
D
EOC
CL
Sout CL
CL 1
VSS fcl
tWH(cl)
50%
C
tsu
50%
SC
tsu tsu tWH(D)
D
50%
tPLH tPHL
50% 90% 10%
Q7
tTLH tTHL tPLH
50% 90%
Sout 10%
tTLH
NOTE: Pin 10 = VSS
TIMING DIAGRAM
CLOCK
SC
D
Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

EOC

Sout INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH
Dont care condition

INH Indicates Serial Out is inhibited low.
* Q8 is ninthbit of serial information available from 8bit register.
NOTE: Pin 10 = VSS
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MC14549B, MC14559B
Both the MC14549B and MC14559B can be operated in conversion, tie Q1 to FF; the part will respond as shown in
either the free run or strobed operation mode for the timing diagram less two bit times. Not that Q1 and Q0
conversion schemes with any number of bits. Reliable will still operate and must be disregarded.
cascading and/or recirculating operation can be achieved if For 8bit operation, FF is tied to VSS.
the End of Convert (EOC) output is used as the controlling For applications with more than 8 but less than 16 bits, use
function, since with EOC = 0 (and with SC = 1 for the basic connections shown in Figure 1. The FF input of the
MC14549B but either 1 or 0 for MC14559B) no stable state MC14559B is used to shorten the setup. Tying FF directly
exists under continual clocked operation. The MC14559B to the least significant bit used in the MC14559B allows
will automatically recirculate after EOC = 1 during EOC to provide the cascading signal, and results in smooth
externally strobed operation, provided SC = 1. transition of serial information from the MC14559B to the
All data and control inputs for these devices are triggered MC14549B. The Serial Out (Sout) inhibit structure of the
into the circuit on the positive edge of the clock pulse. MC14559B remains inactive one cycle after EOC goes high,
Operation of the various terminals is as follows: while Sout of the MC14549B remains inhibited until the
C = Clock A positivegoing transition of the Clock is second clock cycle of its operation.
required for data on any input to be strobed into the circuit. Qn = Data Outputs After a conversion is initiated the
SC = Start Convert A conversion sequence is initiated Qs on succeeding cycles go high and are then conditionally
on the positivegoing transition of the SC input on reset dependent upon the state of the D input. Once
succeeding clock cycles. conditionally reset they remain in the proper state until the
D = Data in Data on this input (usually from a circuit is either reset or reinitiated.
comparator in A/D applications) is also entered into the EOC = End of Convert This output goes high on the
circuit on a positivegoing transition of the clock. This input negativegoing transition of the clock following FF = 1 (for
is Schmitt triggered and synchronized to allow fast response the MC14559B) or the conditional reset of Q0. This allows
and guaranteed quality of serial and parallel data. settling of the digital circuitry prior to the End of Conversion
MR = Master Reset (MC14549B Only) Resets all indication. Therefore either level or edge triggering can
output to 0 on positivegoing transitions of the clock. If indicate complete conversion.
removed while SC = 0, the circuit will remain reset until SC Sout = Serial Out Transmits conversion in serial
= 1. This allows easy cascading of circuits. fashion. Serial data occurs during the clock period when the
FF = Feed Forward (MC14559B Only) Provides corresponding parallel data bit is conditionally reset. Serial
register shortening by removing unwanted bits from a Out is inhibited on the initial period of a cycle, when the
system. circuit is reset, and on the second cycle after EOC goes high.
For operation with less than 8 bits, tie the output following This provides efficient operation when cascaded.
the least significant bit of the circuit to EOC. E.g., for a 6bit
FROM A/D EXTERNAL 1/4 MC14001

COMPARATOR CLOCK
SERIAL OUT
(CONTINUAL
UPDATE EVERY
D Sout D Sout
C C 13 CLOCK CYCLES)
SC MC14559B SC MC14549B
* FF MR
Q7 Q6 Q5 Q4 Q0 EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
** {
NC
MSB LSB
TO D/A AND PARALLEL DATA
TO D/A AND
PARALLEL DATA
FREE RUN MODE
EXTERNAL STROBE
* FF allows EOC to activate as if in 4stage register.
** Cascading using EOC guaranteed; no stable unfunctional state.
Completion of conversion automatically reinitiates cycle in free run mode.
Figure 1. 12Bit Conversion Scheme
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MC14549B, MC14559B
Externally Controlled 6Bit ADC (Figure 2) Continuously Cycling 12Bit ADC (Figure 4)
Several features are shown in this application: Because each successive approximation register (SAR)
Shortening of the register to six bits by feeding the has a capability of handling only an eightbit word, two
seventh output bit into the FF input. must be cascaded to make an ADC with more than eight bits.
Continuous conversion, if a continuous signal is applied When it is necessary to cascade two SARs, the second
to SC. SAR must have a stable resettable state to remain in while
Externally controlled updating (the start pulse must be awaiting a subsequent start signal. However, the first stage
shorter than the conversion cycle). must not have a stable resettable state while recycling,
The EOC output indicating that the parallel data are valid because during switchon or due to outside influences, the
and that the serial output is complete. first stage has entered a reset state, the entire ADC will
remain in a stable nonfunctional condition.
Continuously Cycling 8Bit ADC (Figure 3) This 12bit ADC is continuously recycling. The serial as
This ADC is running continuously because the EOC well as the parallel outputs are updated every thirteenth
signal is fed back to the SC input, immediately initiating a clock pulse. The EOC pulse indicates the completion of the
new cycle on the next clock pulse. 12bit conversion cycle, the end of the serial output word,
and the validity of the parallel data output.
C
SC
MC14559B Sout
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
Figure 2. Externally Controlled 6Bit ADC
C
SC
MC14559B Sout
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
Figure 3. Continuously Cycling 8Bit ADC
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MC14549B, MC14559B
Sout
C Sout C
SC SC Sout
MC14559B MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
TO DAC TO DAC
EOC
Figure 4. Continuously Cycling 12Bit ADC
Externally Controlled 12Bit ADC (Figure 5) Additional Motorola Parts for Successive
In this circuit the external pulse starts the first SAR and Approximation ADC
simultaneously resets the cascaded second SAR. When Q4 Monolithic digitaltoanalog converters The
of the first SAR goes high, the second SAR starts MC1408/1508 converter has eightbit resolution and is
conversion, and the first one stops conversion. EOC available with 6, 7, and 8bit accuracy. The
indicates that the parallel data are valid and that the serial amplifiercomparator block The MC1407/1507
output is complete. Updating the output data is started with contains a high speed operational amplifier and a high speed
every external control pulse. comparator with adjustable window.
With these two linear parts it is possible to construct
SAADCs with an accuracy of up to eight bits, using as the
register one MC14549B or one MC14559B. An additional
CMOS block will be necessary to generate the clock
frequency.
Additional information on successive approximation
ADC is found in Motorola Application Note AN716.
C Sout C
SC SC Sout
MC14559B MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
TO DAC TO DAC
EOC Sout
Figure 5. Externally Controlled 12Bit ADC
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MC14551B
Quad 2-Channel Analog

Multiplexer/Demultiplexer
The MC14551B is a digitallycontrolled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved. http://onsemi.com
Triple Diode Protection on All Control Inputs

MARKING
DIAGRAMS
Analog Voltage Range (VDD VEE) = 3.0 to 18 V
Note: VEE must be VSS v PDIP16
16
Linearized Transfer Characteristics P SUFFIX MC14551BCP

AWLYYWW
Low Noise 12 nVCycle, f 1.0 kHz typical CASE 648
For Low RON, Use The HC4051, HC4052, or HC4053 HighSpeed

1
CMOS Devices 16
Switch Function is Break Before Make SOIC16
14551B
D SUFFIX AWLYWW
CASE 751B
1
MAXIMUM RATINGS (2.) 16

F SUFFIX MC14551B
VDD DC Supply Voltage Range 0.5 to + 18.0 V CASE 966 AWLYWW
(Referenced to VEE, VSS VEE)
1
Vin, Vout Input or Output Voltage (DC or 0.5 to VDD + 0.5 V
Transient) (Referenced to VSS for A = Assembly Location
Control Input & VEE for Switch I/O) WL or L = Wafer Lot
Iin Input Current (DC or Transient), 10 mA YY or Y = Year
per Control Pin WW or W = Work Week
Isw Switch Through Current 25 mA

PD Power Dissipation, per Package (3.) 500 mW ORDERING INFORMATION
TA Ambient Temperature Range 55 to + 125 _C Device Package Shipping
Tstg Storage Temperature Range 65 to + 150 _C MC14551BCP PDIP16 2000/Box
TL Lead Temperature 260 _C MC14551BD SOIC16 48/Rail
(8Second Soldering)
v v
to the range VSS (Vin or Vout) VDD for control inputs and VEE (Vin or Vout)
VDD for Switch I/O.
either VSS, VEE or VDD). Unused outputs must be left open.

MC14551B
PIN ASSIGNMENT
W1 1 16 VDD
X0 2 15 W0
X1 3 14 W
X 4 13 Z
Y 5 12 Z1
Y0 6 11 Z0
VEE 7 10 Y1
VSS 8 9 CONTROL
9 CONTROL
W 14
15 W0
1 W1 X 4
2 X0 COMMONS
SWITCHES 3 X1 OUT/IN
IN/OUT 6 Y0 Y 5
10 Y1
11 Z0 Z 13
12 Z1
VDD = Pin 16 Control ON

VSS = Pin 8 0 W0 X0 Y0 Z0
VEE = Pin 7
1 W1 X1 Y1 Z1
NOTE: Control Input referenced to VSS, Analog Inputs and

Outputs reference to VEE. VEE must be VSS. v
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MC14551B
Characteristic Symbol VDD Test Conditions

55_C
Min Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit

Power Supply Voltage VDD VDD 3.0 VSS 3.0 18 3.0 18 3.0 18 V
Range VEE
Quiescent Current Per IDD 5.0 Control Inputs: Vin = 5.0 0.005 5.0 150 A
Package 10 VSS or VDD, 10 0.010 10 300
15 Switch I/O: VEE v VI/O 20 0.015 20 600
v VDD, and Vswitch
v 500 mV (5.)
Total Supply Current ID(AV) 5.0 TA = 25_C only (The A
Quiescent, Per Package) 15 (Vin Vout)/Ron, is
not included.)
CONTROL INPUT (Voltages Referenced to VSS)
LowLevel Input Voltage VIL 5.0 Ron = per spec, 1.5 2.25 1.5 1.5 V
10 Ioff = per spec 3.0 4.50 3.0 3.0
15 4.0 6.75 4.0 4.0
HighLevel Input Voltage VIH 5.0 Ron = per spec, 3.5 3.5 2.75 3.5 V
10 Ioff = per spec 7.0 7.0 5.50 7.0
15 11 11 8.25 11
SWITCHES IN/OUT AND COMMONS OUT/IN W, X, Y, Z (Voltages Referenced to VEE)
Peak Voltage Into or Out
of the Switch
Output Offset Voltage VOO Vin = 0 V, No Load 10 V
ON Resistance Ron 5.0 Vswitchv 500 mV (5.), 800 250 1050 1200
10 Vin = VIL or VIH 400 120 500 520
15 (Control), and Vin = 220 80 280 300
0 to VDD (Switch)
ON Resistance Between Ron 5.0 70 25 70 135
OffChannel Leakage Ioff 15 Vin = VIL or VIH 100 0.05 100 1000 nA
Channel or Any One
Channel
Capacitance, Switch I/O CI/O Switch Off 10 pF
Capacitance, Common O/I CO/I 17 pF
Capacitance, Feedthrough CI/O Pins Not Adjacent 0.15 pF
(Channel Off) Pins Adjacent 0.47
5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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370
MC14551B
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE
VSS)
VDD VEE
Propagation Delay Times tPLH, tPHL ns
Switch Input to Switch Output (RL = 10 k)
Control Input to Output (RL = 10 k) tPLH, tPHL ns
VEE = VSS (Figure 4) 5.0 350 875
10 140 350
15 100 250
Second Harmonic Distortion 10 0.07 %
RL = 10 k, f = 1 kHz, Vin = 5 Vpp
Bandwidth (Figure 5) BW 10 17 MHz
RL = 1 k, Vin = 1/2 (VDD VEE) pp,
20 Log (Vout / Vin) = 3 dB, CL = 50 pF
Off Channel Feedthrough Attenuation, Figure 5 10 50 dB
fin = 55 MHz
Channel Separation (Figure 6) 10 50 dB
fin = 3 MHz
Crosstalk, Control Input to Common O/I, Figure 7 10 75 mV
R1 = 1 k, RL = 10 k,
Control tr = tf = 20 ns
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371
MC14551B
VDD
VDD VDD
IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
16 VDD
CONTROL 9 LEVEL
CONTROL
CONVERTER
8 VSS 7 VEE
W0 15
14 W
W1 1
X0 2
4 X
X1 3
Y0 6
5 Y
Y1 10
Z0 11
13 Z
Z1 12
Figure 2. MC14551B Functional Diagram
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372
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
PULSE
SECTION
GENERATOR
OF IC CONTROL Vout
LOAD
V RL CL
SOURCE
VDD VEE VEE VDD
Figure 3. V Across Switch Figure 4. Propagation Delay Times,

Control to Output
Control input used to turn ON or OFF

the switch under test.
RL
ON
CONTROL Vout CONTROL
RL CL = 50 pF OFF
Vout
RL CL = 50 pF
Vin
VDD VEE VDD VEE Vin
2 2

Feedthrough Attenuation (Adjacent Channels Used for Setup)

VDD
VEE
CONTROL
SECTION OTHER
CONTROL Vout
OF IC CHANNEL(S) VEE
RL CL = 50 pF VDD
R1
VEE
VDD
Figure 7. Crosstalk, Control Input Figure 8. Off Channel Leakage

to Common O/I
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
VDD RANGE X/Y
PLOTTER
VEE = VSS
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373
MC14551B

350 350
300 300
RON, ON RESISTANCE (OHMS)

250 250
200 200
150 150 TA = 125C

TA = 125C
100 100 25C
25C
55C
50 55C 50
0 0
10 8.0 6.0 4.0 2.0 0 2.0 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 2.0 4.0 6.0 8.0 10
Figure 10. VDD @ 7.5 V, VEE @ 7.5 V Figure 11. VDD @ 5.0 V, VEE @ 5.0 V
700 350
TA = 25C
600 300
500 250 VDD = 2.5 V
400 200
300 150
5.0 V
TA = 125C
200 100 7.5 V
25C
100 55C 50
0 0
10 8.0 6.0 4.0 2.0 0 2.0 4.0 6.0 8.0 10 10 8.0 6.0 4.0 2.0 0 2.0 4.0 6.0 8.0 10
Figure 12. VDD @ 2.5 V, VEE @ 2.5 V Figure 13. Comparison at 25_C, VDD @ VEE
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374
MC14551B
Figure A illustrates use of the onchip level converter margin at each peak. If voltage transients above VDD and/or
detailed in Figure 2. The 0to5 volt Digital Control signal below VEE are anticipated on the analog channels, external
is used to directly control a 9 Vpp analog signal. diodes (Dx) are recommended as shown in Figure B. These
The digital control logic levels are determined by VDD diodes should be small signal types able to absorb the
and VSS. The VDD voltage is the logic high voltage; the VSS maximum anticipated current surges during clipping.
high at the control inputs; VSS = GND = 0 V = logic low. VDD and VEE is 18.0 volts. Most parameters are specified
The maximum analog signal level is determined by VDD up to 15 volts which is the recommended maximum
and VEE. The VDD voltage determines the maximum difference between VDD and V EE.
recommended peak above VSS. The VEE voltage Balanced supplies are not required. However, V SS must
determines the maximum swing below VSS. For the be greater than or equal to VEE. For example, VDD =
example, VDD VSS = 5 volt maximum swing above VSS; + 10 volts, VSS = + 5 volts, and VEE = 3 volts is acceptable.
VSS VEE = 5 volt maximum swing below VSS. The See the table below.
example shows a 4.5 volt signal which allows a 1/2 volt
+5 V 5 V
VDD VSS VEE

+ 4.5 V
+5 V 9 Vpp SWITCH
ANALOG SIGNAL I/O 9 Vpp
COMMON
GND
O/I ANALOG SIGNAL
EXTERNAL MC14551B
CMOS 0TO5 V DIGITAL
CONTROL 4.5 V
DIGITAL CONTROL SIGNAL
CIRCUITRY
VDD VDD
Dx Dx
SWITCH COMMON
I/O O/I
Dx Dx
VEE VEE

Figure B. External Schottky or Germanium Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS

VDD

VSS VEE
Control Inputs
Logic High/Logic Low Maximum Analog Signal Range

In Volts In Volts In Volts In Volts In Volts

+8 0 8 + 8/0 + 8 to 8 = 16 Vpp

+5 0 12 + 5/0 + 5 to 12 = 17 Vpp

+5 0 0 + 5/0 + 5 to 0 = 5 Vpp

+5

0 5 + 5/0 + 5 to 5 = 10 Vpp

+ 10

5 + 10/ + 5 + 10 to 5 = 15 Vpp
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375
MC14553B
3-Digit BCD Counter

The MC14553B 3digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
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All outputs are TTL compatible.
An onchip oscillator provides the lowfrequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, MARKING
digital panel meters, and as a building block for general logic DIAGRAMS
16
applications. PDIP16
TTL Compatible Outputs P SUFFIX MC14553BCP
AWLYYWW
OnChip Oscillator
CASE 648
1
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock 16
Output Latches 14553B

SOIC16
Master Reset DW SUFFIX
CASE 751G
AWLYYWW
1
Symbol Parameter Value Unit A = Assembly Location
WL or L = Wafer Lot
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V WW or W = Work Week
(DC or Transient)
Iout Output Current +20 mA
(DC or Transient) per Pin Device Package Shipping
PD Power Dissipation, 500 mW MC14553BCP PDIP16 25/Rail

(8Second Soldering)
may occur.

MC14553B
BLOCK DIAGRAM
4 3
CIA CIB Q0 9
12 CLOCK Q1 7
Q2 6
10 LE
Q3 5
O.F. 14
11 DIS
DS1 2
DS2 1
13 MR
DS3 15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Master
Reset Clock Disable LE Outputs
0 0 0 No Change
0 0 0 Advance
0 X 1 X No Change
0 1 0 Advance
0 1 0 No Change
0 0 X X No Change
0 X X Latched
0 X X 1 Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0
X = Dont Care
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377
MC14553B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 4.6 Vdc) Source 5.0 0.25 0.2 0.36 0.14
(VOH = 9.5 Vdc) Pin 3 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1
(VOH = 9.5 Vdc) Other 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) Outputs 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) Pin 3 10 1.1 0.9 2.25 0.65
(VOL = 1.5 Vdc) 15 1.8 1.5 8.8 1.20
(VOL = 0.4 Vdc) Sink Other 5.0 3.0 2.5 4.0 1.6 mAdc
(VOL = 0.5 Vdc) Outputs 10 6.0 5.0 8.0 3.5
(VOL = 1.5 Vdc) 15 18 15 20 10
(Vin = 0)
(Per Package) 10 10 0.020 10 300
MR = VDD 15 20 0.030 20 600
buffers switching)
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378
MC14553B

Characteristic
Figure
2a
Symbol
tTLH,
ns
Clock to BCD Out 2a tPLH, 5.0 900 1800 ns
tPHL 10 500 1000
15 200 400
Clock to Overflow 2a tPHL 5.0 600 1200 ns
10 400 800
15 200 400
Reset to BCD Out 2b tPHL 5.0 900 1800 ns
10 500 1000
15 300 600
Clock to Latch Enable Setup Time 2b tsu 5.0 600 300 ns
Master Reset to Latch Enable Setup Time 10 400 200
15 200 100
Removal Time 2b trem 5.0 80 200 ns
Latch Enable to Clock 10 10 70
15 0 50
Clock Pulse Width 2a tWH(cl) 5.0 550 275 ns
10 200 100
15 150 75
Reset Pulse Width 2b tWH(R) 5.0 1200 600 ns
10 600 300
15 450 225
10 0 50
15 20 30
Input Clock Frequency 2a fcl 5.0 1.5 0.9 MHz
10 5.0 2.5
15 7.0 3.5
Input Clock Rise Time 2b tTLH 5.0 No ns
10 Limit
15
Disable, MR, Latch Enable tTLH, 5.0 15 s
Rise and Fall Times tTHL 10 5.0
15 4.0
Scan Oscillator Frequency 1 fosc 5.0 1.5/C1 Hz
(C1 measured in F) 10 4.2/C1
15 7.0/C1
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379
MC14553B
1000
100
101
899
900
901
990
991
992
993
994
995
996
997
998
999
10
12
13
14
15
16
17
86
87
88
89
90
91
92
93
94
95
96
97
98
99
11
1
2
3
4
5
6
7
8
9
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
UP AT 80 UP AT 980
HUNDREDS
CLOCK
HUNDREDS Q0
HUNDREDS Q3
UP AT 800
DISABLE (DISABLES CLOCK WHEN HIGH)
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
UNITS
DIGIT SELECT 2 TENS
DIGIT SELECT 3 HUNDREDS
Figure 1. 3Digit Counter Timing Diagram (Reference Figure 3)
16 VDD
(a)
PULSE Q3 20 ns
1000
C tWL(cl)
999
GENERATOR Q2 CL 20 ns
90%
Q1 CL CLOCK 50%
10%
LE Q0 CL tPLH
O.F. CL tPHL 1/fcl
DIS DS1 CL BCD OUT 10% 90% 50% tPHL
DS2 tTLH tTHL
MR DS3 OVERFLOW 50%
8 VSS
tTLH
90%
VDD CLOCK 50%
(b) 10%
GENERATOR Q3 tsu trem
C
1 Q2 CL
Q1 CL LATCH 50%
GENERATOR
LE Q0 CL ENABLE
2 tPHL, tPLH
O.F. CL tsu
GENERATOR MR DS1 CL
3 BCD OUT 50%
DS2
DIS DS3
tPHL
VSS
MASTER RESET 50%
tWH(R)
Figure 2. Switching Time Test Circuits and Waveforms
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380
MC14553B
The MC14553B threedigit counter, shown in Figure 3, The Master Reset input, when taken high, initializes the
consists of three negative edgetriggered BCD counters three BCD counters and the multiplexer scanning circuit.
which are cascaded in a synchronous fashion. A quad latch While Master Reset is high the digit scanner is set to digit
at the output of each of the three BCD counters permits one; but all three digit select outputs are disabled to prolong
storage of any given count. The three sets of BCD outputs display life, and the scan oscillator is inhibited. The Disable
(active high), after going through the latches, are time input, when high, prevents the input clock from reaching the
division multiplexed, providing one BCD number or digit at counters, while still retaining the last count. A pulse shaping
a time. Digit select outputs (active low) are provided for circuit at the clock input permits the counters to continue
display control. All outputs are TTL compatible. operating on input pulses with very slow rise times.
An onchip oscillator provides the low frequency Information present in the counters when the latch input
scanning clock which drives the multiplexer output selector. goes high, will be stored in the latches and will be retained
The frequency of the oscillator can be controlled externally while the latch input is high, independent of other inputs.
by a capacitor between pins 3 and 4, or it can be overridden Information can be recovered from the latches after the
and driven with an external clock at pin 4. Multiple devices counters have been reset if Latch Enable remains high
can be cascaded using the overflow output, which provides during the entire reset cycle.
one pulse for every 1000 counts.
C1A
LATCH ENABLE 4
10 SCAN PULSE
R C1
OSCILLATOR 3 GENERATOR
C1B
CLOCK
12 R SCANNER
Q0
PULSE C Q1 QUAD
SHAPER Q2 LATCH
R 10
Q3 9
UNITS Q0
11
DISABLE
(ACTIVE
HIGH) MULTIPLEXER
7
Q0 Q1
C
Q1 QUAD BCD
Q2 LATCH OUTPUTS
R 10
Q3 (ACTIVE
TENS
HIGH)
6
Q2
Q0
C
Q1 QUAD 5
Q3
Q2 LATCH
R
10 Q3
HUNDREDS
2 1 15
DS1 DS2 DS3
13 14 (LSD) DIGIT SELECT (MSD)
MR OVERFLOW (ACTIVE LOW)
(ACTIVE HIGH)
Figure 3. Expanded Block Diagram
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381
STROBE
RESET
10 13 10 13
LE MR 4 LE MR 4
12 C1A 0.001 12 C1 A
CLOCK CLK CLK 3
INPUT 3 F
MC14553B C1B MC14553B C1 B
11 11 14
DIS 14 DIS
O.F. O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1 Q3 Q2 Q1 Q0 DS3 DS2 DS1
5 6 7 9 15 1 2 5 6 7 9 15 1 2
5 9
A a
3 10
B b
2 11
VDD C c
4 12
D MC14543B d
6 13
Ph e
1 15
382
VDD LD f
7 g 14
BI
MC14553B
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Figure 4. SixDigit Display
5 9
A a
3
B b 10
2 11
C c
4 12
D MC14543B d
6 13
Ph e
1 15
VDD LD f
7 14
BI g
LSD DISPLAYS ARE LOW CURRENT LEDs MSD

(I peak < 10 mA PER SEGMENT)
MC14555B, MC14556B
Dual Binary to 1-of-4

Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2, http://onsemi.com
Q3). The MC14555B has the selected output go to the high state,
and the MC14556B has the selected output go to the low state. MARKING
Expanded decoding such as binarytohexadecimal (1of16), etc., DIAGRAMS
can be achieved by using other MC14555B or MC14556B devices. 16
Applications include code conversion, address decoding, memory PDIP16
P SUFFIX MC1455XBCP
selection control, and demultiplexing (using the Enable input as a data AWLYYWW
CASE 648
input) in digital data transmission systems.
1
Active High or Active Low Outputs SOIC16
1455XB
Expandable D SUFFIX AWLYWW
CASE 751B
1
Capable of Driving Two LowPower TTL Loads or One LowPower SOEIAJ16
Schottky TTL Load Over the Rated Temperature Range F SUFFIX MC1455XB
CASE 966 AWLYWW
X = Specific Device Code

Symbol Parameter Value Unit WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(DC or Transient)
Iin, Iout Input or Output Current 10 mA ORDERING INFORMATION
TA Ambient Temperature Range 55 to +125 C MC14555BD SOIC16 48/Rail

Tstg Storage Temperature Range 65 to +150 C MC14555BDR2 SOIC16 2500/Tape & Reel
TL Lead Temperature 260 C MC14555BF SOEIAJ16 See Note 1.
(8Second Soldering)
may occur.
applications of any voltage higher than maximum rated voltages to this MC14556BF SOEIAJ16 See Note 1.
to the range VSS v (Vin or Vout) vVDD. MC14556BFEL SOEIAJ16 See Note 1.

MC14555B, MC14556B
PIN ASSIGNMENTS
MC14555B MC14556B
EA 1 16 VDD EA 1 16 VDD
AA 2 15 EB AA 2 15 EB
BA 3 14 AB BA 3 14 AB
Q0A 4 13 BB Q0A 4 13 BB
Q1A 5 12 Q0B Q1A 5 12 Q0B
Q2A 6 11 Q1B Q2A 6 11 Q1B
Q3A 7 10 Q2B Q3A 7 10 Q2B
VSS 8 9 Q3B VSS 8 9 Q3B
TRUTH TABLE
Inputs Outputs
Enable Select MC14555B MC14556B
E B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1
0 1 0 0 1 0 0 1 0 1 1
0 1 1 1 0 0 0 0 1 1 1
1 X X 0 0 0 0 1 1 1 1
X = Dont Care
BLOCK DIAGRAM
MC14555B MC14556B
2 A Q0 4 2 A Q0 4
Q1 5 Q1 5
3 B 3 B
Q2 6 Q2 6
1 E 1 E
Q3 7 Q3 7
14 A Q0 12 14 A Q0 12
Q1 11 Q1 11
13 B 13 B
Q2 10 Q2 10
15 E 15 E
Q3 9 Q3 9
VDD = PIN 16
VSS = PIN 8
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384
MC14555B, MC14556B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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385
MC14555B, MC14556B

Characteristic
Symbol
tTLH,
ns
Propagation Delay Time A, B to Output tPLH, ns
Propagation Delay Time E to Output tPLH, ns
INPUT E LOW
20 ns 20 ns INPUT A HIGH, INPUT E LOW
20 ns 20 ns
VDD
90%
50% VDD
90%
A INPUTS 10% VSS INPUT B 50%
1
(50% DUTY CYCLE) 10% VSS
2f VDD tPHL tPLH
90% VOH
OUTPUT Q3 50%
B INPUTS VSS
MC14556B 10%
(50% DUTY CYCLE) V
VOH tTHL tTLH OL
tPLH tPHL
VOH
OUTPUT Q1 VOL OUTPUT Q3 90%
50%
MC14555B 10% VOL
All 8 outputs connect to respective CL loads.
f in respect to a system clock. tTLH tTHL
Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
* Q0
*
Q1
* Q2
* Q3
*Eliminated for MC14555B
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386
MC14557B
1-to-64 Bit Variable Length

Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus http://onsemi.com
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or MARKING
negative edge clocking capability. DIAGRAMS
The device can be effectively used for variable digital delay lines or 16
simply to implement odd length shift registers. PDIP16
P SUFFIX MC14557BCP
164 Bit Programmable Length CASE 648 AWLYYWW
Q and Q Serial Buffered Outputs 1

Asynchronous Master Reset
16
All Inputs Buffered
No Limit On Clock Rise and Fall Times SOIC16 14557B
Supply Voltage Range = 3.0 Vdc to 18 Vdc DW SUFFIX
Capable of Driving Two Lowpower TTL Loads or one Lowpower
CASE 751G
AWLYYWW
1
16

F SUFFIX MC14557B

(DC or Transient) A = Assembly Location
WL or L = Wafer Lot
(8Second Soldering)
may occur. MC14557BDWR2 SOIC16 1000/Tape & Reel

MC14557B
PIN ASSIGNMENT
L2 1 16 VDD
L1 2 15 L4
RESET 3 14 L8
CLOCK 4 13 L16
CE 5 12 L32
B 6 11 Q
A 7 10 Q
VSS 8 9 A/B SEL
BLOCK DIAGRAM
3 RESET
4 CLOCK
5 CE
6 B Q 10
7 A
9 A/B SELECT
2 L1
1 L2
15 L4 Q 11
14 L8
13 L16
12 L32
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs Output
Rst A/B Clock CE Q
0 0 0 B
0 1 0 A
0 0 1 B
0 1 1 A
1 X X X 0
Q is the output of the first selected shift
register stage.
X = Dont Care
LENGTH SELECT TRUTH TABLE

L32 L16 L8 L4 L2 L1 Register Length
0 0 0 0 0 0 1 Bit
0 0 0 0 0 1 2 Bits
Bit
0 0 0 0 1 0 3 Bits
0 0 0 0 1 1 4 Bits
0 0 0 1 0 0 5 Bits
0 0 0 1 0 1 6 Bits

1 0 0 0 0 0 33 Bits
Bit
1 0 0 0 0 1 34 Bits

1 1 1 1 0 0 61 Bits
1 1 1 1 1 1 62 Bits
1 1 1 1 1 0 63 Bits
1 1 1 1 0 1 64 Bit
Bits
NOTE: Length equals the sum of the binary length control
subscripts plus one.
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388
MC14557B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 0.51 0.88 0.36
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.020 10 300
15 20 0.030 20 600
buffers switching)
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389
MC14557B

Characteristic
Rise and Fall Time, Q or Q Output
Symbol
tTLH,
ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5 100 200
Propagation Delay, Clock or CE to Q or Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5 300 600
Propagation Delay, Reset to Q or Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5 300 600
Pulse Width, Clock tWH(cl) 5 200 95 ns
10 100 45
15 75 35
Pulse Width, Reset tWH(rst) 5 300 150 ns
10 140 70
15 100 50
Clock Frequency (50% Duty Cycle) fcl 5 3.0 1.7 MHz
10 7.5 5.0
15 13.0 6.7
Setup Time, A or B to Clock or CE tsu ns
Worst case condition: L1 = L2 = L4 = L8 = 5 700 350
L16 = L32 = VSS (Register Length = 1) 10 290 130
15 145 85
Best case condition: L32 = VDD, L1 through L16 = 5 400 45
Dont Care (Any register length from 33 to 64) 10 165 5
15 60 0
Hold Time, Clock or CE to A or B th ns
Best case condition: L1 = L2 = L4 = L8 = L16 = 5 200 150
L32 = VSS (Register Length = 1) 10 100 60
15 10 50
Worst case condition: L32 = VDD, L1 through L16 = 5 400 50
Dont Care (Any register length from 33 to 64) 10 185 25
15 85 22
Rise and Fall Time, Clock tr, 5
tf 10 No Limit
15
Rise and Fall Time, Reset or CE tr, 5 15 s
tf 10 5
15 4
Removal Time, Reset to Clock or CE trem 5 160 80 ns
10 80 40
15 70 35
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390
MC14557B
TIMING DIAGRAM
VDD
50%
CLOCK tWH(cl) VSS
1/fcl VDD
50%
A INPUT trem VSS
tsu
VDD
th 50%
RESET VSS
tTLH tTHL PWR
1bit length: VOH
90%
CE = 0 50%
A/B = 1 Q 10% VOL
L1 = L2 = L4 = L8 = L16 = L32 = 0 tPLH tPHL tPHL
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391
5
CE
4
CLOCK
3
RESET
7 C R C R C R C R
A 32 BIT 16 BIT 8 BIT 4 BIT
6
B
A/B 9 12 13 14 15
392
SELECT L32 L16 L8 L4
MC14557B
LOGIC DIAGRAM
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C R C R C R 10
Q
2 BIT 1 BIT 1 BIT
11
Q
1 2 VDD = PIN 16
L2 L1 VSS = PIN 8
MC14562B
128-Bit Static Shift

Register
The MC14562B is a 128bit static shift register constructed with
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are http://onsemi.com
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired. MARKING
14
PDIP14
Cascadable to Provide Longer Shift Register Lengths P SUFFIX MC14562BCP
Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646 AWLYYWW

WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(DC or Transient)
(8Second Soldering) MC14562BCP PDIP14 25/Rail
may occur.

MC14562B
PIN ASSIGNMENT
Q64 1 14 VDD
Q96 2 13 Q32
Q128 3 12 DATA
NC 4 11 NC
CLOCK 5 10 Q16
Q112 6 9 Q48
VSS 7 8 Q80
NC = NO CONNECTION
BLOCK DIAGRAM
Q16 10
12 DATA Q32 13
Q48 9
Q64 1
Q80 8
5 CLOCK Q96 2
Q112 6
Q128 3
Pins 4 and 11 VDD = PIN 14

not used. VSS = PIN 7
LOGIC DIAGRAM
CLOCK 5
DATA IN 12
D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q
C C C C C C C C C C
1 2 3 16 17 32 33 48 49 64
10 Q16
D Q D Q D Q D Q D Q D Q D Q D Q
C C C C C C C C 13 Q32
65 80 81 96 97 112 113 128
9 Q48
1 Q64
8 Q80
2 Q96
6 Q112
3 Q128
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394
MC14562B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 05 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.020 10 300
15 20 0.030 20 600
buffers switching)
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395
MC14562B

Characteristic
Symbol
tTLH,
ns
Clock to Q tPHL
(50% Duty Cycle) 10 220 110
15 150 75
10 5.6 3.0
15 8.0 4.0
Data to Clock Setup Time tsu(1) 5.0 20 170 ns
10 10 64
15 0 60
tsu(0) 5.0 20 91 ns
10 10 58
15 0 48
Data to Clock Hold Time th(1) 5.0 350 263 ns
10 165 109
15 155 100
th(0) 5.0 350 267 ns
10 200 140
15 140 93
Clock Input Rise and Fall Times tr, tf 5.0 15 s
10 5
15 4
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396
MC14562B
VDD
Q16
DATA Q32
Q48
Q64
Q80
CLOCK Q96
Q112
Q128
7 VSS CL CL CL CL CL CL CL CL
ID 500 F
fo VDD
CLOCK
VSS
DATA VDD
(f = 1/2 fo)
VSS
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397
MC14562B
TIMING DIAGRAM
PIN PULSE 1 PULSE 16 PULSE 32 PULSE 128

NO.S
CLOCK 5
DATA IN 12
Q16 10
Q32 13
Q28 3
AC TEST WAVEFORMS
PULSE 1 PULSE 2 PULSE 16 PULSE 17

90% VDD
CLOCK 50% 50% 50% 50%
10%
VSS
tWH tr
tWL tf
VDD
DATA IN 50% 50%
VSS
tsu(0)
th(0)
VDD
50% 10% 90%
Q16
VSS
tPHL
tTHL
PULSE 1 PULSE 2 PULSE 16 PULSE 17
VDD
CLOCK 50% 50% 50% 50%
VSS
tWH
tWL
VDD
DATA IN 50% 50%
VSS
tsu(1)
th(1)
VDD
Q16 50% 90%
10%
VSS
tPLH
tTHL
NOTE: The remaining DataBit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
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398
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable dividebyN dual 4bit binary
or BCD down counter constructed with MOS Pchannel and http://onsemi.com
Nchannel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase MARKING
comparator/counter in frequency synthesizers, phaselocked loops, DIAGRAMS
and other frequency division applications requiring low power 16
dissipation and/or high noise immunity. PDIP16
MC14569BCP
Speedup Circuitry for Zero Detection P SUFFIX
CASE 648 AWLYYWW
Each 4Bit Counter Can Divide Independently in BCD or Binary 1
Mode
Can be Cascaded With MC14526B for 16
Frequency Synthesizer Applications TSSOP16 14
All Outputs are Buffered DT SUFFIX 569B
Schmitt Triggered Clock Conditioning CASE 948F ALYW
16
SOIC16 14569B
Symbol Parameter Value Unit DW SUFFIX
VDD DC Supply Voltage Range 0.5 to +18.0 V CASE 751G
AWLYYWW
(DC or Transient) 1

YY or Y = Year
WW or W = Work Week

(8Second Soldering)
may occur. MC14569BDT TSSOP16 96/Rail
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14569BDW SOIC16 47/Rail

MC14569B
PIN ASSIGNMENT
ZERO 1 16 VDD
DETECT
CTL1 2 15 Q
P0 3 14 P7
P1 4 13 P6
P2 5 12 P5
P3 6 11 P4
CASCADE 7 10 CTL2
FEEDBACK
VSS 8 9 CLOCK
BLOCK DIAGRAM
P0 P1 P2 P3 CTL1 CTL2 P4 P5 P6 P7
CTL = Low for Binary Count
3 4 5 6 2 10 11 12 13 14
CTL = High for BCD Count VDD = PIN 16
VSS = PIN 8
9 BINARY/BCD CLOCK BINARY/BCD 15

CLOCK Q
COUNTER #1 LOAD COUNTER #2
CASCADE 7 1 ZERO
FEEDBACK ZERO DETECT ENCODER
DETECT
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400
MC14569B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
Vin = 0 or VDD 1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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401
MC14569B
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
VDD
Vdc Min
All Types
Typ (6.) Max Unit
10 50 100
15 40 80
10 50 100
15 40 80
TurnOn Delay Time tPLH ns
Zero Detect Output 5.0 420 700
10 175 300
15 125 250
Q Output 5.0 675 1200 ns
10 285 500
15 200 400
TurnOff Delay Time tPHL ns
Zero Detect Output 5.0 380 600
10 150 300
15 100 200
Q Output 5.0 530 1000 ns
10 225 400
15 155 300
10 150 45
15 115 30
10 9.5 5.1
15 13.0 7.8
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 NO LIMIT s
10
15
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402
MC14569B
SWITCHING WAVEFORMS
20 ns
20 ns
90%
CLOCK 50% fin = fmax
10%
tWH
tPLH tPHL
90%
Q 50%
10%
tTLH tTHL
Figure 1.
20 ns
20 ns
90%
CLOCK 50%
10%
tWH
tPHL
tPLH
90%
ZERO DETECT 10%
tTLH tTHL
Figure 2.
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403
MC14569B
PIN DESCRIPTIONS
INPUTS CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) Preset Inputs. Cascade Feedback (Pin 7) This pin is normally set
Programmable inputs for the least significant counter. May high. When low, loading of the preset inputs (P0 through P7)
be binary or BCD depending on the control input. is inhibited, i.e., P0 through P7 are dont cares. Refer to
P4, P5, P6, P7 (Pins 11, 12, 13, 14) Preset Inputs. Table 1 for output characteristics.
Programmable inputs for the most significant counter. May CTL1 (Pin 2) This pin controls the counting mode of
be binary or BCD depending on the control input. the least significant counter. When set high, counting mode
Clock (Pin 9) Preset data is decremented by one on is BCD. When set low, counting mode is binary.
each positive transition of this signal. CTL2 (Pin 10) This pin controls the counting mode of
the most significant counter. When set high, counting mode
OUTPUTS is BCD. When set low, counting mode is binary.
Zero Detect (Pin 1) This output is normally low and
goes high for one clock cycle when the counter has SUPPLY PINS
decremented to zero. VSS (Pin 18) Negative Supply Voltage. This pin is
Q (Pin 15) Output of the last stage of the most usually connected to ground.
significant counter. This output will be inactive unless the VDD (Pin 16) Positive Supply Voltage. This pin is
preset input P7 has been set high. connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
The MC14569B is a programmable dividebyN dual one pulse appears on the Zero Detect output. (See Timing
4bit down counter. This counter may be programmed (i.e., Diagram.) The Q output is the output of the last stage of the
preset) in BCD or binary code through inputs P0 to P7. For most significant counter (See Tables 1 through 5, Mode
each counter, the counting sequence may be chosen Controls.)
independently by applying a high (for BCD count) or a low When cascading the MC14569B to the MC14526B, the
(for binary count) to the control inputs CTL1 and CTL2. Cascade Feedback input, Q, and Zero Detect outputs must
The divide ratio N (N being the value programmed on the be respectively connected to 0, Clock, and Load of the
preset inputs P0 to P7) is automatically loaded into the following counter. If the MC14569B is used alone, Cascade
counter as soon as the count 1 is detected. Therefore, a Feedback must be connected to VDD.
division ratio of one is not possible. After N clock cycles,
18
CL = 50 pF
16
f, FREQUENCY (MHz), TYPICAL
14
12 VDD = 15 V
10
8.0 10 V
6.0
4.0 5.0 V
2.0
0
40 20 0 + 20 + 40 + 60 + 80 + 100
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404
MC14569B
Table 1. Mode Controls (Cascade Feedback = Low)

Counter Control Values Divide Ratio
CTL1 CTL2 Zero Detect Q
0 0 256 256
0 1 160 160
1 0 160 160
1 1 100 100
NOTE: Data Preset Inputs (P0P7) are Dont Cares while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect Q Comments
0 0 0 0 0 0 0 0 256 256 Max Count
0 0 0 0 0 0 0 1 X X Illegal State
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 1 1 1 15 X
0 0 0 1 0 0 0 0 16 X
X
X
X
0 0 1 0 0 0 0 0 32 X
X
X
X
0 1 0 0 0 0 0 0 64 X
X
X
X
0 1 1 1 1 1 1 1 127 X
1 0 0 0 0 0 0 0 128 128 Q Output Active

1 0 0 0 1 0 0 0 136 136

1 1 1 1 1 1 1 1 255 255
27 26 25 24 23 22 21 20
128 64 32 16 8 4 2 1 Bit Value
Counter #2 Counter #1 Counting
Binary Binary Sequence
X = No Output (Always Low)
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405
MC14569B
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Preset Inputs Divide Ratio
Zero
0 0 0 0 0 0 0 0 160 160 Max Count
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 0 0 1 9 X
0 0 0 1 0 0 0 0 10 X
X
X
X
0 0 0 1 1 0 0 1 19 X
0 0 1 0 0 0 0 0 20 X
X
X
X
0 0 1 1 0 0 0 0 30 X
X
X
X
0 1 0 0 0 0 0 0 40 X
X
X
X
0 1 0 1 0 0 0 0 50 X
X
X
X
0 1 1 0 0 0 0 0 60 X
X
X
X
0 1 1 1 0 0 0 0 70 X
X
X
X
1 0 0 0 0 0 0 0 80 80 Q Output Active

1 0 0 1 0 0 0 0 90 90

1 1 1 1 0 0 0 0 150 150

1 1 1 1 1 0 0 1 159 159
80 40 20 10 8 4 2 1 Bit Value
Binary BCD Sequence
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406
MC14569B
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Preset Values Divide Ratio
Zero
0 0 0 0 0 0 0 0 160 160 Max Count
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 1 1 1 15 X
0 0 0 1 0 0 0 0 16 X
X
X
X
0 0 0 1 1 1 1 1 31 X
0 0 1 0 0 0 0 0 32 X
X
X
X
0 0 1 1 0 0 0 0 48 X

0 1 0 0 0 0 0 0 64 X

0 1 0 1 0 0 0 0 80 X

0 1 1 1 0 0 0 0 112 X

1 0 0 0 0 0 0 0 128 128 Q Output Active

1 0 0 1 0 0 0 0 144 144

1 0 0 1 1 1 1 1 159 159
27 26 25 24 23 22 21 20
128 64 32 16 8 4 2 1 Bit Value
BCD Binary Sequence
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407
MC14569B
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Preset Values Divide Ratio
Zero
0 0 0 0 0 0 0 0 100 100 Max Count
0 0 0 0 0 0 0 1 X X illegal state
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 0 0 1 9 X
0 0 0 1 0 0 0 0 10 X
X
X
X
0 0 1 1 0 0 0 0 30 X
X
X
X
0 1 0 0 0 0 0 0 40 X
X
X
X
0 1 0 1 0 0 0 0 50 X
X
X
X
0 1 1 1 0 0 0 0 70 X
X
X
X
1 0 0 0 0 0 0 0 80 80 Q Output Active

1 0 0 1 0 0 0 0 90 90

1 0 0 1 1 0 0 1 99 99
80 40 20 10 8 4 2 1 Bit Value
BCD BCD Sequence
TIMING DIAGRAM MC14569B
CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DIVIDE
BY 2
DIVIDE
ZERO BY 3
DETECT
OUTPUT DIVIDE
BY 4
DIVIDE
BY 12
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408
MC14569B
LOGIC DIAGRAM
2
CTL1
DP Q
PE
D C
DP Q
3 PE
P0 D C
4 DP Q
P1 PE
D C
DP Q PE
5 D C
P2
DP Q
PE
6 D C
P3
DP Q
PE
D C
DP Q
PE
D C
DP Q
PE
D C
IU
VDD
CASCADE 7
FEEDBACK VDD
9
CLOCK
1
ZERO
DETECT
11 DP D C
P4
Q PE
12 DP D C
P5
Q PE
13 DP D C
P6
Q PE
14 DP D C
P7
Q PE
10 15
CTL2
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409
MC14569B
CF CF CF
fin C Q C Q4 C Q4 Q1/C2
MC14522B MC14522B
MC14569B OR OR MC14568B
ZERO DETECT PE MC14526B 0 PE MC14526B 0 PE 0
DP0 DP3 DP0 DP3 DP0 DP3
LSD MSD fout
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
fout
(40 kHz) PCin PCout VCO
C1 G VSS (144 146 MHz)
CT1 F VSS
VSS 0 Q1/C2
PE
VDD
DP0 DP3
MC14011
Q CF
MC14569B C
ZERO DETECT
MIXER
2k
2M
CRYSTAL
Frequencies shown in parenthesis are given as an example OSCILLATOR
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer

(Channel Spacing 10 kHz)
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410
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
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NAND gate.
Single Supply Operation DIAGRAMS
NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter PDIP16
MC14572UBCP
P SUFFIX
NAND Input Pin Adjacent to VDD Pin to Simplify Use As An CASE 648 AWLYYWW
Inverter 1
NOR Output Pin Adjacent to Inverter Input Pin For OR Application 16
NAND Output Pin Adjacent to Inverter Input Pin For AND SOIC16
14572U
Application D SUFFIX AWLYWW
CASE 751B
SOEIAJ16
F SUFFIX MC14572UB
CASE 966 AWLYWW
1

TA Ambient Temperature Range 55 to +125 C MC14572UBCP PDIP16 2000/Box
Tstg Storage Temperature Range 65 to +150 C MC14572UBD SOIC16 48/Rail

TL Lead Temperature 260 C MC14572UBDR2 SOIC16 2500/Tape & Reel
(8Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device MC14572UBF SOEIAJ16 See Note 1.
may occur.
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C 1. For ordering information on the EIAJ version of
This device contains protection circuitry to guard against damage due to high ON Semiconductor representative.

MC14572UB
PIN ASSIGNMENT
OUTA 1 16 VDD
INA 2 15 IN 2F
OUTB 3 14 IN 1F
INB 4 13 OUTF
OUTC 5 12 INE
IN 1C 6 11 OUTE
IN 2C 7 10 IND
VSS 8 9 OUTD
LOGIC DIAGRAM
2 1
4 3
6
5
7
10 9
12 11
14
13
15
VDD = PIN 16
VSS = PIN 8
CIRCUIT SCHEMATIC
VDD VDD
VDD
7
2 1 13
6 14
5
VSS
15
VSS VSS
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412
MC14572UB
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
Vin = 0 or VDD 1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.0 2.25 1.0 1.0
(VO = 9.0 or 1.0 Vdc) 10 2.0 4.50 2.0 2.0
(VO = 13.5 or 1.5 Vdc) 15 2.5 6.75 2.5 2.5
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 4.0 2.75 4.0
(VO = 1.0 or 9.0 Vdc) 10 8.0 8.0 5.50 8.0
(VO = 1.5 or 13.5 Vdc) 15 12.5 12.5 8.25 12.5
(VOH = 2.5 Vdc) Source 5.0 1.2 1.0 1.7 0.7
(VOH = 4.6 Vdc) 5.0 0.25 0.2 0.36 0.14
(VOH = 9.5 Vdc) 10 0.62 0.5 0.9 0.35
(VOH = 13.5 Vdc) 15 1.8 1.5 3.5 1.1
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 0.5 0.0010 0.5 15
15 1.0 0.0015 1.0 30
buffers switching)
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413
MC14572UB
Output Rise Time

tTLH
ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 65 130
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
VDD VDD
INPUT
INPUT 16 16
7
2 PULSE
PULSE GENERATOR
OUTPUT 6 OUTPUT
GENERATOR 1 5
8 VSS CL 8 VSS CL
VDD
20 ns 20 ns
16 VDD
90% 90%
INPUT 14 INPUT 50% 50%
10% 10% VSS
15 OUTPUT
PULSE tPHL
13 tPLH
GENERATOR
8 VSS CL 90% 90% VOH
OUTPUT 50% 50%
10% 10%
VOL
tf tr
Figure 1. Switching Time Test Circuits and Waveforms
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414
MC14584B
Hex Schmitt Trigger
The MC14584B Hex Schmitt Trigger is constructed with MOS
dissipation and/or high noise immunity is desired. The MC14584B
may be used in place of the MC14069UB hex inverter for enhanced
http://onsemi.com
noise immunity to square up slowly changing waveforms.
MARKING
Capable of Driving Two Lowpower TTL Loads or One Lowpower DIAGRAMS
Double Diode Protection on All Inputs PDIP14
MC14584BCP
Can Be Used to Replace MC14069UB P SUFFIX
CASE 646 AWLYYWW
For Greater Hysteresis, Use MC14106B which is PinforPin 1
Replacement for CD40106B and MM74Cl4 14
SOIC14
14584B
D SUFFIX AWLYWW
CASE 751A
VDD DC Supply Voltage Range 0.5 to +18.0 V TSSOP14 14
DT SUFFIX 584B
CASE 948G ALYW
(DC or Transient)
(DC or Transient) per Pin 14
PD Power Dissipation, 500 mW SOEIAJ14
per Package (Note 3.) F SUFFIX MC14584B
CASE 965 AWLYWW
1
WL or L = Wafer Lot
(8Second Soldering)
YY or Y = Year
2. Maximum Ratings are those values beyond which damage to the device WW or W = Work Week
may occur.
applications of any voltage higher than maximum rated voltages to this MC14584BCP PDIP14 2000/Box
to the range VSS v (Vin or Vout) vVDD. MC14584BD SOIC14 55/Rail
either VSS or VDD). Unused outputs must be left open. MC14584BDR2 SOIC14 2500/Tape & Reel


MC14584B
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 IN 6
IN 2 3 12 OUT 6
OUT 2 4 11 IN 5
IN 3 5 10 OUT 5
OUT 3 6 9 IN 4
VSS 7 8 OUT 4
LOGIC DIAGRAM
1 2
3 4
5 6
9 8
11 10
13 12
VDD = PIN 14
VSS = PIN 7
EQIVALENT CIRCUIT SCHEMATIC

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MC14584B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
Vin = 0 1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 0.5 0.0010 0.5 15
15 1.0 0.0015 1.0 30
buffers switching)
Hysteresis Voltage VH (7.) 5.0 0.27 1.0 0.25 0.6 1.0 0.21 1.0 Vdc
10 0.36 1.3 0.3 0.7 1.2 0.25 1.2
15 0.77 1.7 0.6 1.1 1.5 0.50 1.4
Threshold Voltage VT+ Vdc
PositiveGoing 5.0 1.9 3.5 1.8 2.7 3.4 1.7 3.4
10 3.4 7.0 3.3 5.3 6.9 3.2 6.9
15 5.2 10.6 5.2 8.0 10.5 5.2 10.5
NegativeGoing VT 5.0 1.6 3.3 1.6 2.1 3.2 1.5 3.2 Vdc
10 3.0 6.7 3.0 4.6 6.7 3.0 6.7
15 4.5 9.7 4.6 6.9 9.8 4.7 9.9
7. VH = VT+ VT (But maximum variation of VH is specified as less than VT + max VT min).
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MC14584B
VDD
10 50 100
15 40 80
10 50 100
15 40 80
Propagation Delay Time tPLH, tPHL 5.0 125 250 ns
10 50 100
15 40 80
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MC14584B
VDD 20 ns 20 ns
14 VDD
INPUT 90%
PULSE OUTPUT 50%
GENERATOR 10% VSS
INPUT
CL tPHL tPLH
7 VSS 90% VOH
OUTPUT 50%
10% VOL
tf tr
Vin Vout
VH VDD VH VDD
VT+ VT+
Vin VT Vin VT
VSS VSS
VDD VDD
Vout Vout
VSS VSS
(a) Schmitt Triggers will square up inputs with slow (b) A Schmitt trigger offers maximum noise immunity
rise and fall times. in gate applications.
Figure 2. Typical Schmitt Trigger Applications
VDD
0
0 VT VT+ VDD
VH
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MC14585B
4-Bit Magnitude
Comparator
The MC14585B 4Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),
three cascading inputs (A < B, A = B, and A > B), and three outputs (A http://onsemi.com
< B, A = B, and A > B). This device compares two 4bit words (A and
B) and determines whether they are less than, equal to, or greater MARKING
than by a high level on the appropriate output. For words greater than DIAGRAMS
4bits, units can be cascaded by connecting outputs (A > B), (A < B), 16
and (A = B) to the corresponding inputs of the next significant PDIP16
P SUFFIX MC14585BCP
comparator. Inputs (A < B), (A = B), and (A > B) on the least AWLYYWW
CASE 648
significant (first) comparator are connected to a low, a high, and a low,
respectively. 1
Applications include logic in CPUs, correction and/or detection of 16
instrumentation conditions, comparator in testers, converters, and SOIC16
14585B
D SUFFIX AWLYWW
controls. CASE 751B
Expandable 16
Applicable to Binary or 8421BCD Code SOEIAJ16
MC14585B
F SUFFIX
Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 966 AWLYWW
1
Schottky TTL Load over the Rated Temperature Range
Can be Cascaded See Fig. 3 A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
(DC or Transient) Device Package Shipping
Iin, Iout Input or Output Current 10 mA MC14585BCP PDIP16 2000/Box

per Package (Note 3.) MC14585BDR2 SOIC16 2500/Tape & Reel
TA Ambient Temperature Range 55 to +125 C MC14585BF SOEIAJ16 See Note 1.

Tstg Storage Temperature Range 65 to +150 C 1. For ordering information on the EIAJ version of
TL Lead Temperature 260 C the SOIC packages, please contact your local
(8Second Soldering)
may occur.

MC14585B
PIN ASSIGNMENT
B2 1 16 VDD
A2 2 15 A3
(A = B)out 3 14 B3
(A u B)in 4 13 (A u B)out
(A t B)in 5 12 (A t B)out
(A = B)in 6 11 B0
A1 7 10 A0
VSS 8 9 B1
BLOCK DIAGRAM
4 (A > B)in
6 (A = B)in
5 (A < B)in (A > B)out 13
10 A0
11 B0
7 A1 (A = B)out 3
9 B1
2 A2
1 B2 (A < B)out 12
15 A3
14 B3
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE (x = Dont Care)

Inputs
Comparing Cascading Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A<B A=B A>B A<B A=B A>B
A3 > B3 x x x x x x 0 0 1
A3 = B3 A2 > B2 x x x x x 0 0 1
A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0
A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0
A3 = B3 A2 < B2 x x x x x 1 0 0
A3 < B3 x x x x x x 1 0 0
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MC14585B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
(Vin = 0)
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
buffers switching)
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MC14585B

Characteristic
Symbol
tTLH,
ns
TurnOn, TurnOff Delay Time tPLH, ns
20 ns
20 ns
VDD
A3
1 VSS
2f VDD
B3
VSS
20 ns 20 ns
VOH
(A > B)out VDD
90%
VOL 50%
B0
VOH 10% VSS
(A = B)out tPLH tPHL
VOL VOH
90%
VOH 50%
(A < B)out
(A < B)out 10% VOL
VOL
tTLH tTHL
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low. Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
f in respect to a system clock. A2, B1, A1, A0, and (A<B) low.
Figure 1. Dynamic Power Dissipation Figure 2. Dynamic Signal Waveforms

Signal Waveforms
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423
MC14585B
WORD
B = B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
WORD
A= A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VSS VDD VSS
(A<B)
(A=B)
(A>B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT MC14585B
(A<B)
(A=B)
(A>B)
INPUTS
MC14585B
MC14585B
WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.
(A<B)
(A=B)
(A>B)
OUTPUTS
Figure 3. Cascading Comparators
LOGIC DIAGRAM
15
A3
14
B3
2
A2
1
B2
7 12
A1 (A < B)out
9
B1
10
A0
11
B0
5
(A < B)in
3
6 (A = B)out
(A = B)in
13
4 (A > B)out
(A > B)in
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MC14598B
8-Bit Bus-Compatible
Latches
The MC14598B is an 8bit latch addressed with an external binary
address. The 8 latchoutputs are high drive, threestate and bus line
compatible. The drive capability allows direct applications with MPU
systems such as the Motorola 6800 family. http://onsemi.com
The latches of the MC14598B are accessed via the Address pins,
A0, A1, and A2.
All 8 outputs from the latches are available in parallel when Enable
is in the low state. Data is entered into a selected latch from the Data
pin when the Strobe is high. Master reset is available on both parts.
Serial Data Input
ThreeState Bus Compatible Parallel Outputs
ThreeState Control Pin (Enable) TTL Compatible Input
Open Drain Full Flag (Multiple Latch WireO Ring) MARKING
Master Reset 18
DIAGRAMS
Level Shifting Inputs on All Except Enable PDIP18
MC14598BCP
Diode Protection All Inputs P SUFFIX
CASE 707
AWLYYWW
Supply Voltage Range 3.0 Vdc to 18 Vdc 1
Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows: A = Assembly Location
1 TTL Load WL or L = Wafer Lot
4 LSTTL Loads YY or Y = Year
WW or W = Work Week

Vin Input Voltage Range, 0.5 to VDD + 0.5 V MC14598BCP PDIP18 20/Rail
Enable (DC or Transient)
Vin Input Voltage Range, All Other 0.5 to VDD + 12 V
Inputs (DC or Transient)
Vout Output Voltage Range, 0.5 to VDD + 0.5 V
(DC or Transient)
against damage due to high static voltages or electric
TL Lead Temperature 260 C voltages to this highimpedance circuit. For proper
(8Second Soldering) operation, Vin and Vout should be constrained to the
(Vin or Vout) VDD.

MC14598B
PIN ASSIGNMENT
D0 1 18 VDD
RESET 2 17 D1
DATA 3 16 D2
ENABLE 4 15 D3
NC 5 14 D4
STROBE 6 13 D5
A0 7 12 D6
A1 8 11 D7
VSS 9 10 A2
BLOCK DIAGRAMS
MC14598B ENABLE
OUTPUT
4
TRUTH TABLE
RESET 2
DATA 3 1 D0 Enable Outputs
STROBE 6 17 D1 1 High Impedance
THREE
16 D2 0 Dn
A0 7 8 STATE
OUTPUT 15 D3
A1 8 ADDRESS LATCHES Dn = State of nth latch
BUFFERS 14 D4
A2 10 DECODER 13 D5
NC = NO CONNECTION
12 D6
VDD = 18 11 D7
VSS = 9
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MC14598B
VDD
Vdc Min
55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
Input Voltage (4.) Enable 0 Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 0.8 1.1 0.8 0.8
(VO = 9.0 or 1.0 Vdc) 10 1.6 2.2 1.6 1.6
(VO = 13.5 or 1.5 Vdc) 15 2.4 3.4 2.4 2.4
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 2.0 2.0 1.9 2.0
(VO = 1.0 or 9.0 Vdc) 10 6.0 6.0 3.1 6.0
(VO = 1.5 or 13.5 Vdc) 15 10 10 4.3 10
Other Inputs
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11
Output Drive Current Source IOH mAdc
(Full Sink Only)
(VOH = 4.6 Vdc) 5.0 1.0 1.0 2.0 1.0
(VOH = 9.5 Vdc) 10 6.0
(VOH = 13.5 Vdc) 15 12
(VOL = 0.5 Vdc) 10 6.0
(VOL = 1.5 Vdc) 15 12
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
Total Supply Current at an IT 5.0 IT = (2.0 A/kHz) f + IDD Adc
**External Load Capacitance of 10 IT = (4.0 A/kHz) f + IDD
**130 pF (4.) IT = (6.0 A/kHz) f + IDD
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MC14598B
SWITCHING CHARACTERISTICS (5.) (TA = 25_C, CL = 130 pF + 1 TTL Load)
VDD
Vdc Min
All Types
Typ (6.) Max Unit
Enable to Output tPHL 5.0 160 320
10 125 250
15 100 200
Strobe to Output 5.0 200 400
10 100 200
15 80 160
Reset to Output 5.0 175 350
10 90 180
15 70 140
Pulse Width tWH, ns
Enable tWL 5.0 320 160
10 240 120
15 160 80
Strobe 5.0 200 100
10 100 50
15 80 40
Increment 5.0 200 100
10 100 50
15 80 40
Reset 5.0 300 150
10 160 80
15 100 50
Setup Time tsu ns
Data 5.0 100 50
10 50 25
15 35 20
Address 5.0 200 100
10 100 50
15 70 35
Hold Time th ns
Data 5.0 100 50
10 50 25
15 35 20
Address 5.0 100 50
10 50 25
15 35 20
10 20 15
15 20 10
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MC14598B
MC14598B FUNCTION DIAGRAM
RESET 2 VDD
DATA 3
TO OTHER 1 D0
LATCHES
STROBE 6
ENABLE 4 VSS
EACH LATCH
TO OTHER
LATCHES ZERO
SELECT 17 D1
A0 7 16 D2
15 D3
ADDRESS ADDITIONAL 7 LATCHES 14 D4
A1 8 DECODER 13 D5
12 D6
11 D7
A2 10
(M.S.B)
MC14598B TIMING DIAGRAM
90%
50% 10%
tTHL tPLH
D7 1 50% 90%
10%
tPLH tPHL tTLH
RESET
20 ns
tW 90%
A0, A1, A2 50% 10%
tsu th
DATA
tsu th
90% 90%
STROBE 10% 50% 10%
20 ns 20 ns tW
ENABLE *
tW
*1.4 V with VDD = 5.0 V

NOTES:
1. Highimpedance output state (another device controls bus).
2. Output Load as for MC14597B.
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MC14598B
LATCH TRUTH TABLE TRUTH TABLE FOR MC14597B

Address Other Address
Strobe Reset Latch Latches Increment Enable Reset Counter Full
0 1 * * X 1 Count Up
1 1 Data * X 1 No Change
X 0 0 0 X 1 0 Reset to Zero Set to One
*= No change in state of latch X 0 1 No Change Set to One
X = Dont care If at To Zero on

X 1 1 ADDRESS 7 Falling Edge
of STROBE
X = Dont care
TEST LOAD
ALL OUTPUTS
+5.0 V
RL = 2.5 k
Dn
130 pF 11.7 k
Circuit diagrams external to or containing Motorola The information contained herein is for guidance only,
products are included as a means of illustration only. with no warranty of any type, expressed or implied.
Complete information sufficient for construction purposes Motorola reserves the right to make any changes to the
may not be fully illustrated. Although the information herein information and the product(s) to which the information
has been carefully checked and is believed to be reliable. applies and to discontinue manufacture of the product(s) at
Motorola assumes no responsibility for inaccuracies. any time.
Information herein does not convey to the purchaser any
license under the patent rights of Motorola or others.
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CHAPTER 7
CMOS Reliability
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431
RELIABILITY usually expressed in percent failures per thousand hours.
Paramount in the mind of every semiconductor user is the Other forms include FIT (Failures in Time = (%/103 hrs) x
question of device performance versus time. After the 104 = 109 failures per hour) and MTTF (Mean Time To
applicability of a particular device has been established, its Failure) or MTBF (Mean Time Between Failures), both
effectiveness depends on the length of troublefree service it being equal to 1/ and having units of hours.
can offer. The reliability of a device is exactly that an Since reliability evaluations usually involve only samples
expression of how well it will serve the customer. The of an entire population of devices, the concepts of the
following discussion will attempt to present an overview of Central Limit Theorem apply and is calculated using x2
ON Semiconductors reliability efforts. distribution through the equation:
BASIC CONCEPTS vx 2 (x, 2r + 2)

2nt
It is essential to begin with an explanation of the various
100 CL
parameters of Reliability. These are probably summarized where x =
100
best in the Bathtub Curve (Figure 1). The reliability
performance of a device is characterized by three phases: CL = Confidence Limit in percent
infant mortality, useful life, and wearout. When a device is r = Number of rejects
produced, there is often a small distribution of failure n = Number of devices
mechanisms which will exhibit themselves under relatively t = Duration of test
moderate stress levels and therefore appear early. This The confidence limit is the degree of conservatism desired
period of early failures, termed infant mortality is reduced in the calculation. The Central Limit Theorem states that the
significantly through proper manufacturing controls and values of any sample of units out of a large population will
screening techniques. The most effective period is that in produce a normal distribution. A 50% confidence limit is
which only occasional random failure mechanisms appear. termed the best estimate and is the mean of this distribution.
The useful life typically spans a long period of time with a A 90% confidence limit is a very conservative value and
very low failure rate. The final period is that in which the results in a higher which represents the point at which 90%
devices literally wear out due to continuous phenomena of the area of the distribution is to the left of that value
which existed at the time of manufacture. Using strictly (Figure 2). The term (2r + 2) is called the degrees of freedom
controlled design techniques and selectivity in applications, and is an expression of the number of rejects in a form
this period is shifted well beyond the lifetime required by the suitable to x2 tables.
user.
50% CL
FREQUENCY
90% CL
INFANT MORTALITY
FAILURE RATE
(SUCH AS EARLY
BURNIN FAILURES)
, FAILURE RATE
WEAROUT
USEFUL LIFE FAILURES
Figure 2.
The number of rejects is a critical factor since the

10 100 1000 10,000 100,000 1,000,000
definition of rejects often differs between manufacturers.
TIME (HOURS)
While ON Semiconductor uses data sheet limits to
Figure 1. determine failures, sometimes rejects are counted only if
they are catastrophic. Due to the increasing chance of a test
Both the infant mortality and random failure rate regions not being representative of the entire population, as sample
can be described through the same types of calculations. size and test time are decreased, the x2 calculation produces
During this time the probability of having no failures to a surprisingly high values of for short test durations even
specific point in time can be expressed by the equation: though the true long term failure rate may be quite low. For
Po = e t this reason relatively large amounts of data must be gathered
where is the failure rate and t is time. Since is changing to demonstrate the real long term failure rate.
rapidly during infant mortality, the expression does not Since this would require years of testing on thousands of
become useful until the random period, where is relatively devices, methods of accelerated testing have been
constant. In this equation is failures per unit of time. It is developed.
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432
Years of semiconductor device testing has shown that devices will be used (Figure 3). For Discrete products, 0.7
temperature will accelerate failures and that this behavior eV is generally applied.
fits the form of the Arrhenius equation: To accomplish this, the time in device hours (t1) and
R (t) = R0(t)e /kT temperature (T1) of the test are plotted as point P1. A vertical
line is drawn at the temperature of interest (T2) and a line
where R(t) = Reaction rate as a function of time and
with a 1.0 eV slope is drawn through point P1.
temperature
Its intersection with the vertical line defines point P2, and
R0 = A constant
determines the number of equivalent device hours (t2). This
t = Time
number may then be used with the x2 formula to determine
= Activation energy in electron volts
the failure rate at the temperature of interest. Assuming T1
k = Boltzmans constant
of 125_C at t1 of 10,000 hours, a t2 of 7.8 million hours
T = Temperature in degrees Kelvin
results at a T2 of 50_C. If one reject results in the 10,000
To provide timetemperature equivalents this equation is device hours of testing at 125_C, the failure rate at that
applied to failure rate calculations in the form: temperature will be 0.1%/1,000 hours using a 60%
t = t0e /kT confidence level. One reject at the equivalent 7.8 million
where t = time device hours at 50_C will result in a 0.0008%/1,000 hour
t0 = A constant failure rate, as illustrated in Figure 4.
The Arrhenius equation essentially states that reaction Three parameters determine the failure rate quoted by the
rate increases exponentially with temperature. This manufacturer: the failure rate at the test temperature, the
produces a straight line when plotted in loglinear paper activation energy employed, and the difference between the
with a slope expressed by . may be physically test temperature and the temperature of the quoted . A term
interpreted as the energy threshold of a particular reaction or often used in this manipulation is the acceleration factor
failure mechanism. The activation energy exhibited by which is simply the equivalent device hours at the lower
semiconductors varies from about 0.3 eV. Although the temperature divided by the actual test device hours.
relationships do not prohibit devices from having poor Every device will eventually fail, but with the present
failure rates and high activation energies, good performance techniques in Semiconductor design and applications, the
usually does not imply a high . Studies by Bell Telephone wearout phase is extended far beyond the lifetime required.
Laboratories have indicated that an overall for During wearout, as in infant mortality, the failure rate is
semiconductors is 1.0 eV. This value has been accepted by changing rapidly and therefore loses its value. The
the Rome Air Development Command for parameter used to describe performance in this area is
timetemperature acceleration in powered burnin. Data Median Life and is the point at which 50% of the devices
taken by ON Semiconductor on Integrated Circuits have have failed. There are currently only few significant wearout
verified this number and it is therefore applied as our mechanisms: electromigration of circuit metallization,
standard timetemperature regression for extrapolation of electrolytic corrosion in plastic devices and metal fatigue for
high temperature failure rates to temperatures at which the Power devices.
1.2 1.6 2.0 2.4 2.8 3.2 3.6 1.2 1.6 2.0 2.4 2.8 3.2 3.6
1000 k 100 100 k
100 k 10
, FAILURE RATE (%/1000 HOURS)
10 k 1.0
t2
TIME (HOURS)
P2
1.0 k
2
100
0.01
10
t1
P1 1
1.0 eV
1.0
SLOPE
0.0001
0.1
T1 T2 0.00001
500 200 100 50 0
TEMPERATURE (C) 500 200 100 50 0
Figure 3. Normalized TimeTemperature TEMPERATURE (C)
Regressions for Various Activation Energy Values Figure 4. Failure Rate
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For increased flexibility in working with a broad range of where
device hours, the timetemperature regression lines have TJ = maximum junction temperature
been normalized to 500_C and the time scale omitted, TA = maximum ambient temperature
permitting the user to define the scale based on his own PD = calculated maximum power dissipation
requirements. including effects of external loads (see
Power Dissipation in section III).
THERMAL MANAGEMENT
JC = average thermal resistance, junction to case
Circuit performance and longterm circuit reliability are CA = average thermal resistance, case to ambient
affected by die temperature. Normally, both are improved by JA = average thermal resistance, junction to
keeping the IC junction temperatures low. ambient
Electrical power dissipated in any integrated circuit is a
This ON Semiconductor recommended formula has been
source of heat. This heat source increases the temperature of
approved by RADC or DESC for calculating a practical
the die relative to some reference point, normally the
maximum operating junction temperature for
ambient temperature of 25_C in still air. The temperature
MILM38510 (JAN) devices.
increase, then, depends on the amount of power dissipated
Only two terms on the right side of equation (1) can be
in the circuit and on the net thermal resistance between the
varied by the user the ambient temperature, and the
heat source and the reference point.
device casetoambient thermal resistance, CA. (To some
The temperature at the junction is a function of the
extent the device power dissipation can also be controlled,
packaging and mounting systems ability to remove heat
but under recommended use the VCC supply and loading
generated in the circuit from the junction region to the
dictate a fixed power dissipation.) Both system air flow and
ambient environment. The basic formula for converting
the package mounting technique affect the CA thermal
power dissipation to estimated junction temperature is:
resistance term. JC is essentially independent of air flow
TJ = TA + PD(JC + CA) (1) and external mounting method, but is sensitive to package
or TJ = TA + PD(JA)
(2) material, die bonding method, and die area.
Thermal Resistance in Still Air

Package Description
JC (_C/Watt)

No. Body Body Body Die Die Area Flag Area

Leads Style Material WxL Bonds (Sq. Mils) (Sq. Mils) Avg. Max.

14 DIL Epoxy 1/4 x 3/4 Epoxy 4096 6,400 38 61
16 DIL Epoxy 1/4 x 3/4 Epoxy 4096 12,100 34 54
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is DualInLine.
3. Standard Mounting Method: DualInLine Socket or P/C board with no contact between bottom of package and socket or P/C board.
Figure 5. Thermal Resistance Values for Standard I/C Packages
For applications where the case is held at essentially a These figures show the proportionate increase in the
fixed temperature by mounting on a large or junction temperature of each dual inline package as the air
temperaturecontrolled heat sink, the estimated junction passes over each device. For higher rates of air flow the
temperature is calculated by: change in junction temperature from package to package

TJ = TC + PD(JC) (3) down the airstream will be lower due to greater cooling.

where TC = maximum case temperature and the other
Power Dissipation Junction Temperature Gradient

parameters are as previously defined. (mW) (_C/Package)
The maximum and average JC resistance values for

200 0.4
standard IC packages are given in Figure 5.

250 0.5
AIR FLOW

300 0.63
The majority of users employ some form of airflow

400 0.88
cooling. As air passes over each device on a printed circuit
board, it absorbs heat from each package. This heat gradient Devices mounted on 0.062 PC board with Z axis spacing of 0.5.
Air flow is 500 Ifpm along the Z axis.
from the first package to the last package is a function of the
air flow rate and individual package dissipations. Figure 6 Figure 6. Thermal Gradient of Junction Temperature
provides gradient data at power levels of 200 mW, 250 mW, (16Pin DualinLine Package)
300 mW, and 400 mW with an air flow rate of 500 Ifpm.
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OPTIMIZING THE LONG TERM RELIABILITY OF Table 1 is graphically illustrated in Figure 7 which shows
PLASTIC PACKAGES that the reliability for plastic and ceramic devices are the
Todays plastic integrated circuit packages are as reliable same until elevated junction temperatures induces
as ceramic packages under most environmental conditions. intermetallic failures in plastic devices. Early and midlife
However when the ultimate in system reliability is required, failure rates of plastic devices are not effected by this
thermal management must be considered as a prime system intermetallic mechanism.
design goal.
Modern plastic package assembly technology utilizes
gold wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
FAILURE RATE OF PLASTIC = CERAMIC
protracted periods of time an intermetallic compound can UNTIL INTERMETALLIC FAILURES OCCUR
form in the bond area resulting in high impedance contacts
NORMALIZED FAILURE RATE

and degradation of device performance. Since the formation
of intermetallic compounds is directly related to device
junction temperature, it is incumbent on the designer to
TJ = 130C
TJ = 120C
TJ = 110C
TJ = 100C
TJ = 90 C
TJ = 80 C
determine that the device junction temperatures are
consistent with system reliability goals.
Predicting Bond Failure Time:

Based on the results of almost ten (10) years of +125_C 1
operating life testing, a special arrhenius equation has been
developed to show the relationship between junction
temperature and reliability. 1 10 100 1000
TIME, YEARS
11554.267
Eq. (1) T = (6.376 x 109)e
273.15 + TJ Figure 7. Failure Rate versus Time
Where: T = Time in hours to 0.1% bond failure Junction Temperature
T = (1 failure per 1,000 bonds).
TJ = Device junction temperature, _C.
And:
Eq. (2) TJ = TA + PDJA = TA + TJ
Procedure
Where: TJ = Device junction temperature, _C. After the desired system failure rate has been established
TA = Ambient temperature, _C. for failure mechanisms other than intermetallics, each
PD = Device power dissipation in watts. device in the system should be evaluated for maximum
JA = Device thermal resistance, junction to air, junction temperature. Knowing the maximum junction
_C/Watt. temperature, refer to Table 1 or Equation 1 to determine the
TJ = Increase in junction temperature due to continuous operating time required to 0.1% bond failures
onchip power dissipation. due to intermetallic formation. At this time, system
Table 1 shows the relationship between junction reliability departs from the desired value as indicated in
temperature, and continuous operating time to 0.1%. bond Figure 7.
failure, (1 failure per 1,000 bonds). Air flow is one method of thermal management which
should be considered for system longevity. Other commonly
Table 1. Device Junction Temperature versus Time

used methods include heat sinks for higher powered devices,
to 0.1% Bond Failures refrigerated air flow and lower density board stuffing. Since

Junction

Temperature _C Time, Hours Time, Years
CA is entirely dependent on the application, it is the
responsibility of the designer to determine its value. This can

80 1,032,200 117.8 be achieved by various techniques including simulation,
modeling, actual measurement, etc.

90 419,300 47.9
100 178,700 20.4 The material presented here emphasizes the need to

110

120
79,600
37,000
9.4
4.2
consider thermal management as an integral part of system
design and also the tools to determine if the management

methods being considered are adequate to produce the
130 17,800 2.0
desired system reliability.

140 8,900 1.0
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PD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)
PD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)

150C 150C
137C 500 500
135C
TJ , JUNCTION TEMPERATURE ( C)
TJ , JUNCTION TEMPERATURE ( C)
139C 134C
125C TJ SOIC 400 125C
129C 130C 400
121C
PD TJ SOIC PD
TJ PDIP 300 300
100C 99C PDIP & SOIC 100C PDIP & SOIC
7 mW/C 98C 7 mW/C
200 89C 200
81C
75C 75C TJ PDIP
100 100
58C
50C 50C
25C 65C 125C 25C 65C 125C
TA, AMBIENT TEMPERATURE TA, AMBIENT TEMPERATURE
Figure 8. Junction Temperature for Worst Case Figure 9. Junction Temperature for Typical
CMOS Logic Device CMOS Logic Device
This graph illustrates junction temperature for the worst case CMOS This graph illustrates junction temperature for a CMOS Logic device
Logic device (MC14007UB) smallest die area operating at (MC14053B) average die area operating at maximum power
maximum power dissipation limit in still air. The solid line indicates dissipation limit in still air. The solid line indicates the junction
the junction temperature, TJ, in a DualInLine (PDIP) package and temperature, TJ, in a DualInLine (PDIP) package and in a Small
in a Small Outline IC (SOIC) package versus ambient temperature, Outline IC (SOIC) package versus ambient temperature, TA. The
TA. The dotted line indicates maximum allowable power dissipation dotted line indicates maximum allowable power dissipation derated
derated over the ambient temperature range, 25_C to 125_C. over the ambient temperature range, 25_C to 125_C.
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CHAPTER 8
Equivalent Gate Count
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EQUIVALENT GATE COUNT
The following is a list of equivalent gate counts for some of ON Semiconductors CMOS devices. In general for CMOS,
the number of equivalent gates is equal to the total number of transistors on chip divided by four. This list includes only those
devices with equivalent gate counts known at the time of this printing.
EQUIVALENT EQUIVALENT
DEVICE GATE COUNT DEVICE GATE COUNT
MC14001B 8 MC14081B 10
MC14001UB 4 MC14082B 8
MC14007UB 1.5 MC14093B 18
MC14008B 40 MC14094B 79
MC14011B 8 MC14099B 70
MC14011UB 4 MC14174B 43.5
MC14012B 7 MC14175B 39.5
MC14013B 16 MC14490 136.5
MC14014B 74 MC14503B 17
MC14015B 53 MC14504B 37.5
MC14016B 8 MC14511B 54
MC14017B 62.5 MC14512B 17.25
MC14018B 38.25 MC14514B 59
MC14020B 84 MC14515B 67
MC14021B 74 MC14516B 61
MC14023B 9 MC14517B 119
MC14024B 59 MC14518B 43.5
MC14025B 9 MC14520B 43.5
MC14028B 26 MC14526B 86
MC14029B 65.5 MC14528B 24
MC14040B 73 MC14532B 38.5
MC14042B 17.5 MC14536B 103
MC14046B 35 MC14538B 38
MC14049UB 3 MC14541B 93
MC14049B 9 MC14543B 52
MC14050B 6 MC14549B 122
MC14051B 48.5 MC14551B 35
MC14052B 38.5 MC14553B 147.5
MC14053B 38 MC14555B 21
MC14060B 73.5 MC14556B 25
MC14066B 13 MC14557B 232.5
MC14067B 65 MC14559B 122
MC14069UB 3 MC14562B 206
MC14071B 10 MC14569B 156
MC14073B 10.5 MC14572UB 4
MC14076B 32.5 MC14584B 18
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CHAPTER 9
Packaging Information Including Surface Mounts
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PACKAGE DIMENSIONS
The standard package availability for each device is indicated on the front page of the individual data sheets. Dimensions
for the packages are given in this chapter. Surface mount packages may be special ordered by specifying the following suffixes:
D (narrow SOIC), DW (wide SOIC), or DT (TSSOP). For example, to order a quad NOR gate, use MC14001BD.
14-Pin Packages
PDIP14
P SUFFIX
PLASTIC PACKAGE
CASE 64606
ISSUE M NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
T J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M 10_ 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01
0.13 (0.005) M
SOIC14
D SUFFIX
PLASTIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
A Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
T F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
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14-Pin Packages (continued)
TSSOP14
DT SUFFIX
PLASTIC PACKAGE
CASE 948G01
ISSUE O
14X K REF NOTES:
0.10 (0.004) M T U S V S Y14.5M, 1982.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
N (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
2X L/2 FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
U N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
IDENT. F EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1 7 6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES

V K1 DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

B 4.30 4.50 0.169 0.177
J J1 C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION NN G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C W K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
T SEATING D G H DETAIL E
PLANE
SOEIAJ14
F SUFFIX
PLASTIC PACKAGE NOTES:
CASE 96501 Y14.5M, 1982.
ISSUE O 3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
14 8 LE REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
Q1 INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
E HE M_ TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
1 7 L BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P MILLIMETERS INCHES
Z
DIM MIN MAX MIN MAX
D A 2.05 0.081
A1 0.05 0.20 0.002 0.008
VIEW P b 0.35 0.50 0.014 0.020
e A c 0.18 0.27 0.007 0.011
c D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
b A1 LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
0.13 (0.005) M 0.10 (0.004) Q1 0.70 0.90 0.028 0.035
Z 1.42 0.056
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16-Pin Packages
PDIP16
P SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
T PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
SOIC16
D SUFFIX
PLASTIC PACKAGE
CASE 751B05
A ISSUE J
NOTES:
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
B MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
T SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019
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SOEIAJ16
F SUFFIX NOTES:
PLASTIC PACKAGE Y14.5M, 1982.
CASE 96601 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
ISSUE O MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
16 9 LE 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
Q1 5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
E HE M_ DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
1 8 L RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
DETAIL P TO BE 0.46 ( 0.018).
Z MILLIMETERS INCHES
D DIM MIN MAX MIN MAX
A 2.05 0.081
A1 0.05 0.20 0.002 0.008
VIEW P
e A b 0.35 0.50 0.014 0.020
c c 0.18 0.27 0.007 0.011
D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
A1 L 0.50 0.85 0.020 0.033
b LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
0.13 (0.005) M 0.10 (0.004) Q1 0.70 0.90 0.028 0.035
Z 0.78 0.031
TSSOP16
DT SUFFIX
PLASTIC PACKAGE NOTES:
CASE 948F01 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE O 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
16X K REF FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
0.10 (0.004) M T U S V S (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
0.15 (0.006) T U S FLASH OR PROTRUSION. INTERLEAD FLASH OR
K PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.
K1 5. DIMENSION K DOES NOT INCLUDE DAMBAR

16 9 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
2X L/2 J1 EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
B SECTION NN REFERENCE ONLY.
L U 7. DIMENSION A AND B ARE TO BE DETERMINED
J AT DATUM PLANE W.
PIN 1
IDENT. MILLIMETERS INCHES
DIM MIN MAX MIN MAX
1 8
A 4.90 5.10 0.193 0.200
N B 4.30 4.50 0.169 0.177
0.25 (0.010) C 1.20 0.047
D 0.05 0.15 0.002 0.006
0.15 (0.006) T U S
F 0.50 0.75 0.020 0.030
A M
G 0.65 BSC 0.026 BSC
V H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
N J1 0.09 0.16 0.004 0.006
F K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
DETAIL E M 0_ 8_ 0_ 8_
C W
0.10 (0.004)
T SEATING H DETAIL E
PLANE D G
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SOIC16
DW SUFFIX
PLASTIC PACKAGE
CASE 751G03
D A ISSUE B
q
16 9
NOTES:
M
1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
B
PER ASME Y14.5M, 1994.

H
h X 45 _
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
M
E
8X
PROTRUSION.
0.25
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
1 8 OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16X B B MILLIMETERS
DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
A
e 1.27 BSC
H 10.05 10.55
L
SEATING h 0.25 0.75
14X e PLANE
L 0.50 0.90
A1
T C q 0_ 7_
18-Pin Package
PDIP18
P SUFFIX
PLASTIC PACKAGE
CASE 70702
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
18 10 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
B 2. DIMENSION L TO CENTER OF LEADS WHEN
1 9 FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
A MILLIMETERS INCHES
DIM MIN MAX MIN MAX
L A 22.22 23.24 0.875 0.915
C B 6.10 6.60 0.240 0.260
C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
N K G 2.54 BSC 0.100 BSC
J H 1.02 1.52 0.040 0.060
F D SEATING M J 0.20 0.30 0.008 0.012
PLANE K 2.92 3.43 0.115 0.135
H G L 7.62 BSC 0.300 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040
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24-Pin Packages
PDIP24
P SUFFIX
PLASTIC PACKAGE
CASE 70902
ISSUE C NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
24 13 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 12 FLASH.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.37 32.13 1.235 1.265
A C L B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
N D 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
K G 2.54 BSC 0.100 BSC
H 1.65 2.03 0.065 0.080
H F M J J 0.20 0.38 0.008 0.015
SEATING K 2.92 3.43 0.115 0.135
G D PLANE
L 15.24 BSC 0.600 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040
SOIC24
DW SUFFIX
PLASTIC PACKAGE
CASE 751E04
ISSUE E
24 13 NOTES:
Y14.5M, 1982.
B 12X P MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
0.010 (0.25) M B M
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 12 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
24X D J
MILLIMETERS INCHES
0.010 (0.25) M T A S B S
DIM MIN MAX MIN MAX
A 15.25 15.54 0.601 0.612
F B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
R X 45 _ D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
C J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
T M 0_ 8_ 0_ 8_
SEATING M P 10.05 10.55 0.395 0.415
PLANE 22X G K R 0.25 0.75 0.010 0.029
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ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES
UNITED STATES CANADA INTERNATIONAL (continued)
ALABAMA ONTARIO KOREA
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Detroit . . . . . . . . . . . . . . . . . . . . . (248)3476800 Munich . . . . . . . . . . . . . . . . . . . . 49 89 921030 Stockholm . . . . . . . . . . . . . . . . . 46(8)7348800
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Plymouth . . . . . . . . . . . . . . . . . . (612)2492360 Hong Kong . . . . . . . . . . . . . . . 85226106888 Taipei . . . . . . . . . . . . . . . . . . . 886(2)27058000
NORTH CAROLINA INDIA THAILAND
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PENNSYLVANIA ISRAEL UNITED KINGDOM
Philadelphia/Horsham . . . . . . . (215)9574100 Tel Aviv . . . . . . . . . . . . . . . . . . . 97299522333 Aylesbury . . . . . . . . . . . . . . . 44 1 (296)395252
TEXAS ITALY
Dallas . . . . . . . . . . . . . . . . . . . . . (972)5165100 Milan . . . . . . . . . . . . . . . . . . . . . . . . 39(02)82201
JAPAN
Tokyo . . . . . . . . . . . . . . . . . . . 81354878345
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ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS
REFERENCE MANUAL
A Reference Manual is a publication that contains a comprehensive system or devicespecific description of the structure and function
(operation) of a particular part/system; used overwhelmingly to describe the functionality of a microprocessor, microcontroller, or some
other submicron sized device. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).
USERS GUIDE
A Users Guide contains procedural, taskoriented instructions for using or running a device or product. A Users Guide differs from
a Reference Manual in the following respects:
* Majority of information (> 60%) is procedural, not functional, in nature
* Volume of information is typically less than for Reference Manuals
* Usually written more in active voice, using secondperson singular (you) than is found in Reference Manuals
* May contain photographs and detailed line drawings rather than simple illustrations that are often found in Reference Manuals
POCKET GUIDE
A Pocket Guide is a pocketsized document that contains technical reference information. Types of information commonly found in
pocket guides include block diagrams, pinouts, alphabetized instruction set, alphabetized registers, alphabetized thirdparty vendors and
their products, etc.
ADDENDUM
A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the
primary publication it supports. Individual addendum items are published cumulatively. Addendums end with the next revision of the
primary document.
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An Application Note is a document that contains realworld application information about how a specific ON Semiconductor
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must already exist and be available.
A document called ApplicationSpecific Information is not the same as an Application Note.
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A Selector Guide is a trifold (or larger) document published on a regular basis (usually quarterly) by many, if not all, divisions, that
contains key lineitem, devicespecific information for particular product families. Some Selector Guides are published in book format
and contain previously published information.
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A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The Product
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The Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces the Advance Information
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ENGINEERING BULLETIN
An Engineering Bulletin is a writeup that typically focuses on a single specific solution for a particular engineering or programming issue
involving one or several devices.
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DL131/D
Rev. 4, Mar-2000
CMOS Logic Data
ON Semiconductor
ON Semiconductor
CMOS Logic Data

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
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special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
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DL131/D 03/00
DL131
REV 4
DL111/D
Rev. 8, July-2001
Bipolar Power Transistor Data

Bipolar Power Transistor Data
DL111/D
Rev. 8, Jul2001
SCILLC, 2001
Previous Edition 1995
All Rights Reserved
Grafoil is a registered Trademark of Union Carbide.
KonDux and RubberDuc are trademarks of Aavid Thermal Technologies, Inc.
Thermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc.
Kapton is a registered trademark of du Pont de Nemours & Co., Inc.
SilPad is a registered trademark of the Bergquist Company.
CHOTHERM is a registered trademark of Chomerics, Inc.
FULLPAK, ICePAK, PowerBase, SCANSWITCH, SWITCHMODE, and Thermopad are trademarks of Semiconductor Components
Industries, LLC.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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2
Table of Contents
Chapter 1. Selector Guide Chapter 2. Data Sheets

Page Page
Bipolar Power Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bipolar Power Transistor Data Sheets . . . . . . . . . . . . 23
Selection by Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Plastic TO220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Plastic TO218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 3. Applications Information and
Plastic (Isolated TO-220 Type) . . . . . . . . . . . . . . . . 13 Case Outlines
Large Plastic TO-264 . . . . . . . . . . . . . . . . . . . . . . . . 13 Application Note: A HighPerformance
Plastic TO225AA Type Video Amplifier for High Resolution
(Formerly TO126 Type) . . . . . . . . . . . . . . . . . . . . 14 CRT Applications (AN1040/D) . . . . . . . . . . . . . . . . . 751
DPAK Surface Mount Power Packages . . . . . . . 16 Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Metal TO204AA (Formerly TO3),
TO204AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Plastic TO247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 4. Numeric Index
D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Alpha Numeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . 783
SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sales Office Listing . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document Type Definitions . . . . . . . . . . . . . . . . . . . . 788
Electronic Lamp Ballasts . . . . . . . . . . . . . . . . . . . . . . . . 21
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4
CHAPTER 1
Selector Guide
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5
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6
Bipolar Power
Transistors
In Brief . . .
ON Semiconductors broad line of Bipolar Power Page
Transistors includes discrete and Darlington transistors Bipolar Power Transistors . . . . . . . . . . . . . . . . . . . . . . 8
in a variety of packages from the popular surface mount Selection by Package . . . . . . . . . . . . . . . . . . . . . . . 8
DPAK at 1.75 watts to the 250 watt TO-3. We now have Plastic TO220AB . . . . . . . . . . . . . . . . . . . . . . . . 9
transistors in SO8 (Dual Transistors) and SOT223. We Plastic TO218 . . . . . . . . . . . . . . . . . . . . . . . . . 12
have a broad line of Electronic Lamp Ballast Transistors, Plastic (Isolated TO-220 Type) . . . . . . . . . . . . 13
Large Plastic TO-264 . . . . . . . . . . . . . . . . . . . . 13
in the BUL Series and MJD18002D2T4, MJE18002, and
Plastic TO225AA Type
MJE18004D24. New products include low VCE(sat)
(Formerly TO126 Type) . . . . . . . . . . . . . . . . 14
devices in surface mount SOT223 package, DPAK Surface Mount Power Packages . . . 16
MMJT9435T1/MMJT9410T1 and in the SO8 package Metal TO204AA (Formerly TO3),
(Dual Transistors), MMDJ3N03BJTR2/ TO204AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MMDJ3P03BJTR2. We also have a broad line of high Plastic TO247 . . . . . . . . . . . . . . . . . . . . . . . . . 19
performance Audio Output Transistors in TO3, TO264 D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
and new products in the Isolated Hole Plastic TO247 SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
package. The new TO247 devices are designated Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electronic Lamp Ballasts . . . . . . . . . . . . . . . . . . . . 21
MJW21191/2/3/4/5/6 and high fT, MJW3281A/1302A.
These have excellent high voltage FBSOA performance.
ON Semiconductor has a commitment to quality and
total customer satisfaction.
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7
BIPOLAR POWER TRANSISTORS SELECTOR GUIDE
SELECTION BY PACKAGE
IC Range VCE Range PD
Package
(Amps) (Volts) (Watts)
TO-204AA 4.0-30 40-250 115-250

(TO-3)
TO-204AE 3060 60-120 150-300

(TO3)
DPAK 0.5-10 40-450 12.5-20
DPAK 0.5-10 40-450 12.5-20
TO-220AB 0.5-15 60-400 30-125
Isolated 1.0-12 60-450 20-45

TO-220 Type
TO-225AA 0.3-5.0 25-400 12.5-40

(TO-126 Type)
SOT223 3.0 30 2.0 (Note 1.)
SO8 3.0 30 2.0 (Note 2.)
TO-264 15-16 200-250 250
D2PAK 5.08.0 80450 5065
TO247 8.016 150250 200
TO218 5.010 60350 125150
1. Tested on 1 sq. FR4 Board

2. Tested on 1 sq., 2 oz. copper
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8
Plastic TO220AB
Device Type Resistive Switching

PD
ICCont VCEO(sus) ts tf fT (Case)
Amps Volts Min hFE @ IC s s @ IC MHz Watts
Max (Note 7.) NPN PNP Min/Max Amp Max Max Amp Min @ 25C Page
1.0 80 TIP29B TIP30B 15/75 1.0 0.6 typ 0.3 typ 1.0 3.0 30 725
100 TIP29C TIP30C 15/75 1.0 0.6 typ 0.3 typ 1.0 3.0 30 725
250 TIP47 30/150 0.3 2.0 typ 0.18 typ 0.3 10 40 747
300 TIP48 MJE5730 30/150 0.3 2.0 typ 0.18 typ 0.3 10 40 747,
581
350 MJE5731 30/150 0.3 2.0 typ 0.18 typ 0.3 10 40 581
400 TIP50 MJE5731A 30/150 0.3 2.0 typ 0.18 typ 0.3 10 40 747,
(Note 6.) 581
2.0 60 TIP110 TIP115 500 min 2.0 1.7 typ 1.3 typ 2.0 25 50
(Note 4.) (Note 4.) (Note 3.) 709
80 TIP111 TIP116 500 min 2.0 1.7 typ 1.3 typ 2.0 25 50
(Note 4.) (Note 4.) (Note 3.) 709
100 TIP112 TIP117 500 min 2.0 1.7 typ 1.3 typ 2.0 25 50
(Note 4.) (Note 4.) (Note 3.) 709
400/700 BUL44 14/36 0.4 2.75 0.175 1.0 13 typ 50
(Note 5.) (Note 5.) 279
450/1000 BUX85 30 0.1 3.5 1.4 1.0 4.0 50 313
450/1000 MJE18002 14/34 0.2 3.0 0.17 1.0 12 typ 40
(Note 5.) (Note 5.) 505
3.0 60 TIP31A TIP32A 25 min 1.0 0.6 typ 0.3 typ 1.0 3.0 40 729
80 TIP31B TIP32B 25 min 1.0 0.6 typ 0.3 typ 1.0 3.0 40 729
100 BD241C BD242C 25 min 1.0 3.0 40 157
TIP31C TIP32C 25 min 1.0 0.6 typ 0.3 typ 1.0 3.0 40 729
4.0 80 D44C12 D45C12 40/120 0.2 1.0 40 typ 30 320
400/700 MJE13005 6/30 3.0 3.0 0.7 3.0 4.0 60 468
5.0 60 TIP120 TIP125 1k min 3.0 1.5 typ 1.5 typ 3.0 4.0 65
(Note 4.) (Note 4.) (Note 3.) 715
80 TIP121 TIP126 1k min 3.0 1.5 typ 1.5 typ 3.0 4.0 65
(Note 4.) (Note 4.) (Note 3.) 715
100 TIP122 TIP127 1k min 3.0 1.5 typ 1.5 typ 4.0 4.0 75
(Note 4.) (Note 4.) (Note 3.) 715
250 2N6497 10/75 2.5 1.8 0.8 2.5 5.0 80 133
400/700 BUL45 14/34 0.3 1.7 0.15 1.0 12 typ 75
(Note 5.) (Note 5.) 296
450/1000 MJE18004 14/34 0.3 1.7 0.15 1.0 13 75 522
MJE18004D2* 512
3. |hFE| @ 1.0 MHz
4. Darlington
5. Switching tests performed with special application simulator circuit. See data sheet for details.
6. VCEO = 375 V
7. When 2 voltages are given, the format is VCEO(sus)/VCES.
*D2 suffix indicates transistor with built in CE freewheeling diode and antisaturation network.
Devices listed in bold, italic are ON Semiconductor preferred devices.
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9
Plastic TO220AB (continued)

PD
Amps Volts Min hFE @ IC s s @ IC MHz Watts Page
Max (Note 11.) NPN PNP Min/Max Amp Max Max Amp Min @ 25C
6.0 60 TIP41A TIP42A 15/75 3.0 0.4 typ 0.15 typ 3.0 3.0 65 742
80 TIP41B TIP42B 15/75 3.0 0.4 typ 0.15 typ 3.0 3.0 65 742
BD243B BD244B 15 min 3.0 0.4 typ 0.15 typ 3.0 3.0 65 162
100 BD243C BD244C 15 min 3.0 0.4 typ 0.15 typ 3.0 3.0 65 162
TIP41C TIP42C 15/75 3.0 0.4 typ 0.15 typ 3.0 3.0 65 742
400/700 BUL146 14/34 0.5 1.75 0.15 3.0 14 typ 100
(Note 10.) (Note 10.) 263
450/1000 MJE18006 14/34 0.5 3.2 0.13 3.0 14 typ 100
(Note 10.) (Note 10.) 531
7.0 30 2N6288 2N6111 30/150 3.0 0.4 typ 0.15 typ 3.0 4.0 40 107
50 2N6109 30/150 2.5 0.4 typ 0.15 typ 3.0 4.0 40 107
70 2N6292 2N6107 30/150 2.0 0.4 typ 0.15 typ 3.0 4.0 40 107
150 BU407 30 min 1.5 0.75 5.0 10 60 214
200 BU406 30 min 1.5 0.75 5.0 10 60 214
8.0 60 2N6043 2N6040 1k/10k 4.0 1.5 typ 1.5 typ 3.0 4.0 75
(Note 9.) (Note 9.) (Note 8.) 98
TIP100 TIP105 1k/20k 3.0 1.5 typ 1.5 typ 3.0 4.0 80
(Note 9.) (Note 9.) (Note 8.) 704
80 BDX53B BDX54B 750 min 3.0 4.0 60
(Note 9.) (Note 9.) (Note 8.) 203
TIP101 TIP106 1k/20k 3.0 1.5 typ 1.5 typ 3.0 4.0 80
(Note 9.) (Note 9.) (Note 8.) 704
100 2N6045 2N6042 1k/10k 3.0 1.5 typ 1.5 typ 3.0 4.0 75
(Note 9.) (Note 9.) (Note 8.) 98
BDX53C BDX54C 750 min 3.0
(Note 9.) (Note 9.) 203
TIP102 TIP107 1k/20k 3.0 1.5 typ 1.5 typ 3.0 4.0 80
(Note 9.) (Note 9.) (Note 8.) 704
120 MJE15028 MJE15029 20 min 4.0 30 50 492
150 MJE15030 MJE15031 20 min 4.0 30 50 492
300/600 MJE5740 200 min 4.0 8.0 typ 2.0 typ 6.0 4.0 80
(Note 9.) 585
300 MJE5850 15 min 2.0 2.0 0.5 4.0 80 590
350 MJE5851 15 min 2.0 2.0 0.5 4.0 80 590
400 MJE5742 200 min 4.0 8.0 typ 2.0 typ 6.0 80
(Note 9.) 585
MJE13007 5/30 5.0 3.0 0.7 5.0 80 474
MJE5852 15 min 2.0 2.0 0.5 4.0 80 590
8. |hFE| @ 1.0 MHz
9. Darlington
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Plastic TO220AB (continued)

PD
8.0 400/700 BUL147 14/34 1.0 2.5 0.18 2.0 14 typ 125 272
(Note 14.) (Note 14.)
450/1000 MJE18008 16/34 1.0 2.75 0.18 2.0 13 typ 125 538
(Note 14.) (Note 14.)
10 60 D44H8 D45H8 40 min 4.0 50 320
MJE3055T MJE2955T 20/70 4.0 75 560
2N6387 2N6667 1k/20k 5.0 20 65 121,
(Note 13.) (Note 13.) (Note 12.) 137
80 BDX33B BDX34B 750 min 3.0 3.0 70 197
(Note 13.) (Note 13.)
BD809 BD810 15 min 4.0 1.5 90 183
2N6388 2N6668 1k/20k 5.0 20 65 121,
(Note 13.) (Note 13.) (Note 12.) 137
D44H10 D45H10 20 min 4.0 0.5 typ 0.14 typ 5.0 50 typ 50 316
D44H11 D45H11 40 min 4.0 0.5 typ 0.14 typ 5.0 50 typ 50 316
100 BDX33C BDX34C 750 min 3.0 3.0 70 197
(Note 13.) (Note 13.)
12 400/700 MJE13009 6/30 8.0 3.0 0.7 8.0 4.0 100 483
15 60 2N6487 2N6490 20/150 5.0 0.6 typ 0.3 typ 5.0 5.0 75 127
80 2N6488 2N6491 20/150 5.0 0.6 typ 0.3 typ 5.0 5.0 75 127
D44VH10 D45VH10 20 min 4.0 0.5 0.09 8.0 50 typ 83 318
100 BDW42 BDW47 1k min 5.0 1.0 typ 1.5 typ 5.0 4.0 85 190
(Note 13.) (Note 13.)
12. |hFE| @ 1.0 MHz
13. Darlington
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Plastic TO218 Type

PD
10 60 TIP140 TIP145 500 min 10 2.5 typ 2.5 typ 5.0 4.0 125 720
(Note 17.) (Note 17.) (Note 16.)
TIP141 TIP146 500 min 10 2.5 typ 2.5 typ 5.0 4.0 125 720
(Note 17.) (Note 17.) (Note 16.)
100 BDV65B BDV64B 1k min 5.0 125 187
(Note 17.) (Note 17.)
TIP33C TIP34C 20/100 3.0 3.0 80 734
TIP142 TIP147 500 min 10 2.5 typ 2.5 typ 5.0 4.0 125 720
(Note 17.) (Note 17.) (Note 16.)
350 BU323Z 500/3400 5.0 6.0 150 209
(Note 17.)
15 60 TIP3055 TIP2955 5 min 10 2.5 80 727
150 MJH11018 MJH11017 400/15k 10 3.0 150 634
(Note 17.) (Note 17.)
200 MJH11020 MJH11019 400/15k 10 3.0 150 634
(Note 17.) (Note 17.)
250 MJH11022 MJH11021 400/15k 10 3.0 150 634
(Note 17.) (Note 17.)
16 160 MJE4343 MJE4353 15 min 8.0 1.2 typ 1.2 typ 8.0 1.0 125 574
20 100 MJH6284 MJH6287 750/18k 10 4.0 125 640
(Note 17.) (Note 17.)
25 60 TIP35A TIP36A 15/75 15 0.6 typ 0.3 typ 10 3.0 125 737
100 TIP35C TIP36C 15/75 15 0.6 typ 0.3 typ 10 3.0 125 737
16. |hFE| @ 1.0 MHz
17. Darlington
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Plastic (Isolated TO-220 Type)

PD
ICCont VCEO(sus) VCES ts tf fT (Case)
Amps Volts Volts hFE @ IC s s @ IC MHz Watts Page
Max Min Min NPN PNP Min/Max Amp Max Max Amp Min @ 25C
1.0 250 MJF47 30/150 0.3 2.0 typ 0.17 typ 0.3 10 28 622
3.0 100 MJF31C MJF32C 10 min 1.0 0.6 0.3 1.0 3.0 28 729
5.0 100 MJF122 MJF127 2000 min 3.0 1.5 typ 1.5 typ 3.0 4.0 28 601
(Note 20.) (Note 20.) (Note 19.)
450 1000 MJF18004 14/34 0.3 1.7 0.15 1.0 13 typ 35 522
(Note 21.) (Note 21.)
8.0 150 MJF15030 MJF15031 40 min 3.0 1.0 typ 0.15 typ 3.0 30 35 608
450 1000 MJF18008 16/34 1.0 2.75 0.18 2.0 13 typ 45 538
(Note 21.) (Note 21.)
10 60 MJF3055 MJF2955 20/100 4.0 2.0 40 614
80 MJF44H11 MJF45H11 40/100 4.0 0.5 typ 0.14 typ 5.0 40 35 618
100 MJF6388 MJF6668 3k/20k 3.0 1.5 typ 1.5 typ 20 40 627
(Note 20.) (Note 20.) (Note 19.)
Large Plastic TO-264

ICCont VCEO(sus) ts tf fT PD (Case)
Amps Volts hFE @ IC s s @ IC MHz Watts
Max Min NPN PNP Min/Max Amp Max Max Amp Min @ 25C Page
15 200 MJL3281A MJL1302A 60/175 5.0 30 typ 200 655
16 250 MJL21194 MJL21193 25/75 8.0 4.0 200 644
MJL21196 MJL21195 25/75 8.0 4.0 200 649
19. |hFE| @ 1.0 MHz
20. Darlington
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Plastic TO225AA Type (Formerly TO126 Type)
PD
Amps Volts hFE @ IC s s @ IC MHz Watts Page
Max Min NPN PNP Min/Max Amp Max Max Amp Min @ 25C
0.3 350 MJE3439 40/160 0.02 15 15 566
0.5 200 MJE344 30/300 0.05 15 20.8 568
250 2N5655 30/250 0.1 3.5 typ 0.24 typ 0.1 10 20 80
300 MJE340 MJE350 30/240 0.05 20.8 563,
570
350 2N5657 30/250 0.1 3.5 typ 0.24 typ 0.1 10 20 80
BD159 30/240 0.05 20 146
1.0 40 2N4921 2N4918 20/100 0.5 0.6 typ 0.3 typ 0.5 3.0 30 55,
50
60 2N4922 2N4919 20/100 0.5 0.6 typ 0.3 typ 0.5 3.0 30 55,
50
80 2N4923 2N4920 20/100 0.5 0.6 typ 0.3 typ 0.5 3.0 30 55,
50
1.5 45 BD135 BD136 40/250 0.15 12.5 142,
144
60 BD137 BD138 40/250 0.15 12.5 142,
144
80 BD139 BD140 40/250 0.15 12.5 142,
144
400 MJE13003 5/25 1.0 4.0 0.7 1.0 5.0 40
(Note 24.) 461
2.0
0 80 BD237 BD238 25 min 1.0 3.0 25 154
100 MJE270 MJE271 1.5k min 0.12 6.0 15
(Notes 23. & 24.) (Notes 23. & 24.) 558
3.0 60 MJE181 MJE171 50/250 0.1 0.6 typ 0.12 typ 0.1 50 12.5 501
80 BD179 BD180 40/250 0.15 25 148,
151
MJE182 MJE172 50/250 0.1 0.6 typ 0.12 typ 0.1 50 12.5 501
500 BUH51 8.0 min 1.0 50
(Note 24.) 254
4.0 40 MJE521 MJE371 40 min 1.0 40 579,
572
45 BD437 BD438 40 min 2.0 3.0 36 166,
169
60 BD439 BD440 25 min 2.0 3.0 36 166,
169
BD677 BD678 750 min 1.5 40 172,
(Note 23.) (Note 23.) 175
BD677A BD678A 750 min 1.5 40 172,
(Note 23.) (Note 23.) 175
BD787 BD788 20 min 2.0 50 15 178
2N5191 2N5194 25/100 1.5 0.4 typ 0.4 typ 1.5 2.0 40 62,
67
MJE800 MJE700 750 min 1.5 1.0 40
(Note 23.) (Note 23.) (Note 22.) 596
2N6038 2N6035 750/18k 2.0 1.7 typ 1.2 typ 2.0 25 40
(Note 23.) (Note 23.) 92
22. |hFE| @ 1.0 MHz
23. Darlington
24. Case 77, Style 3
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Plastic TO225AA Type (Formerly TO126 Type) (continued)

PD
4.0 80 2N5192 2N5195 25/100 1.5 0.4 typ 0.4 typ 1.5 2.0 40 62,
67
BD441 BD442 15 min 2.0 3.0 36 166,
169
BD679 BD680 750 min 1.5 40 172,
(Note 26.) (Note 26.) 175
BD679A BD680A 750 min 2.0 40 172,
(Note 26.) (Note 26.) 175
MJE802 MJE702 750 min 1.5 1.0 40
(Note 26.) (Note 26.) (Note 25.) 596
MJE803 MJE703 750 min 2.0 1.0 40
(Note 26.) (Note 26.) (Note 25.) 596
2N6039 2N6036 750/18k 2.0 1.7 typ 1.2 typ 2.0 25 40
(Note 26.) (Note 26.) 92
100 BD681 BD682 750 min 1.5 40 172,
(Note 26.) (Note 26.) 175
MJE243 MJE253 40/120 0.2 0.15 typ 0.07 typ 2.0 40 15 553
5.0 25 MJE200 MJE210 45/180 2 0.13 typ 0.035 typ 2.0 65 15 548
25. |hFE| @ 1.0 MHz
26. Darlington
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DPAK Surface Mount Power Packages

PD
ICCont VCEO(sus) ts tf fT (Case) Page
0.5 300 MJD340T4 MJD350T4 30/240 0.05 15 438
1.0 250 MJD47T4 30/150 0.3 2.0 0.2 0.3 10 15 452
400 MJD50T4 30/150 0.3 2.0 0.2 0.3 10 15 452
2.0 100 MJD112T4 MJD117T4 1000 min 2.0 1.7 1.3 2.0 25 20
(Note 28.) (Note 28.) (Note 27.) 395
450 MJD18002D2T4 6.0 min 2.0 1.0 typ 0.15 typ 1.0 13 typ 25 407
3.0 40 MJD31T4 MJD32T4 10 min 1.0 0.6 0.3 1.0 3.0 15 433
100 MJD31CT4 MJD32CT4 10 min 1.0 0.6 0.3 1.0 3.0 15 433
4.0 80 MJD6039T4 MJD6036T4 1k/2k 2.0 1.7 1.2 2.0 25 20
(Note 28.) (Note 28.) 456
100 MJD243T4 MJD253T4 40/180 0.2 0.16 0.04 1.0 40 12.5 423
5.0 25 MJD200T4 MJD210T4 45/180 2.0 0.15 0.04 2.0 65 12.5 418
6.0 100 MJD41CT4 MJD42CT4 15/75 3.0 0.4 0.15 3.0 3.0 20 442
8.0 80 MJD44H11T4 MJD45H11T4 40 min 4.0 0.5 0.14 5.0 50 typ 20 448
100 MJD122T4 MJD127T4 1k/2k 4.0 1.5 2.0 4.0 4 20
(Note 28.) (Note 28.) (Note 27.) 401
10 60 MJD3055T4 MJD2955T4 20/100 4.0 1.5 1.5 3.0 2.0 20 429
80 MJD44ET4 1k min 5.0 2.0 0.5 10 20
(Note 28.) 446
27. |hFE| @ 1.0 MHz
28. Darlington
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Metal TO204AA (Formerly TO3)

PD
4.0 250 MJ15020 MJ15021 30 min 1.0 20 150 344
10 140 2N3442 20/70 4.0 117 35
250 MJ15011 MJ15012 20/100 2.0 200 342
12 100 2N6052 750/18k 6.0 1.6 typ 1.5 typ 6.0 4.0 150
(Note 30.) (Note 29.) 102
15 60 2N3055 MJ2955 20/70 4.0 0.7 typ 0.3 typ 4.0 2.5 115 31
2N3055A 20/70 4.0 0.8 115 25
120 MJ15015 MJ15016 20/70 4.0 0.7 typ 0.3 typ 4.0 1.0 180 25
140 MJ15001 MJ15002 25/150 4.0 2.0 200 337
250 MJ11022 MJ11021 100 min 15 3.0 175
(Note 30.) (Note 30.) (Note 29.) 325
16 140 2N3773 2N6609 15/60 8.0 1.1 typ 1.5 typ 8.0 4.0 150 46
2N5631 2N6031 15/60 8.0 1.2 typ 1.2 typ 8.0 1.0 200 76
200 MJ15022 MJ15023 15/60 8.0 5.0 250 346,
349
250 MJ15024 MJ15025 15/60 8.0 5.0 250 346,
349
MJ21194 MJ21193 25/75 8.0 4.0 250 352
MJ21196 MJ21195 25/75 8.0 4.0 250 357
20 60 2N3772 15/60 10 2.0 150 38
80 2N6283 2N6286 750/18k 10 2.5 typ 2.5 typ 10 4.0 160
(Note 30.) (Note 30.) (Note 29.) 112
90 2N5038 20/100 12 1.5 0.5 12 60 140 60
100 2N6284 2N6287 750/18k 10 2.5 typ 2.5 typ 10 4.0 160
(Note 30.) (Note 30.) (Note 29.) 112
140 MJ15003 MJ15004 25/150 5.0 2.0 250 340
25 60 2N5885 2N5883 20/100 10 1.0 0.8 10 4.0 200 87
80 2N5886 2N5884 20/100 10 1.0 0.8 10 4.0 200 87
100 2N6338 30/120 10 1.0 0.25 10 40 200 118
150 2N6341 30/120 10 1.0 0.25 10 40 200 118
29. |hFE| @ 1.0 MHz
30. Darlington
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Metal TO204AA (Formerly TO3) (continued)

PD
30 40 2N3771 15/60 15 2.0 150 42
60 2N5302 15/60 15 2.0 1.0 10 2.0 200 72
MJ11012 1k min 20 4.0 200
(Note 33.) (Note 32.) 322
100 MJ802 MJ4502 25/100 7.5 2.0 200 364,
362
120 MJ11016 MJ11015 1k min 20 4.0 200
(Note 33.) (Note 33.) (Note 32.) 322
250 MJ11022 MJ11021 400/15k 10 3.0 200
(Note 33.) (Note 33.) (Note 32.) 325
40 200 BUV21 10 min 25 1.8 0.4 25 8.0 150
(Note 35.) 307
250 BUV22 10 min 20 1.1 0.35 20 8.0 250
(Note 35.) 310
50 80 2N5686 2N5684 15/60 25 0.5 0.3 typ 25 2.0 300
(Note 35.) (Note 35.) typ 83
120 MJ11032 MJ11033 400 min 50 300
(Note 33. & 35.) (Note 33. & 35.) 330
125 BUV20 10 min 50 1.2 0.25 50 8.0 250
(Note 35.) 304
BUV60 10 min 80 1.1 0.25 80 250
(Note 35.) 304
60 80 MJ14002 MJ14003 15/100 50 300
(Note 35.) (Note 35.) 333
32. |hFE| @ 1.0 MHz
33. Darlington
35. Case 197A03 (TO204AE)
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Isolated Mounting Hole Plastic TO247
Device Type Inductive Switching

PD
8.0 150 MJW21192 MJW21191 15 min 8.0 4.0 100 660
16 250 MJW21194* MJW21193* 20/60 8.0 4.0 200 665
16 250 MJW21196* MJW21195* 20/60 8.0 4.0 200 671
15 230 MJW3281A* MJW1302A* 60/175 5.0 30 200 677
D2PAK

PD
5.0 450/1000 MJB18004D2T4 6.0 2.0 2.4 0.175 2.5 13 typ 75 367
6.0 100 MJB42CT4 15/75 3.0 3.0 65 381
8.0 80 MJB44H11T4 MJB45H11T4 40/100 4.0 0.5 typ 0.14 5.0 40 50 388
SOT223

PD
ICCont VCEO(sus) ts tf fT (Case) Page
3.0 30 MMJT9410T1 MMJT9435T1 50 1.0 0.8 694,
699
0.5 30 MMJT350T1 30/240 0.05 0.8 692
SO8 (Dual Transistors)

PD
3.0 30 MMDJ3N03BJTR2 MMDJ3P03BJTR2 50 1.0 30 2.0 682,
687
*Available in Q2, 2001.
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Audio
GENERAL DESIGN CURVES FOR POWER AUDIO OUTPUT STAGES
V(BR)CEO Required on Output and Driver Transistor Output Transistor Peak Collector Current
versus versus
Output Power for 4, 8 and 18 Ohm Loads Output Power for 4, 8 and 16 Ohm Loads
500 50
PEAK OUTPUT CURRENT (AMPS)

16 OHMS 30
300
4 OHMS
8 OHMS
V (BR) CEO (VOLTS)
8 OHMS
100 4 OHMS 10
70
50 5.0 16 OHMS
30 3.0
10 1.0
10 30 50 100 300 500 1000 10 30 50 100 300 500 1000
OUTPUT POWER (WATTS) OUTPUT POWER (WATTS)
Another important parameter that must be considered before selecting the output transistors is the safeoperating area these
devices must withstand. For a complete discussion see Application Note AN485.
Recommended Power Transistors for Audio/Servo Loads
RMS PD fT
Power Watts hFE @ IC MHz ISB
Output NPN PNP Case @ 25C VCEO Min/Max Amps Typ Volts/Amps Page
To 25 W MJE15030 MJE15031 TO220 50 150 20 min 4.0 30 14/3.6 492
MJE15032 MJE15033 TO220 50 250 50 min 1.0 30 50/1.0 497
25 to 50 W 2N3055A MJ2955A TO204 120 120 20/70 4.0 3.0 60/2.0 25
MJ15001 MJ15002 TO204 200 140 25/150 4.0 3.0 40/5.0 337
50 to 100 W MJ15015 MJ15016 TO204 180 120 20/70 4.0 3.0 60/3.0 25
MJ15003 MJ15004 TO204 250 140 25/150 5.0 3.0 100/1.0 340
MJ15020 MJ15021 TO204 150 250 30 min 1.0 30 50/3.0 344

Over 100 W MJ15024 MJ15025 TO204 250 250 15/60 8.0 4.0 80/2.2 346,
349
MJL3281A MJL1302A 340G02 150 200 60/175 7.0 30 40/4.0 655
MJ21194 MJ21193 TO204 250 250 25/75 8.0 4.0 100/2.0 352
MJL21194 MJL21193 340G02 200 200 25/75 8.0 4.0 100/2.0 644
MJL21196 MJL21195 340G02 200 200 25/75 8.0 4.0 100/2.0 649
MJW21192 MJW21191 340K01 100 150 15 min 4.0 4.0 50/3.0 660
MJW21194 MJW21193 340K01 200 250 20/60 8.0 4.0 50/4.0 665
MJW21196 MJW21195 340K01 200 250 25/60 8.0 4.0 50/4.0 671
MJW3281A MJW1302A 340K01 200 200 60/175 5.0 30 50/4.0 677
The Power Transistors shown are provided for reference only and show device capability. The final choice of the Power
Transistors used is left to the circuit designer and depends upon the particular safeoperating area required and the mounting
and heat sinking configuration used.
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Bipolar Power Transistors for Electronic Lamp Ballasts
Plastic TO220AB
ICCont VCEO(sus) VCES IC hFE min Inductive Switching PD (Case)

Amps Volts Volts Operating @ IC Operating @ IC Operating Watts Page
Max Min Min Device Type Amps VCE = 1.0 V Tsi Min/Max (s) @ 25C
2.0 400 700 BUL44 0.8 10 2.6 / 3.8 50 279
450 1000 MJE18002 1.0 6.0 / 2.75 50 505
4.0 500 800 BUH50 2.0 8.0 typ / 2.5 50 246
5.0 400 700 BUL45 2.0 7.0 2.6 / 3.8 75 296
400 700 BUL45D2* 2.0 10 1.95 / 2.25 75 286
450 1000 MJE18004 2.0 6.0 / 2.5 75 522
450 1000 MJE18004D2* 2.0 6.0 2.1 / 2.4 75 512
6.0 400 700 BUL146 3.0 8.0 2.6 / 3.8 100 263
450 1000 MJE18006 3.0 6.0 / 3.2 100 531
8.0 400 700 BUL147 4.5 8.0 2.6 / 3.8 125 272
450 1000 MJE18008 4.5 6.0 / 3.2 125 538
10 400 700 BUH100 5.0 10 typ / 3.0 100 226
15 400 700 BUH150 10 8.0 typ / 2.75 150 236
BUHXXX Series are specified for Halogen applications.
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Bipolar Power Transistors for Electronic Lamp Ballasts
Case 221D-02 is UL RECOGNIZED for its isolation feature. Case 221D-02 has been evaluated to 3500 volts RMS. Actual
isolation rating depends on specific mounting position and maintaining required strike and creepage distances.
Plastic (Isolated TO-220 Type)

5.0 450 1000 MJF18004 2.0 6.0 / 2.5 35 522
6.0 400 700 BUL146F 3.0 8.0 2.6 / 3.8 40 263
8.0 450 1000 MJF18008 4.5 6.0 / 3.2 45 538
Surface Mount Power Packages DPAK

2.0 400 700 BUD44D21* 0.8 20 typ 2.05 / 2.35 25 216
Surface Mount Power Packages DPAK

VCEO(sus)
CEO( ) PD
ICCont /VCES ts tf fT (Case)
2.0 450/1000 MJD18002D2T4 6.0 1.0 1.2 0.150 1.0 A 13 typ 25 407
D2PAK

VCEO(sus)
CEO( ) PD
ICCont /VCES ts tf fT (Case)
5.0 450/1000 MJB18004D2T4 6.0 2.0 2.4 0.175 2.5 A 13 typ 75 367
Plastic TO225AA Type (Formerly TO126 Type)

1.5 400 700 MJE13003 1.0 6.0 typ / 3.0 40 461
(Note 36.)
3.0 500 800 BUH51 1.0 8.0 / 3.75 50 254
(Note 36.)
36. Case 77, Style 3

BUHXXX Series are specified for Halogen applications.
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22
CHAPTER 2
Data Sheets
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23
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24
ON Semiconductor
NPN
Complementary Silicon 2N3055A
High-Power Transistors MJ15015 *
. . . PowerBase complementary transistors designed for high PNP
power audio, stepping motor and other linear applications. These
devices can also be used in power switching circuits such as relay or
MJ15016 *
solenoid drivers, dctodc converters, inverters, or for inductive loads
requiring higher safe operating area than the 2N3055. *ON Semiconductor Preferred Device
CurrentGain BandwidthProduct @ IC = 1.0 Adc 15 AMPERE

fT = 0.8 MHz (Min) NPN COMPLEMENTARY
= 2.2 MHz (Min) PNP SILICON
POWER TRANSISTORS
Safe Operating Area Rated to 60 V and 120 V, Respectively

60, 120 VOLTS
115, 180 WATTS

*MAXIMUM RATINGS

Rating Symbol 2N3055A
MJ15015
MJ15016 Unit

CollectorEmitter Voltage

CollectorBase Voltage
VCEO
VCBO
60
100
120
200
Vdc
Vdc

CollectorEmitter Voltage Base

Reversed Biased
VCEV 100 200 Vdc
CASE 107

TO204AA
EmitterBase Voltage VEBO 7.0 Vdc (TO3)

Collector Current Continuous

IC 15 Adc

Base Current

IB 7.0 Adc

Total Device Dissipation @ TC = 25C PD 115 180 Watts
Derate above 25C 0.65 1.03 W/C

Operating and Storage Junction

Temperature Range
TJ, Tstg 65 to +200 C
THERMAL CHARACTERISTICS

Characteristic Symbol Max Max Unit

Thermal Resistance, Junction to Case RJC 1.52 0.98 C/W
*Indicates JEDEC Registered Data. (2N3055A)
Preferred devices are ON Semiconductor recommended choices for future use and best overall value.

May, 2001 Rev. 4 2N3055A/D
2N3055A MJ15015 MJ15016
200
PD(AV), AVERAGE POWER DISSIPATION (W)

150
MJ15015
MJ15016
100
50 2N3055A
0
0 25 50 75 100 125 150 175 200
TC, CASE TEMPERATURE (C)
Figure 1. Power Derating
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26
2N3055A MJ15015 MJ15016
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS (1)

*CollectorEmitter Sustaining Voltage 2N3055A VCEO(sus) 60 Vdc
(IC = 200 mAdc, IB = 0) MJ15015, MJ15016 120

Collector Cutoff Current

(VCE = 30 Vdc, VBE(off) = 0 Vdc) 2N3055A
ICEO
0.7
mAdc

(VCE = 60 Vdc, VBE(off) = 0 Vdc) MJ15015, MJ15016 0.1

*Collector Cutoff Current 2N3055A ICEV 5.0 mAdc
(VCEV = Rated Value, VBE(off) = 1.5 Vdc) MJ15015, MJ15016 1.0


(VCEV = Rated Value, VBE(off) = 1.5 Vdc, 2N3055A
ICEV
30
mAdc

TC = 150C) MJ15015, MJ15016 6.0

Emitter Cutoff Current 2N3055A IEBO 5.0 mAdc
(VEB = 7.0 Vdc, IC = 0) MJ15015, MJ15016 0.2
*SECOND BREAKDOWN

Second Breakdown Collector Current with Base Forward Biased IS/b Adc
(t = 0.5 s nonrepetitive) 2N3055A 1.95

(VCE = 60 Vdc)
*ON CHARACTERISTICS (1)

MJ15015, MJ15016 3.0
DC Current Gain

(IC = 4.0 Adc, VCE = 2.0 Vdc)
hFE
10 70

(IC = 4.0 Adc, VCE = 4.0 Vdc) 20 70
(IC = 10 Adc, VCE = 4.0 Vdc) 5.0

CollectorEmitter Saturation Voltage

(IC = 4.0 Adc, IB = 400 mAdc)
VCE(sat)
1.1
Vdc

(IC = 10 Adc, IB = 3.3 Adc) 3.0
(IC = 15 Adc, IB = 7.0 Adc) 5.0

BaseEmitter On Voltage

(IC = 4.0 Adc, VCE = 4.0 Vdc)
VBE(on) 0.7 1.8 Vdc

*DYNAMIC CHARACTERISTICS

CurrentGain Bandwidth Product 2N3055A, MJ15015 fT 0.8 6.0 MHz

(IC = 1.0 Adc, VCE = 4.0 Vdc, f = 1.0 MHz) MJ15016 2.2 18
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)
Cob 60 600 pF
*SWITCHING CHARACTERISTICS (2N3055A only)
RESISTIVE LOAD
Delay Time

Rise Time

(VCC = 30 Vdc, IC = 4.0 Adc,
td
tr

0.5
4.0
s

IB1 = IB2 = 0.4
0 4 Adc,
Adc
Storage Time tp = 25 s
Duty y Cycle
y 2% ts 3.0 s
Fall Time

(1) Pulse Test: Pulse Width = 300 s, Duty Cycle 2%.
tf 6.0 s
*Indicates JEDEC Registered Data. (2N3055A)
http://onsemi.com
27
2N3055A MJ15015 MJ15016
200 2.8
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)

TJ = 25C
100 TJ = 150C 2.4
70
hFE , DC CURRENT GAIN
50 2
-55C
30 1.6 IC = 1 A 4A 8A
20
VCE = 4.0 V 25C 1.2
10
7 0.8
5
0.4
3
2 0
0.2 0.3 0.5 0.7 1 2 3 5 7 10 15 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5
IC, COLLECTOR CURRENT (AMP) IB, BASE CURRENT (AMP)
Figure 2. DC Current Gain Figure 3. Collector Saturation Region
T CURRENT-GAIN BANDWIDTH PRODUCT (MHz)

3.5 10
TC = 25C
3
5.0 MJ15016
2.5
V, VOLTAGE (VOLTS)
2
2.0
1.5 2N3055A
VBE(sat) @ IC/IB = 10 MJ15015
1
1.0
VBE(on) @ VCE = 4 V
0.5
VCE(sat) @ IC/IB = 10
0
0.2 0.3 0.5 0.7 1 2 3 5 7 10 20 0.1 0.2 0.3 0.5 1.0 2.0
f,
IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMPS)

Figure 4. On Voltages Figure 5. CurrentGain Bandwidth Product
10
7 VCC = 30 V
5 IC/IB = 10
VCC TJ = 25C
+30 V 3
2
t, TIME (s)
tr

7.5
25 s 1
+13 V SCOPE 0.7
30
0 0.5
1N6073 0.3
-11 V
0.2
tr, tf 10 ns td
-5 V
DUTY CYCLE = 1.0% 0.1
0.2 0.3 0.5 0.7 1 2 3 5 7 10 15
IC, COLLECTOR CURRENT (AMP)
Figure 6. Switching Times Test Circuit Figure 7. TurnOn Time

(Circuit shown is for NPN)
http://onsemi.com
28
2N3055A MJ15015 MJ15016
10 400
7 TJ = 25C
5 2N3055A
3 200 Cib MJ15015
C, CAPACITANCE (pF)
2 ts MJ15016
t, TIME (s)

tf
0.1 100
0.7
0.5 VCC = 30 50 Cob
IC/IB = 10
0.3 IB1 = IB2
0.2 TJ = 25C 30
0.1 20
0.2 0.3 0.5 0.7 1 2 3 5 7 10 15 1.0 2.0 5.0 10 20 50 100 200 500 1000
IC, COLLECTOR CURRENT (AMPS) VR, REVERSE VOLTAGE (VOLTS)
Figure 8. TurnOff Times Figure 9. Capacitances
COLLECTOR CUTOFF REGION
NPN PNP
10,000 1000
VCE = 30 V VCE = 30 V
1000 100
IC, COLLECTOR CURRENT (A)

100 10 TJ = 150C
TJ = 150C
10 1.0
100C 100C
1.0 0.1 IC = ICES
IC = ICES
REVERSE FORWARD
REVERSE FORWARD
0.1 0.01 25C
25C
0.01 0.001
+0.2 +0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5
VBE, BASE-EMITTER VOLTAGE (VOLTS) VBE, BASE-EMITTER VOLTAGE (VOLTS)
Figure 10. 2N3055A, MJ15015 Figure 11. MJ15016
20 20
30 s 0.1ms
IC, COLLECTOR CURRENT (AMPS)
10
10
100 s 5.0
1 ms 1.0ms
5
2.0
100 ms 1.0 100ms

BONDING WIRE LIMIT BONDING WIRE LIMIT
2 THERMAL LIMIT @ TC = 25C dc THERMAL LIMIT @ TC = 25C
0.5
(SINGLE PULSE) (SINGLE PULSE)
SECOND BREAKDOWN LIMIT SECOND BREAKDOWN LIMIT dc
1 0.2
10 20 60 100 15 20 30 60 100 120
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 12. Forward Bias Safe Operating Area Figure 13. Forward Bias Safe Operating Area
2N3055A MJ15015, MJ15016
http://onsemi.com
29
2N3055A MJ15015 MJ15016
There are two limitations on the power handling ability of

a transistor: average junction temperature and second
breakdown. Safe Operating area curves indicate IC VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figures 12 and 13 is based on TC = 25C;
TJ(pk) is variable depending on power level. Second
breakdown pulse limits are valid for duty cycles to 10% but
must be derated for temperature according to Figure 1.
http://onsemi.com
30
ON Semiconductor
NPN
Complementary Silicon Power 2N3055 *
PNP
Transistors MJ2955 *
. . . designed for generalpurpose switching and amplifier
applications. *ON Semiconductor Preferred Device
DC Current Gain hFE = 2070 @ IC = 4 Adc 15 AMPERE

CollectorEmitter Saturation Voltage POWER TRANSISTORS
VCE(sat) = 1.1 Vdc (Max) @ IC = 4 Adc COMPLEMENTARY
Excellent Safe Operating Area SILICON
60 VOLTS
115 WATTS

MAXIMUM RATINGS

Rating Symbol Value Unit


VCEO
VCER
60
70
Vdc
Vdc

CollectorBase Voltage VCB 100 Vdc

EmitterBase Voltage VEB 7 Vdc CASE 107
TO204AA

Collector Current Continuous IC 15 Adc (TO3)

Base Current IB 7 Adc

Total Power Dissipation @ TC = 25C

Derate above 25C
PD 115
0.657
Watts
W/C

Operating and Storage Junction Temperature TJ, Tstg 65 to +200 C
Range


Characteristic Symbol Max Unit

Thermal Resistance, Junction to Case
160
RJC 1.52 C/W
140
PD, POWER DISSIPATION (WATTS)
120
100
80
60
40
20
0
0 25 50 75 100 125 150 175 200

April, 2001 Rev. 2 2N3055/D
2N3055 MJ2955


*OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage (1) VCEO(sus) 60 Vdc

(IC = 200 mAdc, IB = 0)

CollectorEmitter Sustaining Voltage (1) VCER(sus) 70 Vdc

(IC = 200 mAdc, RBE = 100 Ohms)

Collector Cutoff Current ICEO 0.7 mAdc

(VCE = 30 Vdc, IB = 0)

Collector Cutoff Current ICEX mAdc
(VCE = 100 Vdc, VBE(off) = 1.5 Vdc) 1.0

(VCE = 100 Vdc, VBE(off) = 1.5 Vdc, TC = 150C) 5.0

Emitter Cutoff Current

(VBE = 7.0 Vdc, IC = 0)

IEBO 5.0 mAdc
*ON CHARACTERISTICS (1)

DC Current Gain hFE

(IC = 4.0 Adc, VCE = 4.0 Vdc) 20 70
(IC = 10 Adc, VCE = 4.0 Vdc) 5.0

(IC = 4.0 Adc, IB = 400 mAdc)
VCE(sat)
1.1
Vdc

(IC = 10 Adc, IB = 3.3 Adc) 3.0


(IC = 4.0 Adc, VCE = 4.0 Vdc)
VBE(on) 1.5 Vdc
SECOND BREAKDOWN

Second Breakdown Collector Current with Base Forward Biased Is/b 2.87 Adc
(VCE = 40 Vdc, t = 1.0 s, Nonrepetitive)
DYNAMIC CHARACTERISTICS

Current Gain Bandwidth Product fT 2.5 MHz
(IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 MHz)

*SmallSignal Current Gain

(IC = 1.0 Adc, VCE = 4.0 Vdc, f = 1.0 kHz)
hfe 15 120

*SmallSignal Current Gain Cutoff Frequency

(VCE = 4.0 Vdc, IC = 1.0 Adc, f = 1.0 kHz)
*Indicates Within JEDEC Registration. (2N3055)
fhfe 10 kHz
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
http://onsemi.com
32
2N3055 MJ2955
2N3055, MJ2955 There are two limitations on the power handling ability of
20 a transistor: average junction temperature and second
50 s
breakdown. Safe operating area curves indicate IC VCE
10 dc
1 ms limits of the transistor that must be observed for reliable

6 operation; i.e., the transistor must not be subjected to greater
4 dissipation than the curves indicate.
500 s The data of Figure 2 is based on TC = 25C; TJ(pk) is
2 250 s
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
1
derated for temperature according to Figure 1.
0.6 BONDING WIRE LIMIT
0.4 THERMALLY LIMITED @ TC = 25C (SINGLE PULSE)
SECOND BREAKDOWN LIMIT
0.2
6 10 20 40 60
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 2. Active Region Safe Operating Area
http://onsemi.com
33
2N3055 MJ2955
NPN PNP
2N3055 MJ2955
500 200
300 VCE = 4.0 V VCE = 4.0 V
TJ = 150C TJ = 150C
200 25C
100

25C
100 70 -55C
70 -55C
50
50
30 30
20
20
10
7.0
5.0 10
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)
Figure 3. DC Current Gain
2.0 2.0
TJ = 25C VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) TJ = 25C

1.6 1.6
IC = 1.0 A 4.0 A 8.0 A IC = 1.0 A 4.0 A 8.0 A
1.2 1.2
0.8 0.8
0.4 0.4
0 0
5.0 10 20 50 100 200 500 1000 2000 5000 5.0 10 20 50 100 200 500 1000 2000 5000
IB, BASE CURRENT (mA) IB, BASE CURRENT (mA)
Figure 4. Collector Saturation Region
1.4 2.0
TJ = 25C TJ = 25C
1.2
1.6
1.0
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
0.8 1.2 VBE(sat) @ IC/IB = 10

VBE(sat) @ IC/IB = 10
VBE @ VCE = 4.0 V
0.6 VBE @ VCE = 4.0 V 0.8
0.4
0.4
0.2 VCE(sat) @ IC/IB = 10
0 0
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10
IC, COLLECTOR CURRENT (AMPERES) IC, COLLECTOR CURRENT (AMP)
Figure 5. On Voltages
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34
ON Semiconductor
High-Power Industrial 2N3442

Transistors
NPN silicon power transistor designed for applications in industrial 10 AMPERE
and commercial equipment including high fidelity audio amplifiers, POWER TRANSISTOR
series and shunt regulators and power switches. NPN SILICON
Collector Emitter Sustaining Voltage 140 VOLTS
117 WATTS
VCEO(sus) = 140 Vdc (Min)
Excellent Second Breakdown Capability
CASE 107
TO204AA
(TO3)
*MAXIMUM RATINGS




VCEO
VCB
140
160
Vdc
Vdc

EmitterBase Voltage

VEB
IC
7.0
10
Vdc
Adc

Collector Current Peak

Base Current Continuous IB
15**
7.0 Adc

Peak

Total Power Dissipation @ TC = 25C PD 117 Watts

Derate above 25C 0.67 W/C

Operating and Storage Junction TJ, Tstg 65 to +200 C
Temperature Range


* Indicates JEDEC Registered Data.

** This data guaranteed in addition to JEDEC registered data.
RJC 1.5 C/W

March, 2001 Rev. 10 2N3442/D
2N3442

OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage VCEO(sus) 140 Vdc
(IC = 200 mAdc, IB = 0)


(VCE = 140 Vdc, IB = 0)

ICEO 200 mAdc


(VCE = 140 Vdc, VBE(off) = 1.5 Vdc)
(VCE = 140 Vdc, VBE(off) = 1.5 Vdc, TC = 150C)
ICEX

5.0
30
mAdc

(VBE = 7.0 Vdc, IC = 0)

IEBO 5.0 mAdc
DC Current Gain

ON CHARACTERISTICS (1)

hFE

(IC = 3.0 Adc, VCE = 4.0 Vdc)

(IC = 10 Adc, VCE = 4.0 Vdc)

20
7.5
70

CollectorEmitter Saturation Voltage VCE(sat) 5.0 Vdc
(IC = 10 Adc, IB = 2.0 Adc)

(IC = 10 Adc, VCE = 4.0 Vdc)
VBE(on) 5.7 Vdc


CurrentGain Bandwidth Product (2) fT 80 kHz

SmallSignal Current Gain
(IC = 2.0 Adc, VCE = 4.0 Vdc, ftest = 40 kHz)

hfe 12 72

*Indicates JEDEC Registered Data.
NOTES:
1. Pulse Test: Pulse Width = 300 s, Duty Cycle 2.0%.
2. fT = |hfe| ftest
PD /PD(MAX), POWER DISSIPATION (NORMALIZED)
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150 175 200
http://onsemi.com
36
2N3442
ACTIVE REGION SAFE OPERATING AREA INFORMATION

20
10 s
10 There are two limitations on the powerhandling ability
7.0 dc of a transistor: average junction temperature and second

5.0 breakdown. Safe operating area curves indicate IC VCE
3.0 30 s limits of the transistor that must be observed for reliable
50 s
operation, i.e., the transistor must not be subjected to greater
2.0
100 s
TJ = 200C
1.0 1.0 ms The data of Figure 2 is based on TJ(pk) = 200C; TC is vari-
0.7 CURRENT LIMIT able depending on conditions. At high case temperatures,
100 ms
0.5 THERMAL LIMIT @ TC = 25C thermal limitations will reduce the power that can be han-
SINGLE PULSE dled to values less than the limitations imposed by second
0.3 SECOND BREAKDOWN LIMIT breakdown.
0.2
2.0 3.0 5.0 7.0 10 20 30 50 70 100 200
Figure 2. 2N3442
400 1.4
TJ = 150C VCE = 4.0 V VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
200 1.2 IC = 1.0 A 2.0 A 4.0 A 8.0 A
hFE, DC CURRENT GAIN
100 1.0
-55C
60 25C
0.8
40
0.6
20
0.4
10
0.2
6.0 TJ = 25C
4.0 0
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 2.0 5.0 10 20 50 100 200 500 1.0k 2.0k
IC, COLLECTOR CURRENT (AMP) IB, BASE CURRENT (mA)
Figure 3. DC Current Gain Figure 4. CollectorSaturation Region
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37
ON Semiconductor
High Power NPN Silicon Power 2N3771*

Transistors 2N3772
. . . designed for linear amplifiers, series pass regulators, and *ON Semiconductor Preferred Device
inductive switching applications.
Forward Biased Second Breakdown Current Capability 20 and 30 AMPERE
POWER TRANSISTORS
IS/b = 3.75 Adc @ VCE = 40 Vdc 2N3771

NPN SILICON
= 2.5 Adc @ VCE = 60 Vdc 2N3772
40 and 60 VOLTS
150 WATTS

*MAXIMUM RATINGS

Rating Symbol 2N3771 2N3772 Unit

CollectorEmitter Voltage VCEO 40 60 Vdc

CollectorEmitter Voltage VCEX 50 80 Vdc


EmitterBase Voltage
VCB
VEB
50
5.0
100
7.0
Vdc
Vdc CASE 107

TO204AA
Collector Current Continuous IC 30 20 Adc

(TO3)
Peak 30 30

Base Current Continuous

Peak
IB 7.5
15
5.0
15
Adc

Total Device Dissipation @ TC = 25C PD 150 Watts

Temperature Range

Characteristics Symbol 2N3771, 2N3772 Unit

Thermal Resistance, Junction to Case JC 1.17 C/W
200
175
150
125
100
75
50
25
0
0 25 50 75 100 125 150 175 200

March, 2001 Rev. 9 2N3771/D
2N3771 2N3772

OFF CHARACTERISTICS

*CollectorEmitter Sustaining Voltage (1) 2N3771 VCEO(sus) 40 Vdc

(IC = 0.2 Adc, IB = 0) 2N3772 60

CollectorEmitter Sustaining Voltage 2N3771 VCEX(sus) 50 Vdc
(IC = 0.2 Adc, VEB(off) = 1.5 Vdc, RBE = 100 Ohms) 2N3772 80

CollectorEmitter Sustaining Voltage

(IC = 0.2 Adc, RBE = 100 Ohms)
2N3771
2N3772
VCER(sus) 45
70

Vdc

*Collector Cutoff Current ICEO mAdc

(VCE = 30 Vdc, IB = 0) 2N3771 10
(VCE = 50 Vdc, IB = 0) 2N3772 10

(VCE = 25 Vdc, IB = 0)

*Collector Cutoff Current ICEV mAdc

(VCE = 50 Vdc, VEB(off) = 1.5 Vdc) 2N3771 2.0

(VCE = 30 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 2N3771

10
2N3772 10

(VCE = 45 Vdc, VEB(off) = 1.5 Vdc, TC = 150C)

*Collector Cutoff Current ICBO mAdc
(VCB = 50 Vdc, IE = 0) 2N3771

2.0
(VCB = 100 Vdc, IE = 0) 2N3772 5.0

*Emitter Cutoff Current

(VBE = 5.0 Vdc, IC = 0)

2N3771
IEBO
5.0
mAdc
(VBE = 7.0 Vdc, IC = 0) 2N3772 5.0

*ON CHARACTERISTICS

DC Current Gain (1) hFE
(IC = 15 Adc, VCE = 4.0 Vdc) 2N3771 15 60

(IC = 10 Adc, VCE = 4.0 Vdc) 2N3772 15 60

(IC = 8.0 Adc, VCE = 4.0 Vdc)
(IC = 30 Adc, VCE = 4.0 Vdc) 2N3771 5.0

(IC = 20 Adc, VCE = 4.0 Vdc) 2N3772 5.0


(IC = 15 Adc, IB = 1.5 Adc)
(IC = 10 Adc, IB = 1.0 Adc)

2N3771
2N3772
VCE(sat)
2.0
Vdc

1.4
(IC = 30 Adc, IB = 6.0 Adc) 2N3771 4.0

(IC = 20 Adc, IB = 4.0 Adc) 2N3772 4.0

BaseEmitter On Voltage VBE(on) Vdc
(IC = 15 Adc, VCE = 4.0 Vdc) 2N3771

2.7
(IC = 10 Adc, VCE = 4.0 Vdc) 2N3772 2.2

(IC = 8.0 Adc, VCE = 4.0 Vdc)

CurrentGain Bandwidth Product fT 0.2 MHz


hfe 40
SECOND BREAKDOWN

Second Breakdown Energy with Base Forward Biased, t = 1.0 s (nonrepetitive) IS/b Adc

(VCE = 40 Vdc) 2N3771 3.75
(VCE = 60 Vdc) 2N3772 2.5
(1) Pulse Test: 300 s, Rep. Rate 60 cps.
http://onsemi.com
39
2N3771 2N3772
1.0
0.7
r(t), EFFECTIVE TRANSIENT THERMAL
D = 0.5
0.5
RESISTANCE (NORMALIZED)
0.3 0.2
0.2
0.1
0.1 0.05 JC(t) = r(t) JC P(pk)
0.07
JC = 0.875C/W MAX
0.05 D CURVES APPLY FOR POWER
0.02
PULSE TRAIN SHOWN t1
0.03 0.01 READ TIME AT t1 t2
0.02 SINGLE PULSE TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
0.01
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000
t, TIME (ms)
Figure 2. Thermal Response 2N3771, 2N3772
40 There are two limitations on the power handling ability of

40 s
2N3771 breakdown. Safe operating area curves indicate IC VCE

20
2N3772, (dc) 100 s limits of the transistor that must be observed for reliable
dc operation: i.e., the transistor must not be subjected to greater
10 200 s dissipation than the curves indicate.
TC = 25C
Figure 3 is based on JEDEC registered Data. Second
7.0 BONDING WIRE LIMITED 1.0 ms
THERMALLY LIMITED
breakdown pulse limits are valid for duty cycles to 10%
5.0 (SINGLE PULSE) 100 ms provided TJ(pk) < 200C. TJ(pk) may be calculated from the
SECOND BREAKDOWN LIMITED data of Figure 2. Using data of Figure 2 and the pulse power
CURVES APPLY BELOW RATED VCEO
3.0 PULSE CURVES APPLY 500 ms
limits of Figure 3, TJ(pk) will be found to be less than TJ(max)
2N3771
FOR ALL DEVICES for pulse widths of 1 ms and less. When using ON
2N3772
2.0 Semiconductor transistors, it is permissible to increase the
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
pulse power limits until limited by T J(max).
Figure 3. ActiveRegion Safe Operating Area

2N3771, 2N3772
VCC
+30 V 10
5.0 VCC = 30
IC/IB = 10 VBE(off) = 5.0 V
25 s RC 2.0 TJ = 25C
+11 V SCOPE
RB 1.0
tr
t, TIME (s)
0.5

0
51 D1
0.2
-9.0 V
0.1
tr, tf 10 ns -4 V
DUTY CYCLE = 1.0% 0.05 td
RB AND RC ARE VARIED TO OBTAIN DESIRED CURRENT LEVELS 0.02
D1 MUST BE FAST RECOVERY TYPE, e.g.: 0.01
1N5825 USED ABOVE IB 100 mA 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
MSD6100 USED BELOW IB 100 mA IC, COLLECTOR CURRENT (AMP)
Figure 4. Switching Time Test Circuit Figure 5. TurnOn Time
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40
2N3771 2N3772
100 2000
50 VCC = 30 V TJ = 25C
IC/IB = 10
20 IB1 = IB2
Cib
C, CAPACITANCE (pF)
10 TJ = 25C 1000
t, TIME (s)
5.0 Cob

700
ts
2.0
500
1.0
tf
0.5
300
0.2
0.1 200
0.3 0.5 1.0 2.0 3.0 5.0 7.0 10 20 30 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
IC, COLLECTOR CURRENT (AMP) VR, REVERSE VOLTAGE (VOLTS)
Figure 6. TurnOff Time Figure 7. Capacitance

500 2.0

TJ = 25C
300 TJ = 150C VCE = 4.0 V
200 1.6
25C IC = 2.0 A 5.0 A 10 A 20 A
100
70 1.2
50 -55C
30 0.8
20
0.4
10
7.0
5.0 0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
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41
ON Semiconductor
High Power NPN Silicon Power 2N3771*

Transistors 2N3772
. . . designed for linear amplifiers, series pass regulators, and *ON Semiconductor Preferred Device
inductive switching applications.
Forward Biased Second Breakdown Current Capability 20 and 30 AMPERE
POWER TRANSISTORS
IS/b = 3.75 Adc @ VCE = 40 Vdc 2N3771

NPN SILICON
= 2.5 Adc @ VCE = 60 Vdc 2N3772
40 and 60 VOLTS
150 WATTS

*MAXIMUM RATINGS



CollectorEmitter Voltage VCEX 50 80 Vdc


EmitterBase Voltage
VCB
VEB
50
5.0
100
7.0
Vdc
Vdc CASE 107

TO204AA
Collector Current Continuous IC 30 20 Adc

(TO3)
Peak 30 30


Peak
IB 7.5
15
5.0
15
Adc


Temperature Range

Characteristics Symbol 2N3771, 2N3772 Unit

200
175
150
125
100
75
50
25
0
0 25 50 75 100 125 150 175 200

March, 2001 Rev. 9 2N3771/D
2N3771 2N3772

OFF CHARACTERISTICS

*CollectorEmitter Sustaining Voltage (1) 2N3771 VCEO(sus) 40 Vdc

(IC = 0.2 Adc, IB = 0) 2N3772 60

CollectorEmitter Sustaining Voltage 2N3771 VCEX(sus) 50 Vdc
(IC = 0.2 Adc, VEB(off) = 1.5 Vdc, RBE = 100 Ohms) 2N3772 80


2N3771
2N3772
VCER(sus) 45
70

Vdc

*Collector Cutoff Current ICEO mAdc

(VCE = 30 Vdc, IB = 0) 2N3771 10
(VCE = 50 Vdc, IB = 0) 2N3772 10

(VCE = 25 Vdc, IB = 0)

*Collector Cutoff Current ICEV mAdc


(VCE = 30 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 2N3771

10
2N3772 10


*Collector Cutoff Current ICBO mAdc
(VCB = 50 Vdc, IE = 0) 2N3771

2.0
(VCB = 100 Vdc, IE = 0) 2N3772 5.0

*Emitter Cutoff Current

(VBE = 5.0 Vdc, IC = 0)

2N3771
IEBO
5.0
mAdc
(VBE = 7.0 Vdc, IC = 0) 2N3772 5.0

*ON CHARACTERISTICS

(IC = 15 Adc, VCE = 4.0 Vdc) 2N3771 15 60

(IC = 10 Adc, VCE = 4.0 Vdc) 2N3772 15 60

(IC = 8.0 Adc, VCE = 4.0 Vdc)
(IC = 30 Adc, VCE = 4.0 Vdc) 2N3771 5.0

(IC = 20 Adc, VCE = 4.0 Vdc) 2N3772 5.0


(IC = 15 Adc, IB = 1.5 Adc)
(IC = 10 Adc, IB = 1.0 Adc)

2N3771
2N3772
VCE(sat)
2.0
Vdc

1.4
(IC = 30 Adc, IB = 6.0 Adc) 2N3771 4.0

(IC = 20 Adc, IB = 4.0 Adc) 2N3772 4.0

(IC = 15 Adc, VCE = 4.0 Vdc) 2N3771

2.7
(IC = 10 Adc, VCE = 4.0 Vdc) 2N3772 2.2

(IC = 8.0 Adc, VCE = 4.0 Vdc)



hfe 40
SECOND BREAKDOWN

Second Breakdown Energy with Base Forward Biased, t = 1.0 s (nonrepetitive) IS/b Adc

(VCE = 40 Vdc) 2N3771 3.75
(VCE = 60 Vdc) 2N3772 2.5
(1) Pulse Test: 300 s, Rep. Rate 60 cps.
http://onsemi.com
43
2N3771 2N3772
1.0
0.7
D = 0.5
0.5
0.3 0.2
0.2
0.1
0.1 0.05 JC(t) = r(t) JC P(pk)
0.07
JC = 0.875C/W MAX
0.02
0.02 SINGLE PULSE TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
0.01
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000
t, TIME (ms)
Figure 2. Thermal Response 2N3771, 2N3772

40 s
2N3771 breakdown. Safe operating area curves indicate IC VCE

20
2N3772, (dc) 100 s limits of the transistor that must be observed for reliable
dc operation: i.e., the transistor must not be subjected to greater
10 200 s dissipation than the curves indicate.
TC = 25C
Figure 3 is based on JEDEC registered Data. Second
7.0 BONDING WIRE LIMITED 1.0 ms
THERMALLY LIMITED
breakdown pulse limits are valid for duty cycles to 10%
5.0 (SINGLE PULSE) 100 ms provided TJ(pk) < 200C. TJ(pk) may be calculated from the
SECOND BREAKDOWN LIMITED data of Figure 2. Using data of Figure 2 and the pulse power
3.0 PULSE CURVES APPLY 500 ms
limits of Figure 3, TJ(pk) will be found to be less than TJ(max)
2N3771
FOR ALL DEVICES for pulse widths of 1 ms and less. When using ON
2N3772
2.0 Semiconductor transistors, it is permissible to increase the
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
pulse power limits until limited by T J(max).

2N3771, 2N3772
VCC
+30 V 10
5.0 VCC = 30
IC/IB = 10 VBE(off) = 5.0 V
25 s RC 2.0 TJ = 25C
+11 V SCOPE
RB 1.0
tr
t, TIME (s)
0.5

0
51 D1
0.2
-9.0 V
0.1
tr, tf 10 ns -4 V
DUTY CYCLE = 1.0% 0.05 td
RB AND RC ARE VARIED TO OBTAIN DESIRED CURRENT LEVELS 0.02
D1 MUST BE FAST RECOVERY TYPE, e.g.: 0.01
1N5825 USED ABOVE IB 100 mA 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
http://onsemi.com
44
2N3771 2N3772
100 2000
50 VCC = 30 V TJ = 25C
IC/IB = 10
20 IB1 = IB2
Cib
C, CAPACITANCE (pF)
10 TJ = 25C 1000
t, TIME (s)
5.0 Cob

700
ts
2.0
500
1.0
tf
0.5
300
0.2
0.1 200
0.3 0.5 1.0 2.0 3.0 5.0 7.0 10 20 30 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100

500 2.0

TJ = 25C
300 TJ = 150C VCE = 4.0 V
200 1.6
25C IC = 2.0 A 5.0 A 10 A 20 A
100
70 1.2
50 -55C
30 0.8
20
0.4
10
7.0
5.0 0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
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45
ON Semiconductor
NPN
PNP
Transistors
2N6609
The 2N3773 and 2N6609 are PowerBase power transistors
designed for high power audio, disk head positioners and other linear *ON Semiconductor Preferred Device
applications. These devices can also be used in power switching
circuits such as relay or solenoid drivers, dc to dc converters or 16 AMPERE
inverters. COMPLEMENTARY
POWER TRANSISTORS
High Safe Operating Area (100% Tested) 150 W @ 100 V 140 VOLTS
Completely Characterized for Linear Operation 150 WATTS
High DC Current Gain and Low Saturation Voltage
hFE = 15 (Min) @ 8 A, 4 V
VCE(sat) = 1.4 V (Max) @ IC = 8 A, IB = 0.8 A
For Low Distortion Complementary Designs
CASE 107
TO204AA
(TO3)
*MAXIMUM RATINGS


Collector Emitter Voltage

VCEO 140 Vdc

CollectorEmitter Voltage VCEX 160 Vdc

CollectorBase Voltage VCBO 160 Vdc

EmitterBase Voltage VEBO 7 Vdc

Collector Current Continuous IC 16 Adc

Peak (1) 30

Base Current Continuous IB 4 Adc
Peak (1) 15


Derate above 25C

PD 150
0.855
Watts
W/C


Temperature Range




RJC 1.17 C/W
(1) Pulse Test: Pulse Width = 5 ms, Duty Cycle 10%.

March, 2001 Rev. 9 2N3773/D
2N3773 2N6609



*CollectorEmitter Breakdown Voltage VCEO(sus) 140 Vdc
(IC = 0.2 Adc, IB = 0)

*CollectorEmitter Sustaining Voltage

(IC = 0.1 Adc, VBE(off) = 1.5 Vdc, RBE = 100 Ohms)
VCEX(sus) 160 Vdc


VCER(sus) 150 Vdc

*Collector Cutoff Current ICEO 10 mAdc

(VCE = 120 Vdc, IB = 0)

*Collector Cutoff Current ICEX mAdc
(VCE = 140 Vdc, VBE(off) = 1.5 Vdc) 2

(VCE = 140 Vdc, VBE(off) = 1.5 Vdc, TC = 150C) 10


(VCB = 140 Vdc, IE = 0)

ICBO 2 mAdc

*Emitter Cutoff Current IEBO 5 mAdc
(VBE = 7 Vdc, IC = 0)

DC Current Gain hFE
*(IC = 8 Adc, VCE = 4 Vdc)

15 60
(IC = 16 Adc, VCE = 4 Vdc) 5


*(IC = 8 Adc, IB = 800 mAdc)
VCE(sat)
1.4
Vdc

(IC = 16 Adc, IB = 3.2 Adc) 4

*BaseEmitter On Voltage VBE(on) 2.2 Vdc
(IC = 8 Adc, VCE = 4 Vdc)


Magnitude of CommonEmitter |hfe| 4
SmallSignal, ShortCircuit, Forward Current Transfer Ratio

(IC = 1 A, f = 50 kHz)

*SmallSignal Current Gain hfe 40

(IC = 1 Adc, VCE = 4 Vdc, f = 1 kHz)
SECOND BREAKDOWN CHARACTERISTICS

Second Breakdown Collector Current with Base Forward Biased IS/b 1.5 Adc
t = 1 s (nonrepetitive), VCE = 100 V, See Figure 12
(2) Pulse Test: Pulse Width = 300 s, Duty Cycle 2%.
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47
2N3773 2N6609
NPN PNP
300 300
200 150C 200 150C
25C
100 100

-55C -55C
70 25C 70
50 50
30 VCE = 4 V 30 VCE = 4 V
20 20
10 10
7.0 7.0
5.0 5.0
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS)
Figure 10. DC Current Gain Figure 11. DC Current Gain
2.0 2.0

IC = 4 A IC = 4 A
1.6 1.6 IC = 16 A
1.2 1.2
IC = 8 A
IC = 8 A
IC = 16 A
0.8 0.8
0.4 0.4
TC = 25C TC = 25C
0 0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0
IB, BASE CURRENT (AMPS) IB, BASE CURRENT (AMPS)
Figure 12. Collector Saturation Region Figure 13. Collector Saturation Region
2.0 2.0
IC/IB = 10 IC/IB = 10
1.6 1.6
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
1.2 1.2 VBE(sat)

VBE(sat)
0.8 25C 0.8 25C
150C 150C
150C
0.4 150C 0.4 25C
VCE(sat) 25C
VCE(sat)
0
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
Figure 14. On Voltage Figure 15. On Voltage
http://onsemi.com
48
2N3773 2N6609
30
20 10 s
40 s
10

100 s
5.0 dc 200 s
3.0 1.0 ms
2.0
100 ms
1.0
0.5
500 ms
0.3 BONDING WIRE LIMIT
0.2 THERMAL LIMIT
@ TC = 25C, SINGLE PULSE
0.1
0.05
0.03
3.0 5.0 7.0 10 20 30 50 70 100 200 300
Figure 16. Forward Bias Safe Operating Area
There are two limitations on the power handling ability of limits are valid for duty cycles to 10% provided TJ(pk)
a transistor: average junction temperature and second < 200C. At high case temperatures, thermal limitations
breakdown. Safe operating area curves indicate IC VCE will reduce the power that can be handled to values less than
limits of the transistor that must be observed for reliable the limitations imposed by second breakdown.
operation: i.e., the transistor must not be subjected to greater
The data of Figure 7 is based on TJ(pk) = 200C; TC is
variable depending on conditions. Second breakdown pulse
100
POWER DERATING FACTOR (%)
80
60
THERMAL
40 DERATING
20
0
0 40 80 120 160 200
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49
ON Semiconductor
2N4918
Medium-Power Plastic PNP thru
Silicon Transistors 2N4920 *
. . . designed for driver circuits, switching, and amplifier *ON Semiconductor Preferred Device
applications. These highperformance plastic devices feature:
3 AMPERE
Low Saturation Voltage GENERALPURPOSE
VCE(sat) = 0.6 Vdc (Max) @ IC = 1.0 Amp POWER TRANSISTORS
Excellent Power Dissipation Due to Thermopad Construction 4080 VOLTS
PD = 30 W @ TC = 25C 30 WATTS
Excellent Safe Operating Area
Gain Specified to IC = 1.0 Amp
Complement to NPN 2N4921, 2N4922, 2N4923
*MAXIMUM RATINGS

Ratings Symbol 2N4918 2N4919 2N4920 Unit

CollectorEmitter Voltage VCEO 40 60 80 Vdc


EmitterBase Voltage
VCB
VEB
40 60
5.0
80 Vdc
Vdc
CASE 7709
TO225AA TYPE

Collector Current Continuous (1)

IC* 1.0
3.0
Adc

Base Current
IB 1.0 Adc


Derate above 25C
PD 30
0.24
Watts
W/C

Operating & Storage Junction TJ, Tstg 65 to +150 C
Temperature Range
THERMAL CHARACTERISTICS (2)


*Indicates JEDEC Registered Data for 2N4918 Series.

JC 4.16 C/W
(1) The 1.0 Amp maximum IC value is based upon JEDEC current gain requirements.
The 3.0 Amp maximum value is based upon actual currenthandling capability of the
device (See Figure 5).
(2) Recommend use of thermal compound for lowest thermal resistance.

March, 2001 Rev. 9 2N4918/D
2N4918 thru 2N4920
40

30
20
10
0
25 50 75 100 125 150
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51
2N4918 thru 2N4920

OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage (1) VCEO(sus) Vdc

(IC = 0.1 Adc, IB = 0) 2N4918 40
2N4919

60
2N4920 80


(VCE = 20 Vdc, IB = 0)

2N4918
ICEO
0.5
mAdc

(VCE = 30 Vdc, IB = 0) 2N4919 0.5
(VCE = 40 Vdc, IB = 0) 2N4920 0.5


(VCE = Rated VCEO, VBE(off) = 1.5 Vdc)
ICEX
0.1
mAdc

(VCE = Rated VCEO, VBE(off) = 1.5 Vdc, TC = 125C) 0.5

Collector Cutoff Current ICBO 0.1 mAdc

(VCB = Rated VCB, IE = 0)

Emitter Cutoff Current IEBO 1.0 mAdc
(VBE = 5.0 Vdc, IC = 0)
DC Current Gain (1)

ON CHARACTERISTICS

hFE

(IC = 50 mAdc, VCE = 1.0 Vdc) 40
(IC = 500 mAdc, VCE = 1.0 Vdc) 30

150
(IC = 1.0 Adc, VCE = 1.0 Vdc) 10

CollectorEmitter Saturation Voltage (1)

(IC = 1.0 Adc, IB = 0.1 Adc)
VCE(sat) 0.6 Vdc

BaseEmitter Saturation Voltage (1) VBE(sat) 1.3 Vdc

(IC = 1.0 Adc, IB = 0.1 Adc)

BaseEmitter On Voltage (1) VBE(on) 1.3 Vdc
(IC = 1.0 Adc, VCE = 1.0 Vdc)

SMALLSIGNAL CHARACTERISTICS

CurrentGain Bandwidth Product (IC = 250 mAdc, VCE = 10 Vdc, f = 1.0 MHz) fT 3.0 MHz

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 100 kHz)

SmallSignal Current Gain (IC = 250 mAdc, VCE = 10 Vdc, f = 1.0 kHz)
Cob
hfe

25
100

pF

(1) Pulse Test: PW 300 s, Duty Cycle 2.0%
VBE(off)
5.0
0 VCC = 30 V IC/IB = 10, UNLESS NOTED
Vin VCC 3.0
RC IC/IB = 20 TJ = 25C
APPROX 2.0 TJ = 150C
-11 V Vin SCOPE
t1 RB 1.0
VCC = 30 V
t, TIME (s)
Cjd<<Ceb 0.7

tr
APPROX 9.0 V 0.5 VCC = 60 V
t2 +4.0 V
0.3 td VCC = 60 V
RB and RC 0.2 VBE(off) = 2.0 V
Vin 0 varied to
t1 < 15 ns obtain desired
100 < t2 < 500 s 0.1
APPROX current levels VCC = 30 V
t3 < 15 ns 0.07
-11 V VBE(off) = 0
t3 DUTY CYCLE 2.0% 0.05
10 20 30 50 70 100 200 300 500 700 1000
TURN-OFF PULSE IC, COLLECTOR CURRENT (mA)
Figure 2. Switching Time Equivalent Test Circuit Figure 3. TurnOn Time
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52
2N4918 thru 2N4920
1.0
0.7 D = 0.5
r(t), TRANSIENT THERMAL RESISTANCE
0.5
0.3 0.2
0.2
(NORMALIZED)
0.1
JC(t) = r(t) JC P(pk)
0.1 0.05
JC = 4.16C/W MAX
0.07 0.01 D CURVES APPLY FOR POWER
0.05 PULSE TRAIN SHOWN t1
0.03 READ TIME AT t1 t2
SINGLE PULSE
TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)
Figure 4. Thermal Response

1.0 ms 100 s
5.0 5.0 ms breakdown. Safe operating area curves indicate IC VCE

operation i.e., the transistor must not be subjected to greater
2.0 TJ = 150C dissipation than the curves indicate.
dc The data of Figure 5 is based on TJ(pk) = 150C; TC is
1.0 variable depending on conditions. Second breakdown pulse
SECOND BREAKDOWN LIMITED limits are valid for duty cycles to 10% provided TJ(pk)
0.5 BONDING WIRE LIMITED 150C. At high case temperatures, thermal limitations
THERMALLY LIMIT @ TC = 25C will reduce the power that can be handled to values less than
0.2 PULSE CURVES APPLY BELOW the limitations imposed by second breakdown.
RATED VCEO
0.1
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
5.0 5.0
IC/IB = 20 TJ = 25C
3.0 3.0
IC/IB = 20 TJ = 150C
2.0 2.0 VCC = 30 V
t s, STORAGE TIME (s)
IB1 = IB2

t f , FALL TIME (s)
1.0 IC/IB = 10 1.0

0.7 0.7
0.5 0.5
IC/IB = 10
0.3 ts = ts - 1/8 tf 0.3
0.2 TJ = 25C 0.2
TJ = 150C
0.1 IB1 = IB2 0.1
0.07 0.07
0.05 0.05
10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 1000
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 6. Storage Time Figure 7. Fall Time
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53
2N4918 thru 2N4920
TYPICAL DC CHARACTERISTICS
1000 1.0

700 VCE = 1.0 V
500 IC = 0.1 A 0.25 A 0.5 A 1.0 A
0.8
TJ = 150C
300
200
0.6
25C
100 TJ = 25C
70 -55C 0.4
50
30
0.2
20
10 0
2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200
IC, COLLECTOR CURRENT (mA) IB, BASE CURRENT (mA)
Figure 8. Current Gain Figure 9. Collector Saturation Region
RBE , EXTERNAL BASE-EMITTER RESISTANCE (OHMS)
108 1.5
IC = 10 ICES VCE = 30 V
107 1.2 TJ = 25C

VOLTAGE (VOLTS)
106 0.9
IC ICES
105 IC = 2x ICES 0.6
VBE @ VCE = 2.0 V
ICES VALUES
104 OBTAINED FROM 0.3
FIGURE 13
103 0
0 30 60 90 120 150 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
TJ, JUNCTION TEMPERATURE (C) IC, COLLECTOR CURRENT (mA)
Figure 10. Effects of BaseEmitter Resistance Figure 11. On Voltage
102 +2.5
+2.0 hFE@VCE 1.0V
TEMPERATURE COEFFICIENTS (mV/ C)
*APPLIES FOR IC/IB <

101 2
+1.5

TJ = 150C
100 +1.0
TJ = 100C to 150C
+0.5
*VC FOR VCE(sat)
10-1 0
TJ = -55C to +100C
100C
-0.5
10-2 IC = ICES -1.0
VCE = 30 V -1.5
104
VB FOR VBE
25C -2.0
103 REVERSE FORWARD
-2.5
-0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
VBE, BASE-EMITTER VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (mA)
Figure 12. Collector CutOff Region Figure 13. Temperature Coefficients
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54
ON Semiconductor
2N4921
Medium-Power Plastic NPN
thru
Silicon Transistors
2N4923 *
. . . designed for driver circuits, switching, and amplifier
*ON Semiconductor Preferred Device
applications. These highperformance plastic devices feature:
Low Saturation Voltage 1 AMPERE
VCE(sat) = 0.6 Vdc (Max) @ IC = 1.0 Amp GENERALPURPOSE
POWER TRANSISTORS
Excellent Power Dissipation Due to Thermopad Construction
4080 VOLTS
PD = 30 W @ TC = 25C 30 WATTS
Excellent Safe Operating Area
Gain Specified to IC = 1.0 Amp
Complement to PNP 2N4918, 2N4919, 2N4920
*MAXIMUM RATINGS

Rating Symbol 2N4921 2N4922 2N4923 Unit

CollectorEmitter Voltage VCEO 40 60 80 Vdc

CollectorBase Voltage VCB 40 60 80 Vdc CASE 7709
TO225AA TYPE

EmitterBase Voltage VEB 5.0 Vdc

Collector Current Continuous (1) IC 1.0 Adc

3.0

Base Current Continuous IB 1.0 Adc


Operating & Storage Junction

Temperature Range

Characteristic

Symbol
JC
Max
4.16
Unit
C/W
(1) The 1.0 Amp maximum IC value is based upon JEDEC current gain requirements.
The 3.0 Amp maximum value is based upon actual current handling capability of the
device (see Figures 5 and 6)
(2) Recommend use of thermal compound for lowest thermal resistance.

March, 2001 Rev. 9 2N4921/D
2N4921 thru 2N4923
40

30
20
10
0
25 50 75 100 125 150
Safe Area Curves are indicated by Figure 5. All limits are applicable and must be observed.
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56
2N4921 thru 2N4923

OFF CHARACTERISTICS


(IC = 0.1 Adc, IB = 0) 2N4921 40
2N4922

60
2N4923 80


(VCE = 20 Vdc, IB = 0)

2N4921
ICEO
0.5
mAdc

(VCE = 30 Vdc, IB = 0) 2N4922 0.5
(VCE = 40 Vdc, IB = 0) 2N4923 0.5


(VCE = Rated VCEO, VEB(off) = 1.5 Vdc)
ICEX
0.1
mAdc

(VCE = Rated VCEO, VEB(off) = 1.5 Vdc, TC = 125C) 0.5



(VEB = 5.0 Vdc, IC = 0)
DC Current Gain (3)

ON CHARACTERISTICS

hFE

(IC = 50 mAdc, VCE = 1.0 Vdc) 40
(IC = 500 mAdc, VCE = 1.0 Vdc)

30 150
(IC = 1.0 Adc, VCE = 1.0 Vdc) 10


(IC = 1.0 Adc, IB = 0.1 Adc)
VCE(sat) 0.6 Vdc

BaseEmitter Saturation Voltage (3) VBE(sat) 1.3 Vdc

(IC = 1.0 Adc, IB = 0.1 Adc)

BaseEmitter On Voltage (3) VBE(on) 1.3 Vdc
(IC = 1.0 Adc, VCE = 1.0 Vdc)

SMALLSIGNAL CHARACTERISTICS

CurrentGain Bandwidth Product (IC = 250 mAdc, VCE = 10 Vdc, f = 1.0 MHz) fT 3.0 MHz

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 100 kHz)

SmallSignal Current Gain (IC = 250 mAdc, VCE = 10 Vdc, f = 1.0 kHz)
Cob
hfe

25
100

pF

(3) Pulse Test: PW 300 s, Duty Cycle 2.0%.
APPROX
TURN-ON PULSE 5.0
+11 V
t1 VCC = 30 V IC/IB = 10, UNLESS NOTED
VCC 3.0
Vin RC IC/IB = 20 TJ = 25C
2.0 TJ = 150C
Vin VCC = 60 V
VBE(off) RB 1.0
t, TIME (s)
Cjd<<Ceb 0.7

t3 0.5 tr
APPROX -4.0 V VCC = 30 V
SCOPE
+11 V t1 15 ns 0.3 td
0.2 VCC = 60 V
100 < t2 500 s
Vin VBE(off) = 2.0 V
t3 15 ns
0.1 VCC = 30 V
APPROX 9.0 V DUTY CYCLE 2.0% 0.07
t2 VBE(off) = 0
RB and RC varied to 0.05
TURN-OFF PULSE obtain desired 10 20 30 50 70 100 200 300 500 700 1000
current levels IC, COLLECTOR CURRENT (mA)
Figure 2. Switching Time Equivalent Circuit Figure 3. TurnOn Time
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57
2N4921 thru 2N4923
1.0
0.7 D = 0.5
RESISTANCE (NORMALIZED) 0.5
r(t), TRANSIENT THERMAL
0.3 0.2
0.2 P(pk)
0.1 JC(t) = r(t) JC
0.05 JC = 4.16C/W MAX
0.1
D CURVES APPLY FOR POWER
0.07 PULSE TRAIN SHOWN
0.05 0.01 t1
READ TIME AT t1 t2
0.03 TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)

7.0 a transistor: average junction temperature and second
5.0 100 s
5.0 ms 1.0 ms breakdown. Safe operating area curves indicate IC VCE

3.0 operation i.e., the transistor must not be subjected to greater
2.0 TJ = 150C dc dissipation than the curves indicate.
The data of Figure 5 is based on TJ(pk) = 150C; TC
1.0 is variable depending on conditions. Second breakdown
0.7 SECOND BREAKDOWN pulse limits are valid for duty cycles to 10% provided TJ(pk)
0.5 LIMITED
150C. At high case temperatures, thermal limitations
BONDING WIRE LIMITED
0.3 THERMALLY LIMITED @ TC = 25C will reduce the power that can be handled to values less than
0.2 PULSE CURVES APPLY BELOW the limitations imposed by second breakdown.
RATED VCEO
0.1
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
5.0 5.0
3.0 IC/IB = 20 3.0
IC/IB = 20
2.0 2.0
t s, STORAGE TIME (s)

1.0
t f , FALL TIME (s)
1.0

0.7 IC/IB = 10 IC/IB = 20 0.7

0.5 0.5
0.3 0.3 IC/IB = 10
0.2 TJ = 25C 0.2 TJ = 25C
TJ = 150C TJ = 150C
0.1 IB1 = IB2 0.1 VCC = 30 V
0.07 ts = ts - 1/8 tf 0.07 IB1 = IB2
0.05 0.05
10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 1000
Figure 6. Storage Time Figure 7. Fall Time
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58
2N4921 thru 2N4923
1000 1.0

700 VCE = 1.0 V
500 IC = 0.1 A 0.25 A 0.5 A 1.0 A
0.8
300
200 TJ = 150C
0.6 TJ = 25C
100
25C
70 0.4
50 -55C
30 0.2
20
10 0
2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200
IC, COLLECTOR CURRENT (mA) IB, BASE CURRENT (mA)
Figure 8. Current Gain Figure 9. Collector Saturation Region
108 1.5
IC = 10 x ICES VCE = 30 V TJ = 25C
107 1.2
IC = 2 x ICES VOLTAGE (VOLTS)
106 0.9
IC ICES
105 0.6
VBE @ VCE = 2.0 V
ICES VALUES
104 OBTAINED FROM 0.3
FIGURE 12
103 0
0 30 60 90 120 150 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
TJ, JUNCTION TEMPERATURE (C) IC, COLLECTOR CURRENT (mA)
Figure 10. Effects of BaseEmitter Resistance Figure 11. On Voltage
104 +2.5
+2.0 hFE@VCE 1.0V
TEMPERATURE COEFFICIENTS (mV/ C)
TJ = 150C *APPLIES FOR IC/IB

103 2
+1.5

102 100C +1.0 TJ = 100C to 150C

25C +0.5
*VC FOR VCE(sat)
101 0
-55C to +100C
IC = ICES -0.5
100 VCE = 30 V -1.0
10-1 -1.5
VB FOR VBE
-2.0
REVERSE FORWARD
10-2 -2.5
-0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
VBE, BASE-EMITTER VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (mA)
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59
ON Semiconductor
2N5038
NPN Silicon Transistors
. . . fast switching speeds and high current capacity ideally suit these
parts for use in switching regulators, inverters, wideband amplifiers
and power oscillators in industrial and commercial applications. 20 AMPERE
NPN SILICON
High Speed tf = 0.5 s (Max) POWER TRANSISTOR
High Current IC(max) = 30 Amps 90 VOLTS
Low Saturation VCE(sat) = 2.5 V (Max) @ IC = 20 Amps 140 WATTS
CASE 107
TO204AA
(TO3)

*MAXIMUM RATINGS



CollectorEmitter Voltage VCEV 150 Vdc


Peak (1)


ICM
IB
30
5 Adc

Total Device Dissipation @ TC = 25C

Derate above 25C

PD 140
0.8
Watts
W/C

Operating and Storage Junction Temperature Range TJ, Tstg 65 to +200 C


Thermal Resistance, Junction to Case RJC 1.25 C/W
(1) Pulse Test: Pulse Width 10 ms, Duty Cycle 50%.
VCC
+30 V
RC
2.5
+11 V 10
PW = 20 s
0 DUTY CYCLE = 1%
-9 V 1N4933
-5 V
2N5038 2N5039
IC = 12 AMPS IC = 10 AMPS
IB1 = IB2 = 1.2 AMPS IB1 = IB2 = 1.0 AMPS
Figure 1. Switching Time Test Circuit

May, 2001 Rev. 10 2N5038/D
2N5038
*ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)

OFF CHARACTERISTICS


(IC = 200 mAdc, IB = 0) 90


(VCE = 140 Vdc, VBE(off) = 1.5 V) 50

Emitter Cutoff Current IEBO mAdc

(VEB = 5 Vdc, IC = 0) 5
(VEB = 7 Vdc, IC = 0) 50

DC Current Gain hFE

(IC = 12 Adc, VCE = 5 Vdc) 20 100


(IC = 20 Adc, IB = 5 Adc)
VCE(sat) 2.5 Vdc

BaseEmitter Saturation Voltage VBE(sat) 3.3 Vdc


Magnitude of CommonEmitter SmallSignal ShortCircuit |hfe| 12

Forward Current Transfer Ratio

(IC = 2 Adc, VCE = 10 Vdc, f = 5 MHz)
SWITCHING CHARACTERISTICS

RESISTIVE LOAD
s

Rise Time (VCC = 30 Vdc) tr 0.5
Storage Time (IC = 12 Adc, IB1 = IB2 = 1.2 Adc) ts 1.5 s
(2) Pulse Test: Pulse Width 300, s, Duty Cycle 2%.

50 breakdown. Safe operating area curves indicate IC VCE

10 dc
5 Second breakdown pulse limits are valid for duty cycles
to 10%. At high case temperatures, thermal limitations may
2 reduce the power that can be handled to values less than the
1 BONDING WIRE LIMIT limitations imposed by second breakdown.
THERMAL LIMIT
0.5 SECOND BREAKDOWN LIMIT
TC = 25C
0.2
0.1
1 2 3 5 7 10 20 30 50 70 100
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61
ON Semiconductor
2N5191
Silicon NPN Power Transistors 2N5192 *
. . . for use in power amplifier and switching circuits, excellent *ON Semiconductor Preferred Device
safe area limits. Complement to PNP 2N5194, 2N5195.
4 AMPERE
POWER TRANSISTORS
SILICON NPN
6080 VOLTS
*MAXIMUM RATINGS
40 WATTS



CollectorBase Voltage VCB 60 80 Vdc


Collector Current IC 4.0 Adc

Base Current IB 1.0 Adc

Derate above 25C 320 mW/C


Temperature Range


Characteristic Symbol Max Unit CASE 7709

TO225AA TYPE
Thermal Resistance, Junction to Case JC 3.12 C

OFF CHARACTERISTICS


(IC = 0.1 Adc, IB = 0) 2N5191 60

2N5192 80

Collector Cutoff Current ICEO mAdc
(VCE = 60 Vdc, IB = 0) 2N5191 1.0

(VCE = 80 Vdc, IB = 0) 2N5192 1.0


(VCE = 60 Vdc, VEB(off) = 1.5 Vdc)
2N5191
2N5192
ICEX
0.1
mAdc

0.1
(VCE = 60 Vdc, VEB(off) = 1.5 Vdc, TC = 125C) 2N5191 2.0


Collector Cutoff Current ICBO mAdc

(VCB = 60 Vdc, IE = 0) 2N5191 0.1
(VCB = 80 Vdc, IE = 0) 2N5192 0.1


(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc

March, 2001 Rev. 9 2N5191/D
2N5191 2N5192
*ELECTRICAL CHARACTERISTICS continued (TC = 25C unless otherwise noted)

ON CHARACTERISTICS


(IC = 1.5 Adc, VCE = 2.0 Vdc) 2N5191 25 100
2N5192

20 80
(IC = 4.0 Adc, VCE = 2.0 Vdc) 2N5191 10

2N5192 7.0

CollectorEmitter Saturation Voltage (2) VCE(sat) Vdc

(IC = 1.5 Adc, IB = 0.15 Adc) 0.6
(IC = 4.0 Adc, IB = 1.0 Adc) 1.4

BaseEmitter On Voltage (2)

(IC = 1.5 Adc, VCE = 2.0 Vdc)
VBE(on) 1.2 Vdc


CurrentGain Bandwidth Product
fT 2.0 MHz

10
7.0 TJ = 150C
VCE = 2.0 V
hFE , DC CURRENT GAIN (NORMALIZED)
5.0 VCE = 10 V
3.0
2.0
1.0
0.7 -55C
25C
0.5
0.3
0.2
0.1
0.004 0.007 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0
2.0
TJ = 25C
1.6
1.2 IC = 10 mA 100 mA 1.0 A 3.0 A
0.8
0.4
0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
IB, BASE CURRENT (mA)
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63
2N5191 2N5192
2.0 +2.5
V, TEMPERATURE COEFFICIENTS (mV/C)

TJ = 25C +2.0 hFE@VCE 2.0V
*APPLIES FOR IC/IB
1.6 +1.5 2
TJ = -65C to +150C
+1.0
1.2 +0.5 *V for VCE(sat)
0
0.8 VBE(sat) @ IC/IB = 10 -0.5
VBE @ VCE = 2.0 V -1.0
0.4 -1.5 V for VBE
VCE(sat) @ IC/IB = 10 -2.0
0 -2.5
0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0
Figure 3. On Voltages Figure 4. Temperature Coefficients

103 107
VCE = 30 V VCE = 30 V
IC = 10 x ICES
102
106
TJ = 150C
101 IC ICES
105
100 100C IC = 2 x ICES
104
REVERSE FORWARD
10-1
10-2 103 (TYPICAL ICES VALUES

25C
OBTAINED FROM FIGURE 5)
ICES
10-3 102
-0.4 -0.3 -0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 20 40 60 80 100 120 140 160
VBE, BASE-EMITTER VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (C)
Figure 5. Collector CutOff Region Figure 6. Effects of BaseEmitter Resistance
300
VCC TJ = +25C
TURN-ON PULSE RC
APPROX 200
+11 V Vin SCOPE
RB
CAPACITANCE (pF)
Vin 0 Cjd<<Ceb
VEB(off) 100
t1 -4.0 V
t3 Ceb
APPROX RB and RC varied 70
t1 7.0 ns
+11 V to obtain desired
100 < t2 < 500 s current levels
t3 < 15 ns 50 Ccb
Vin
DUTY CYCLE 2.0% 30

t2 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 40
APPROX -9.0 V
TURN-OFF PULSE VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Switching Time Equivalent Test Circuit Figure 8. Capacitance
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64
2N5191 2N5192
2.0 2.0
ts
IC/IB = 10
1.0 TJ = 25C 1.0
0.7 tr @ VCC = 30 V 0.7 tf @ VCC = 30 V
0.5 0.5
t, TIME (s)
0.3 0.3

tr @ VCC = 10 V tf @ VCC = 10 V
0.2 0.2
0.1 0.1 IB1 = IB2

0.07 0.07 IC/IB = 10
td @ VEB(off) = 2.0 V ts = ts - 1/8 tf
0.05 0.05
TJ = 25C
0.03 0.03
0.02 0.02
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 4.0 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 4.0
Figure 9. TurnOn Time Figure 10. TurnOff Time

100s a transistor; average junction temperature and second
5.0 5.0ms
1.0ms breakdown. Safe operating area curves indicate IC VCE

TJ = 150C limits of the transistor that must be observed for reliable
2.0 dc operation; i.e., the transistor must not be subjected to greater
1.0 The data of Figure 11 is based on T J(pk) = 150C; TC is
SECONDARY BREAKDOWN LIMIT variable depending on conditions. Second breakdown pulse
0.5 THERMAL LIMIT AT TC = 25C limits are valid for duty cycles to 10% provided TJ(pk)
BONDING WIRE LIMIT
150C. At high case temperatures, thermal limitations
0.2 2N5191
will reduce the power that can be handled to values less than
2N5192
the limitations imposed by second breakdown.
0.1
1.0 2.0 5.0 10 20 50 100
Figure 11. Rating and Thermal Data

ActiveRegion Safe Operating Area
1.0
0.7
THERMAL RESISTANCE (NORMALIZED)
D = 0.5
0.5 JC(max) = 3.12C/W 2N5190-92
r(t), EFFECTIVE TRANSIENT
JC(max) = 2.08C/W MJE5190-92

0.3
0.2
0.2
0.1
0.1 0.05
0.07
0.05 0.02
0.03 0.01
SINGLE PULSE
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 50 100 200 500 1000
t, TIME OR PULSE WIDTH (ms)
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65
2N5191 2N5192
DESIGN NOTE: USE OF TRANSIENT THERMAL RESISTANCE DATA
tP A train of periodical power pulses can be represented by

the model shown in Figure A. Using the model and the
device thermal response, the normalized effective transient
PP PP
thermal resistance of Figure 12 was calculated for various
duty cycles.
To find JC(t), multiply the value obtained from Figure 12
by the steady state value JC.
Example:
t1
The 2N5190 is dissipating 50 watts under the following
1/f conditions: t1 = 0.1 ms, tp = 0.5 ms. (D = 0.2).
t1 Using Figure 12, at a pulse width of 0.1 ms and D = 0.2,
DUTY CYCLE, D = t1 f -
tP the reading of r(t1, D) is 0.27.
PEAK PULSE POWER = PP The peak rise in function temperature is therefore:
Figure A
T = r(t) x PP x JC = 0.27 x 50 x 3.12 = 42.2C
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66
ON Semiconductor
2N5194
Silicon PNP Power Transistors
2N5195 *
. . . for use in power amplifier and switching circuits, excellent *ON Semiconductor Preferred Device
safe area limits. Complement to NPN 2N5191, 2N5192
4 AMPERE
POWER TRANSISTORS
SILICON PNP
6080 VOLTS
*MAXIMUM RATINGS









Temperature Range
TJ, Tstg 65 to +150 C/W
CASE 7709

Characteristic Symbol Max Unit TO225AA TYPE



OFF CHARACTERISTICS

(IC = 0.1 Adc, IB = 0)

2N5194
2N5195
60
80


(VCE = 60 Vdc, IB = 0) 2N5194 1.0
(VCE = 80 Vdc, IB = 0) 2N5195 1.0


(VCE = 60 Vdc, VBE(off) = 1.5 Vdc) 2N5194
ICEX
0.1
mAdc

(VCE = 80 Vdc, VBE(off) = 1.5 Vdc) 2N5195 0.1
(VCE = 60 Vdc, VBE(off) = 1.5 Vdc, TC = 125C) 2N5194 2.0

(VCE = 80 Vdc, VBE(off) = 1.5 Vdc, TC = 125C) 2N5195 2.0


(VCB = 60 Vdc, IE = 0)
(VCB = 80 Vdc, IE = 0)

2N5194
2N5195
ICBO

0.1
0.1
mAdc


(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc

March, 2001 Rev. 9 2N5194/D
2N5194 2N5195
*ELECTRICAL CHARACTERISTICS continued (TC = 25C unless otherwise noted)

ON CHARACTERISTICS


(IC = 1.5 Adc, VCE = 2.0 Vdc) 2N5194 25 100
2N5195

20 80
(IC = 4.0 Adc, VCE = 2.0 Vdc) 2N5194 10

2N5195 7.0

CollectorEmitter Saturation Voltage (2) VCE(sat) Vdc

(IC = 1.5 Adc, IB = 0.15 Adc) 0.6
(IC = 4.0 Adc, IB = 1.0 Adc) 1.4

BaseEmitter On Voltage (2)

(IC = 1.5 Adc, VCE = 2.0 Vdc)
VBE(on) 1.2 Vdc


fT 2.0 MHz

10
7.0 TJ = 150C VCE = 2.0 V
5.0 VCE = 10 V
3.0
2.0
1.0 25C
0.7 -55C
0.5
0.3
0.2
0.1
0.004 0.007 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0
2.0
1.6
1.2 IC = 10 mA 100 mA 1.0 A 3.0 A
0.8
TJ = 25C
0.4
0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
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68
2N5194 2N5195
2.0 +2.5

+2.0 *APPLIES FOR IC/IB hFE @ VCE
TJ = 25C
TJ = -65C to +150C
1.6 +1.5
+1.0
VOLTAGE (VOLTS)
1.2 +0.5 *VC for VCE(sat)

0
0.8 VBE(sat) @ IC/IB = 10 -0.5
VBE @ VCE = 2.0 V
-1.0
0.4 -1.5 VB for VBE
VCE(sat) @ IC/IB = 10 -2.0
0 -2.5
0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0 0.005 0.01 0.020.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0
Figure 3. On Voltage Figure 4. Temperature Coefficients

103 107
VCE = 30 Vdc VCE = 30 V
102
106

TJ = 150C
IC = 10 x ICES
101
105
100C
100 IC = 2 x ICES
IC ICES
104
10-1 REVERSE FORWARD
(TYPICAL ICES VALUES

10-2
25C 103
ICES
10-3 102
+0.4 +0.3 +0.2 +0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 20 40 60 80 100 120 140 160
TURN-ON PULSE VCC RC 500

VBE(off) TJ = 25C
Vin 0 Vin RB SCOPE
300
APPROX
CAPACITANCE (pF)
-11 V Cjd<<Ceb 200

t1
APPROX +4.0 V
+9.0 V
t2
RB AND RC VARIED Ceb
100
TO OBTAIN DESIRED Ccb
Vin
CURRENT LEVELS
70
APPROX
-11 V t3 t1 7.0 ns
100 < t2 < 500 s 50
TURN-OFF PULSE 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 40
t3 < 15 ns
DUTY CYCLE 2.0% VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Switching Time Equivalent Test Circuit Figure 8. Capacitance
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69
2N5194 2N5195
2.0 2.0
IB1 = IB2
IC/IB = 10 ts
1.0 1.0 IC/IB = 10
TJ = 25C
ts = ts - 1/8 tf
0.7 0.7
TJ = 25C
0.5 tr @ VCC = 30 V 0.5
t, TIME (s)
t, TIME (s)
0.3 0.3 tf @ VCC = 30 V

0.2 0.2
tr @ VCC = 10 V tf @ VCC = 10 V
0.1 0.1
0.07 0.07
0.05 0.05
td @ VBE(off) = 2.0 V
0.03 0.03
0.02 0.02
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 4.0 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 4.0
Note 1:
1.0 ms a transistor; average junction temperature and second
5.0 5.0 ms

100 s limits of the transistor that must be observed for reliable
TJ = 150C
1.0 SECONDARY BREAKDOWN LIMIT The data of Figure 11 is based on TJ(pk) = 150C. TC is
THERMAL LIMIT @ TC = 25C variable depending on conditions. Second breakdown pulse
0.5 BONDING WIRE LIMIT limits are valid for duty cycles to 10% provided TJ(pk)
CURVES APPLY BELOW RATED VCEO 150C. At highcase temperatures, thermal limitations
0.2 will reduce the power that can be handled to values less than
2N5194
the limitations imposed by second breakdown.
2N5195
0.1
1.0 2.0 5.0 10 20 50 100
Figure 11. Rating and Thermal Data
ActiveRegion Safe Operating Area
1.0
0.7
D = 0.5
0.5 JC(max) = 3.12C/W
0.3 0.2
0.2
0.1
0.1 0.05
0.07
0.02
0.05
0.03 0.01
SINGLE PULSE
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
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70
2N5194 2N5195
DESIGN NOTE: USE OF TRANSIENT THERMAL RESISTANCE DATA
tP A train of periodical power pulses can be represented by

the model shown in Figure 13. Using the model and the
device thermal response, the normalized effective transient
PP PP
thermal resistance of Figure 12 was calculated for various
duty cycles.
To find JC(t), multiply the value obtained from Figure 12
by the steady state value JC.
Example:
t1
The 2N5193 is dissipating 50 watts under the following
1/f conditions: t1 = 0.1 ms, tp = 0.5 ms. (D = 0.2).
t1 Using Figure 12, at a pulse width of 0.1 ms and D = 0.2,
DUTY CYCLE, D = t1 f =
tP the reading of r(t1, D) is 0.27.
PEAK PULSE POWER = PP The peak rise in junction temperature is therefore:
Figure 13. T = r(t) x PP x JC = 0.27 x 50 x 3.12 = 42.2C
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71
ON Semiconductor
High-Power NPN Silicon 2N5302

Transistor
. . . for use in power amplifier and switching circuits applications.
Low CollectorEmitter Saturation Voltage
VCE(sat) = 0.75 Vdc (Max) @ IC = 10 Adc 30 AMPERE
POWER TRANSISTOR
NPN SILICON
60 VOLTS
*MAXIMUM RATINGS
200 WATTS

Rating Symbol 2N5302 Unit

CollectorEmitter Voltage VCEO 60 Vdc




Total Device Dissipation @ TC = 25C PD 200 Watts CASE 107
Derate above 25C 1.14 W/C TO204AA

(TO3)
C
Operating and Storage Junction TJ, Tstg 65 to +200

Temperature Range

Characteristic

Symbol
JC
Max
0.875
Unit
C/W

Thermal Resistance, Case to Ambient
CA 34 C/W
TA TC
8.0 200
6.0 150 TC
4.0 100 TA
2.0 50
0 0
0 20 40 60 80 100 120 140 160 180 200
TEMPERATURE (C)
Figure 1. Power Temperature Derating Curve

May, 2001 Rev. 0 2N5302/D
2N5302

*OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage (Note 1) VCEO(sus) Vdc

(IC = 200 mAdc, IB = 0) 60

(VCE = 60 Vdc, IB = 0) 5.0


ICEX
1.0
mAdc

(VCE = 60 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 10


(VCB = 80 Vdc, IE = 0)

ICBO
1.0
mAdc

Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0) IEBO 5.0 mAdc
ON CHARACTERISTICS

DC Current Gain (Note 1) hFE
*(IC = 1.0 Adc, VCE = 2.0 Vdc)

40
*(IC = 15 Adc, VCE = 2.0 Vdc) 15 60

*(IC = 30 Adc, VCE = 4.0 Vdc) 5.0

*CollectorEmitter Saturation Voltage (Note 1) VCE(sat) Vdc
(IC = 10 Adc, IB = 1.0 Adc)

0.75
(IC = 20 Adc, IB = 2.0 Adc)2 2.0

(IC = 30 Adc, IB = 6.0 Adc) 3.0

*Base Emitter Saturation Voltage (Note 1) VBE(sat) Vdc
(IC = 10 Adc, IB = 1.0 Adc)

1.7
(IC = 15 Adc, IB = 1.5 Adc) 1.8

(IC = 20 Adc, IB = 2.0 Adc) 2.5

*BaseEmitter On Voltage (Note 1) VBE(on) Vdc
(IC = 15 Adc, VCE = 2.0 Vdc) 1.7

(IC = 30 Adc, VCE = 4.0 Vdc)

3.0

CurrentGain Bandwidth Product (IC = 1.0 Adc, VCE = 10 Vdc, f = 1.0 MHz) fT 2.0 MHz

SmallSignal Current Gain (IC = 1.0 Adc, VCE = 10 Vdc, f = 1.0 kHz) hfe 40

*SWITCHING CHARACTERISTICS
s

Rise Time tr 1.0
Storage Time ts 2.0 s

((VCC = 30 Vdc,
dc, IC = 10
0 Adc,
dc, IB1 = IB2 = 1.0
0 Adc)
dc)
Fall Time tf 1.0 s
Note 1: Pulse Width 300 s, Duty Cycle 2.0%.
SWITCHING TIME EQUIVALENT TEST CIRCUITS
INPUT PULSE
INPUT PULSE tr 20 ns VCC
tr 20 ns VCC +30 V
+30 V PW = 10 to 100 s
PW = 10 to 100 s DUTY CYCLE = 2.0%
3.0 +11 V
+11 V
10 TO
10 TO SCOPE
0
SCOPE tr 20 ns
-2.0 V tr 20 ns D
-9.0 V
VBB = 7.0 V
Figure 2. TurnOn time Figure 3. TurnOff time
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73
2N5302
1.0
r(t), NORMALIZED EFFECTIVE TRANSIENT
0.7 D = 0.5
0.5
0.3
THERMAL RESISTANCE
0.2
0.2
0.1
0.1
0.05 JC = 0.875C/W MAX
0.07
0.05 0.02
SINGLE PULSE TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
0.02
0.01
0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
t, TIME (ms)
100 3000
50 100 s 2000
20 C, CAPACITANCE (pF) TJ = 25C

10 1000
5302 5.0 ms
5.0 dc Cib
1.0 ms
TJ = 200C
2.0 Secondary Breakdown Limited 500
Cob
Bonding Wire Limited
1.0 TC = 25C 300
Thermal Limitations
0.5 Pulse Duty Cycle 10%
200
0.2 2N5302
0.1 100
1.0 2.0 3.0 5.0 10 20 30 50 100 0.5 1.0 2.0 3.0 5.0 7.0 10 20 30 50
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS)
Figure 5. ActiveRegion Safe Operating Area Figure 6. Capacitance versus Voltage
5.0 3.0
TJ = 25C
3.0 TJ = 25C IB1 = IB2
2.0 IC/IB = 10 IC/IB = 10
ts
ts ts - 1/8 tf
1.0 1.0
t, TIME (s)
t, TIME (s)
0.7 0.7

0.5
0.5
0.3 tr @ VCC = 30 V tf @ VCC = 30 V
0.2 0.3
tr @ VCC = 10 V tf @ VCC = 10 V
0.1 td @ VOB = 2.0 V
0.07
0.05 0.1
0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30
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74
2N5302
300 2.0

TJ = 175C VCE = 10 V TJ = 25C
200 VCE = 2.0 V
1.6
IC = 2.0 A 5.0 A 10 A 20 A
100 25C
1.2
70
50
0.8
-55C
30
20 0.4
10 0
0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
IC, COLLECTOR CURRENT (AMP) IB, BASE CURRENT (AMP)
108 2.0
VCE = 30 V 1.8 TJ = 25C
107
1.6
IC = 10 x ICES
1.4
V, VOLTAGE (VOLTS)
106
IC = 2 x ICES 1.2
105 1.0
IC ICES 0.8 VBE(sat) @ IC/IB = 10
104
0.6
VBE(on) @ VCE = 2.0 V
0.4
103 TYPICAL ICES VALUES OBTAINED
FROM FIGURE 13 0.2 VCE(sat) @ IC/IB = 10
102 0
0 20 40 60 80 100 120 140 160 180 200 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30
TJ, JUNCTION TEMPERATURE (C) IC, COLLECTOR CURRENT (AMP)
Figure 11. Effects of BaseEmitter Resistance Figure 12. On Voltages
103 +2.5
VCE = 30 V TJ = 175C +2.0 TJ = -55C to +175C

102 hFE@VCE 2.0V
+1.5 *APPLIES FOR IC/IB <

100C

2
+1.0
101
25C +0.5
*VC for VCE(sat)
100 0
IC = ICES
-0.5
10-1
-1.0
10-2 -1.5 VB for VBE(sat)

REVERSE FORWARD
-2.0
10-3 -2.5
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30
VBE, BASE-EMITTER VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (AMP)
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75
ON Semiconductor
NPN
High-Voltage - High Power 2N5631
PNP
Transistors 2N6031
. . . designed for use in high power audio amplifier applications and
high voltage switching regulator circuits.
High Collector Emitter Sustaining Voltage 16 AMPERE
VCEO(sus) = 140 Vdc POWER TRANSISTORS
High DC Current Gain @ IC = 8.0 Adc COMPLEMENTARY
SILICON
hFE = 15 (Min)
140 VOLTS
Low CollectorEmitter Saturation Voltage 200 WATTS
VCE(sat) = 1.0 Vdc (Max) @ IC = 10 Adc
MAXIMUM RATINGS (1)

Rating

Symbol
VCEO
Value
140
Unit
Vdc


EmitterBase Voltage
VCB
VEB
140
7.0
Vdc
Vdc

Collector Current Continuous IC 16 Adc CASE 107
Peak 20

TO204AA
(TO3)


Derate above 25C
PD 200
1.14
Watts
W/C

Temperature Range

(1) Indicates JEDEC Registered Data.
200
150
100
50
0
0 20 40 60 80 100 120 140 160 180 200
TC, TEMPERATURE (C)

Safe Area Curves are indicated by Figure 5. All Limits are applicable and must be observed.

May, 2001 Rev. 0 2N5631/D
2N5631 2N6031

OFF CHARACTERISTICS


(IC = 200 mAdc, IB = 0) 140

CollectorEmitter Cutoff Current ICEO mAdc
(VCE = 70 Vdc, IB = 0)

CollectorEmitter Cutoff Current ICEX
2.0
mAdc

(VCE = Rated VCB, VEB(off) = 1.5 Vdc) 2.0

(VCE = Rated VCB, VEB(off) = 1.5 Vdc, TC = 150C) 7.0

CollectorBase Cutoff Current ICBO 2.0 mAdc

EmitterBase Cutoff Current

(VBE = 7.0 Vdc, IC = 0)

IEBO 5.0 mAdc
DC Current Gain


hFE

(IC = 8 Adc, VCE = 2.0 Vdc) 15 60
(IC = 16 Adc, VCE = 2.0 Vdc) 4.0


(IC = 10 Adc, IB = 1.0 Adc)

VCE(sat)
1.0
Vdc

(IC = 16 Adc, IB = 4.0 Adc) 2.0

(IC = 10 Adc, IB = 1.0 Adc)


(IC = 8.0 Adc, VCE = 2.0 Vdc)
VBE(on) 1.5 Vdc

CurrentGain Bandwidth Product (3) fT 1.0 MHz

(IC = 1.0 Adc, VCE = 20 Vdc, ftest = 0.5 MHz)

Output Capacitance 2N5631 Cob 500 pF
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) 2N6031 1000


(IC = 4.0 Adc, VCE = 10 Vdc, f = 1.0 kHz)
hfe 15

(2) fT = |hfe| ftest
VCC 3.0
+30 V 2.0 TJ = 25C
IC/IB = 10
25 s 1.0 VCE = 30 V
RC
+11 V 0.7
SCOPE tr
0 RB 0.5
t, TIME (s)

-9.0 V 0.3
51 D1 0.2
tr, tf 10 ns td @ VBE(off) = 5.0 V
DUTY CYCLE = 1.0% -4 V 0.1
RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS 0.07
0.05 2N5631
D1 MUST BE FAST RECOVERY TYPE, e.g.: 2N6031
1N5825 USED ABOVE IB 100 mA 0.03
MSD6100 USED BELOW IB 100 mA 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
For PNP test circuit, reverse all polarities and D1. IC, COLLECTOR CURRENT (AMP)
Figure 2. Switching Times Test Circuit Figure 3. TurnOn Time
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77
2N5631 2N6031
1.0
D = 0.5
0.2
0.2
0.1
0.1 0.05 JC = 0.875C/W MAX
0.05
READ TIME AT t1 t2
SINGLE PULSE 0.01 TJ(pk) - TC = P(pk) JC(t)
0.02 DUTY CYCLE, D = t1/t2
0.01
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000
t, TIME (ms)

1.0ms
5.0ms a transistor: average junction temperature and second
10

7.0 dc
0.5ms limits of the transistor that must be observed for reliable
5.0
3.0 TJ = 200C 50ms
2.0 SECOND BREAKDOWN LIMITED
THERMALLY LIMITED @ TC = 25C variable depending on conditions. Second breakdown pulse
1.0
limits are valid for duty cycles to 10% provided TJ(pk)
0.7
CURVES APPLY BELOW 200C. TJ(pk) may be calculated from the data in
0.5
RATED VCEO Figure 4. At high case temperatures, thermal limitations will
0.3 2N5631, 2N6031 reduce the power that can be handled to values less than the
0.2 limitations imposed by second breakdown.
2.0 3.0 5.0 7.0 10 20 30 50 70 100 200
NPN PNP
2N5631 2N6031
5.0 4.0
TJ = 25C TJ = 25C
3.0
IC/IB = 10 ts IB1 = IB2
3.0 ts IB1 = IB2 IC/IB = 10
2.0
VCE = 30 V VCE = 30 V
2.0
t, TIME (s)

1.0
0.6
1.0
tf 0.4
0.7 0.3 tf
0.5 0.2
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
Figure 6. TurnOff Time
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78
2N5631 2N6031
NPN PNP
2N5631 2N6031
1000 2000
700 TJ = 25C
TJ = 25C
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
500 1000
Cib
700
300
500 Cib
200
300
Cob Cob
100 200
0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200
VR, REVERSE VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitance
500 500
TJ = 150C TJ = +150C
300 VCE = 2.0 V 300 VCE = 2.0 V
200 VCE = 10 V 200 VCE = 10 V
25C +25C
100 100 -55C

-55C
70 70
50 50
30 30
20 20
10 10
7.0 7.0
5.0 5.0
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 10 20
2.0 2.0
TJ = 25C TJ = 25C
1.6 1.6
1.2 IC = 4.0 A 8.0 A 16 A 1.2 IC = 4.0 A 8.0 A 16 A
0.8 0.8
0.4 0.4
0 0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0
IB, BASE CURRENT (AMP) IB, BASE CURRENT (AMP)
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79
ON Semiconductor
Plastic NPN Silicon 2N5655

High-Voltage Power Transistor 2N5657
. . . designed for use in lineoperated equipment such as audio
output amplifiers; lowcurrent, highvoltage converters; and AC line
relays. 0.5 AMPERE
POWER TRANSISTORS
Excellent DC Current Gain NPN SILICON
hFE = 30250 @ IC = 100 mAdc 250350 VOLTS
CurrentGain Bandwidth Product 20 WATTS
fT = 10 MHz (Min) @ IC = 50 mAdc

MAXIMUM RATINGS (1)





Collector Current Continuous IC 0.5 Adc
Peak 1.0 CASE 7709

TO225AA TYPE


Derate above 25C
PD 20
0.16
Watts
W/C

Temperature Range


40
30
50 mH
X
20
200
Hg RELAY TO SCOPE
+ +
6.0 V 50 V
10 -
Y
300 1.0
0
25 50 75 100 125 150
Figure 1. Power Derating Figure 2. Sustaining Voltage Test Circuit
Safe Area Limits are indicated by Figures 3 and 4. Both limits are applicable and must be observed.

May, 2001 Rev. 6 2N5655/D
2N5655 2N5657


OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage 2N5655 VCEO(sus) 250 Vdc

(IC = 100 mAdc (inductive), L = 50 mH) 2N5657 350
CollectorEmitter Breakdown Voltage 2N5655 V(BR)CEO 250 Vdc

(IC = 1.0 mAdc, IB = 0)

2N5657
ICEO
350
mAdc

(VCE = 150 Vdc, IB = 0) 2N5655 0.1
(VCE = 250 Vdc, IB = 0) 2N5657 0.1


2N5655
2N5657
ICEX
0.1
mAdc

0.1


Collector Cutoff Current ICBO Adc
(VCB = 275 Vdc, IE = 0) 2N5655 10

(VCB = 375 Vdc, IE = 0) 2N5657 10

Emitter Cutoff Current (VEB = 6.0 Vdc, IC = 0) IEBO 10 Adc
ON CHARACTERISTICS

(IC = 50 mAdc, VCE = 10 Vdc) 25

(IC = 100 mAdc, VCE = 10 Vdc) 30 250

(IC = 250 mAdc, VCE = 10 Vdc) 15
(IC = 500 mAdc, VCE = 10 Vdc) 5.0


(IC = 100 mAdc, IB = 10 mAdc)
(IC = 250 mAdc, IB = 25 mAdc)
VCE(sat)
1.0
Vdc

2.5
(IC = 500 mAdc, IB = 100 mAdc) 10

BaseEmitter Voltage (1) (IC = 100 mAdc, VCE = 10 Vdc)

VBE 1.0 Vdc

CurrentGain Bandwidth Product (2) (IC = 50 mAdc, VCE = 10 Vdc, f = 10 MHz) fT 10 MHz

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 100 kHz) Cob 25 pF
SmallSignal Current Gain (IC = 100 mAdc, VCE = 10 Vdc, f = 1.0 kHz) hfe 20
*Indicates JEDEC Registered Data for 2N5655 Series.
(2) fT is defined as the frequency at which |hfe| extrapolates to unity.
1.0 There are two limitations on the power handling ability of

0.5 s

500
TJ = 150C s limits of the transistor that must be observed for reliable
0.2 1.0 ms operation; i.e., the transistor must not be subjected to greater
d dissipation than the curves indicate.
0.1 c The data of Figure 3 is based on TJ(pk) = 150C; TC is
Second Breakdown Limit
Thermal Limit @ TC = 25C
0.05 Bonding Wire Limit limits are valid for duty cycles to 10% provided TJ(pk)
Curves apply below rated VCEO 150C. At high case temperatures, thermal limitations
0.02 2N5655 will reduce the power that can be handled to values less than
2N5657 the limitations imposed by second breakdown.
0.01
20 30 40 60 100 200 300 400 600
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81
2N5655 2N5657
300
200 VCE = 10 V
VCE = 2.0 V
100 TJ = +150C
70
+100C
50 +25C
30
20 -55C
10
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
IC, COLLECTOR CURRENT (mA)
Figure 4. Current Gain
1.0 300
200 TJ = +25C
0.8 VBE(sat) @ IC/IB = 10 Cib
C, CAPACITANCE (pF)
V, VOLTAGE (VOLTS)
100
0.6 VBE @ VCE = 10 V
70
50
0.4
30
0.2 TJ = +25C 20 Cob
IC/IB = 5.0
0 10
10 20 30 50 100 200 300 500 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
IC, COLLECTOR CURRENT (mA) VR, REVERSE VOLTAGE (VOLTS)
Figure 5. On Voltages Figure 6. Capacitance
10 10
tr IC/IB = 10
5.0 IC/IB = 10
VCC = 300 V, VBE(off) = 2.0 V 5.0
2.0 (2N5657, only)
VCC = 100 V, VBE(off) = 0 V
1.0 2.0 ts
t, TIME (s)
t, TIME (s)
0.5

td 1.0 tf
0.2
0.1 0.5 VCC = 100 V
0.05
0.2 VCC = 300 V
0.02 (Type 2N5657, only)
0.01 0.1
1.0 2.0 5.0 10 20 50 100 200 500 1.0 2.0 5.0 10 20 50 100 200 500
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82
ON Semiconductor
PNP
High-Current Complementary 2N5684
Silicon Power Transistors NPN
. . . designed for use in highpower amplifier and switching circuit
2N5686
applications.
High Current Capability
IC Continuous = 50 Amperes. 50 AMPERE
DC Current Gain COMPLEMENTARY
hFE = 1560 @ IC = 25 Adc SILICON
POWER TRANSISTORS
Low CollectorEmitter Saturation Voltage 6080 VOLTS
VCE(sat) = 1.0 Vdc (Max) @ IC = 25 Adc 300 WATTS
MAXIMUM RATINGS (1)

2N5684

Rating Symbol 2N5686 Unit



CASE 197A05

Collector Current Continuous IC 50 Adc TO204AE




Temperature Range


JC 0.584 C/W
300
250
200
150
100
50
0
0 20 40 60 80 100 120 140 160 180 200
TEMPERATURE (C)
Safe Area Curves are indicated by Figure 5. All limits are applicable and must be observed.

May, 2001 Rev. 10 2N5684/D
2N5684 2N5686

OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage (Note 2) VCEO(sus) Vdc

(IC = 0.2 Adc, IB = 0) 80

(VCE = 40 Vdc, IB = 0) 1.0


ICEX
2.0
mAdc

(VCE = 80 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 10

(VCB = 80 Vdc, IE = 0)

Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0) IEBO

2.0
5.0 mAdc

DC Current Gain (Note 2)
ON CHARACTERISTICS

hFE

(IC = 25 Adc, VCE = 2.0 Vdc) 15 60
(IC = 50 Adc, VCE = 5.0 Vdc) 5.0

CollectorEmitter Saturation Voltage (Note 2)

(IC = 25 Adc, IB = 2.5 Adc)
(IC = 50 Adc, IB = 10 Adc)

VCE(sat)
1.0
Vdc

5.0
BaseEmitter Saturation Voltage (Note 1) (IC = 25 Adc, IB = 2.5 Adc) VBE(sat) 2.0 Vdc

BaseEmitter On Voltage (Note 1) (IC = 25 Adc, VCE = 2.0 Vdc)

VBE(on) 2.0 Vdc

CurrentGain Bandwidth Product (IC = 5.0 Adc, VCE = 10 Vdc, f = 1.0 MHz) fT 2.0 MHz


(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) 2N5686 1200
SmallSignal Current Gain (IC = 10 Adc, VCE = 5.0 Vdc, f = 1.0 kHz) hfe 15
Note 2: Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
VCC -30 V
RL
+2.0 V
TO SCOPE
0 1.0
tr 20 ns
RB 0.7
0.5 tr
tr -12V
20ns 0.3
10 to 100 s
0.2 2N5684 (PNP)
DUTY CYCLE 2.0%
t, TIME (s)
VCC -30 V td 2N5686 (NPN)

0.1
RL 0.07
+10V
0.05
TO SCOPE TJ = 25C
0 tr 20 ns 0.03
RB IC/IB = 10
0.02 VCC = 30 V
-12V
tr 20ns
VBB +4.0 V 0.01
10 to 100 s 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
DUTY CYCLE 2.0% IC, COLLECTOR CURRENT (AMP)
FOR CURVES OF FIGURES 3 & 6, RB & RL ARE VARIED. Figure 3. TurnOn Time
INPUT LEVELS ARE APPROXIMATELY AS SHOWN.
FOR NPN CIRCUITS, REVERSE ALL POLARITIES.
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84
2N5684 2N5686
1.0
r(t), EFFECTIVE TRANSIENT THERMAL 0.7 D = 0.5
0.3 0.2
0.2
0.1 JC(t) = r(t) JC P(pk)
0.1 JC = 0.584C/W MAX

0.05
0.07
0.05
READ TIME AT t1 t2
0.03 0.01 TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
0.02 SINGLE PULSE
0.01
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000
t, TIME (ms)
100 100 s There are two limitations on the power handling ability of
500 s
1.0 ms
20 dc 5.0 ms breakdown. Safe operating area curves indicate IC VCE
10 TJ = 200C
2.0 THERMALLY LIMITED @ TC = 25C
(SINGLE PULSE) The data of Figure 5 is based on TJ(pk) = 200C; TC is
1.0 CURVES APPLY BELOW variable depending on conditions. Second breakdown pulse
0.5 RATED VCEO limits are valid for duty cycles to 10% provided TJ(pk)
0.2
200C. TJ(pk) may be calculated from the data in
2N5684, 2N5686 Figure 4. At high case temperatures, thermal limitations will
0.1 reduce the power that can be handled to values less than the
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) limitations imposed by second breakdown.
4.0 5000
3.0 2N5684 (PNP)
2N5686 (NPN) TJ = 25C TJ = 25C
IB1 = IB2
2.0 IC/IB = 10 3000
C, CAPACITANCE (pF)
ts VCE = 30 V
t, TIME (s)
2000

1.0 Cib
0.8
0.6 Cob
Cib
1000
0.4 tf
0.3 700 2N5684 (PNP) Cob
2N5686 (NPN)
0.2 500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
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85
2N5684 2N5686
PNP NPN
2N5684 2N5686
500 500
TJ = +150C TJ = +150C VCE = 2.0 V
300 VCE = 2.0 V 300
VCE = 10 V VCE = 10 V
200 200
+25C +25C

100 100
70 70
-55C
50 50 -55C
30 30
20 20
10 10
7.0 7.0
5.0 5.0
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
2.0 2.0

TJ = 25C TJ = 25C
1.6 1.6 IC = 10 A 25 A 40 A
IC = 10 A 25 A 40 A
1.2 1.2
0.8 0.8
0.4 0.4
0 0
0.1 0.2 0.5 1.0 2.0 3.0 5.0 10 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10
IB, BASE CURRENT (AMP) IB, BASE CURRENT (AMP)
2.5 2.0
TJ = 25C TJ = 25C
2.0 1.6
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
1.5 1.2
1.0 VBE(sat) @ IC/IB = 10 0.8 VBE(sat) @ IC/IB = 10
VBE @ VCE = 2.0 V VBE @ VCE = 2.0 V

0.5 0.4
VCE(sat) @ IC/IB = 10 VCE(sat) @ IC/IB = 10

0 0
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 10 20 30 50
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86
ON Semiconductor
PNP
Complementary Silicon 2N5883
High-Power Transistors
. . . designed for generalpurpose power amplifier and switching
2N5884*
applications. NPN
Low CollectorEmitter Saturation Voltage 2N5885
2N5886*
VCE(sat) = 1.0 Vdc, (max) at IC = 15 Adc
Low Leakage Current
ICEX = 1.0 mAdc (max) at Rated Voltage

Excellent DC Current Gain
hFE = 20 (min) at IC = 10 Adc 25 AMPERE
High Current Gain Bandwidth Product COMPLEMENTARY
f = 4.0 MHz (min) at IC = 1.0 Adc SILICON

POWER TRANSISTORS
MAXIMUM RATINGS (1)

6080 VOLTS

2N5883 2N5884 200 WATTS





Peak
IC 25
50
Adc

CASE 107

Total Device Dissipation @ TC = 25C PD 200 Watts TO204AA
(TO3)

C

Temperature Range


(1) Indicates JEDEC registered data. Units and conditions differ on some parameters and
reregistration reflecting these changes has been requested. All above values most or
JC 0.875 C/W
exceed present JEDEC registered data.

200
175
150
125
100
75
50
25
0
0 25 50 75 100 125 150 175 200

March, 2001 Rev. 9 2N5883/D
2N5883 2N5884 2N5885 2N5886


CollectorEmitter Sustaining Voltage (2) 2N5883, 2N5885 VCEO(sus) 60 Vdc
(IC = 200 mAdc, IB = 0) 2N5884, 2N5886 80

Collector Cutoff Current (VCE = 30 Vdc, IB = 0)

Collector Cutoff Current (VCE = 40 Vdc, IB = 0)
2N5883, 2N5885
2N5984, 2N5886
ICEO

2.0
2.0
mAdc


(VCE = 60 Vdc, VBE(off) = 1.5 Vdc) 2N5883, 2N5885 1.0
(VCE = 80 Vdc, VBE(off) = 1.5 Vdc) 2N5884, 2N5886 1.0

(VCE = 60 Vdc, VBE(off) = 1.5 Vdc, TC = 150C) 2N5883, 2N5885 10
(VCE = 80 Vdc, VBE(off) = 1.5 Vdc, TC = 150C) 2N5884, 2N5886

10

(VCB = 60 Vdc, IE = 0) 2N5883, 2N5885 1.0

(VCB = 80 Vdc, IE = 0) 2N5884, 2N5886 1.0

Emitter Cutoff Current (VEB = 5.0 Vdc, IC = 0) IEBO 1.0 mAdc

ON CHARACTERISTICS

DC Current Gain (2) (IC = 3.0 Adc, VCE = 4.0 Vdc) hFE 35
DC Current Gain (2) (IC = 10 Adc, VCE = 4.0 Vdc) 20 100

DC Current Gain (2) (IC = 25 Adc, VCE = 4.0 Vdc) 4.0

CollectorEmitter Saturation Voltage (2) (IC = 15 Adc, IB = 1.5 Adc) VCE(sat) 1.0 Vdc
CollectorEmitter Saturation Voltage (2) (IC = 25 Adc, IB = 6.25 Adc) 4.0

BaseEmitter Saturation Voltage (2) (IC = 25 Adc, IB = 6.25 Adc)

BaseEmitter On Voltage (2) (IC = 10 Adc, VCE = 4.0 Vdc)
VBE(sat)
VBE(on)

2.5
1.5
Vdc
Vdc

CurrentGain Bandwidth Product (3) (IC = 1.0 Adc, VCE = 10 Vdc, ftest = 1.0 MHz) fT 4.0 MHz

Output Capacitance 2N5883, 2N5884 Cob 1000 pF
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz) 2N5885, 2N5886 500

SmallSignal Current Gain (IC = 3.0 Adc, VCE = 4.0 Vdc, ftest = 1.0 kHz)
hfe 20

Rise Time tr 0.7 s
(VCC = 30 Vdc,
Vdc IC = 10 Adc,
Adc

Storage Time ts 1.0 s
IB1 = IB2 = 1.0
1 0 Adc)
Fall Time tf 0.8 s
(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. (3) fT = |hfe| ftest.
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88
2N5883 2N5884 2N5885 2N5886
VCC -30 V
TURNON TIME
RL 3.0
+2.0 V
10 TO SCOPE
0
tr 20 ns 2.0
RB
TJ = 25C
tr -11V 1.0 IC/IB = 10
20ns VCC = 30 V
0.7
10 to 100 s VBE(off) = 2 V
0.5
DUTY CYCLE 2.0% VCC -30 V
t, TIME (s)
0.3 tr

TURNOFF TIME 0.2
RL 3.0
+9.0V 2N5883, 2N5884 (PNP)
10 TO SCOPE 0.1 2N5885, 2N5886 (NPN)
0 td
tr 20 ns 0.07
RB 0.05
-11V
tr 20ns 0.03
10 to 100 s VBB +7.0 V 0.02
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
DUTY CYCLE 2.0%
IC, COLLECTOR CURRENT (AMPERES)
FOR CURVES OF FIGURES 3 & 6, RB & RL ARE VARIED.
INPUT LEVELS ARE APPROXIMATELY AS SHOWN. Figure 3. TurnOn Time
FOR NPN, REVERSE ALL POLARITIES.
Figure 2. Switching Time Equivalent Test Circuits
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89
2N5883 2N5884 2N5885 2N5886
1.0
D = 0.5
0.2
0.2
0.1
0.1 0.05 JC = 0.875C/W MAX
0.02 SINGLE PULSE
0.01
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000
t, TIME (ms)
100
IC, COLLECTOR CURRENT (AMPERES)
50 500 s
1ms
20 breakdown. Safe operating area curves indicate IC VCE
dc 5ms
10 limits of the transistor that must be observed for reliable
5.0 TJ = 200C operation; i.e., the transistor must not be subjected to greater
SECOND BREAKDOWN LIMITED dissipation than the curves indicate.
2.0 BONDING WIRE LIMITED The data of Figure 5 is based on TJ(pk) = 200C; TC is
1.0 THERMAL LIMITATION @ TC = 25C variable depending on conditions. Second breakdown pulse
(SINGLE PULSE)
0.5 limits are valid for duty cycles to 10% provided TJ(pk)
0.2 2N5883, 2N5885 Figure 4. At high case temperatures, thermal limitations will
2N5884, 2N5886
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
limitations imposed by second breakdown.
10 3000
7.0 2N5883, 2N5884 (PNP) TJ = 25C TJ = 25C
5.0 2N5885, 2N5886 (NPN) VCC = 30 V
2000
IC/IB = 10
3.0 Cob
C, CAPACITANCE (pF)
ts IB1 = IB2
2.0 Cib
t, TIME (s)

ts
1.0 1000
0.7 Cib
0.5 700
tf
0.3 500
0.2 tf 2N5883, 2N5884 (PNP) Cob
2N5885, 2N5886 (NPN)
0.1 300
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
IC, COLLECTOR CURRENT (AMPERES) VR, REVERSE VOLTAGE (VOLTS)
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90
2N5883 2N5884 2N5885 2N5886
PNP DEVICES NPN DEVICES

2N5883 and 2N5884 2N5885 and 2N5886
1000 1000
700 700 VCE = 4.0 V
500 TJ = 150C VCE = 4.0 V 500
TJ = 150C
300 300

25C
200 200
-55C
100 100 25C
70 70
50 50
30 30 -55C
20 20
10 10
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
IC, COLLECTOR CURRENT (AMPERES) IC, COLLECTOR CURRENT (AMPERES)
2.0 2.0
1.6 1.6
IC = 2.0 A 5.0 A 10 A 20 A IC = 2.0 A 5.0 A 10 A 20 A
1.2 1.2
0.8 0.8
0.4 0.4
0 0
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
IB, BASE CURRENT (AMPERES) IC, COLLECTOR CURRENT (AMPERES)
2.0 2.0
TJ = 25C TJ = 25C
1.6 1.6
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
1.2 1.2
VBE @ VCE = 4 V VBE @ VCE = 4 V

0.4 0.4

0 0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
IC, COLLECTOR CURRENT (AMPERES) IC, COLLECTOR CURRENT (AMPERES)
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91
ON Semiconductor
PNP
Plastic Darlington 2N6035
Transistors NPN
. . . designed for generalpurpose amplifier and lowspeed 2N6038
switching applications.
High DC Current Gain 2N6039 *
hFE = 2000 (Typ) @ IC = 2.0 Adc
CollectorEmitter Sustaining Voltage @ 100 mAdc
VCEO(sus) = 60 Vdc (Min) 2N6035, 2N6038 = 80 Vdc DARLINGTON

(Min) 2N6036, 2N6039 4AMPERE
Forward Biased Second Breakdown Current Capability COMPLEMENTARY
IS/b = 1.5 Adc @ 25 Vdc SILICON
POWER TRANSISTORS
Monolithic Construction with BuiltIn BaseEmitter Resistors to 60, 80 VOLTS
LimitELeakage Multiplication 40 WATTS
SpaceSaving High PerformancetoCost Ratio TO225AA Plastic
Package
MAXIMUM RATINGS (1)

2N6035 2N6036


VCEO
VCB
60
60
80
80
Vdc
Vdc


Peak 8.0 CASE 7709

TO225AA TYPE
Base Current IB 100 mAdc


Total Power Dissipation @ TA = 25C PD 1.5 Watts

Derate above 25C

Operating and Storage Junction TJ, Tstg
0.012
65 to +150 C
Temperature Range



Thermal Resistance, Junction to Ambient
JC
JA
3.12
83.3
C/W
C/W

March, 2001 Rev. 9 2N6035/D
2N6035 2N6036 2N6038 2N6039
TA TC
4.0 40

3.0 30
TC
2.0 20
1.0 10
TA
0 0
0 20 40 60 80 100 120 140 160
T, TEMPERATURE (C)
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93
2N6035 2N6036 2N6038 2N6039

OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage VCEO(sus) Vdc

(IC = 100 mAdc, IB = 0) 2N6035, 2N6038 60
2N6036, 2N6039 80

CollectorCutoff Current

(VCE = 60 Vdc, IB = 0)

2N6035, 2N6038
ICEO
100
A

(VCE = 80 Vdc, IB = 0) 2N6036, 2N6039 100

CollectorCutoff Current ICEX A

(VCE = 60 Vdc, VBE(off) = 1.5 Vdc) 2N6035, 2N6038 100



CollectorCutoff Current ICBO mAdc
(VCB = 60 Vdc, IE = 0) 2N6035, 2N6038

0.5
(VCB = 80 Vdc, IE = 0) 2N6036, 2N6039 0.5

EmitterCutoff Current (VBE = 5.0 Vdc, IC = 0)
ON CHARACTERISTICS
IEBO 2.0 mAdc
DC Current Gain

(IC = 0.5 Adc, VCE = 3.0 Vdc)
hFE
500

(IC = 2.0 Adc, VCE = 3.0 Vdc) 750 15,000
(IC = 4.0 Adc, VCE = 3.0 Vdc)

100

CollectorEmitter Saturation Voltage VCE(sat) Vdc
(IC = 2.0 Adc, IB = 8.0 mAdc) 2.0

(IC = 4.0 Adc, IB = 40 mAdc) 3.0

BaseEmitter Saturation Voltage (IC = 4.0 Adc, IB = 40 mAdc)
VBE(sat) 4.0 Vdc

BaseEmitter On Voltage (IC = 2.0 Adc, VCE = 3.0 Vdc)
VBE(on) 2.8 Vdc

SmallSignal CurrentGain (IC = 0.75 Adc, VCE = 10 Vdc, f = 1.0 MHz) |hfe| 25

Output Capacitance Cob pF
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) 2N6035, 2N6036 200

2N6038, 2N6039 100
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94
2N6035 2N6036 2N6038 2N6039
4.0
VCC VCC = 30 V IB1 = IB2
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS -30 V ts IC/IB = 250 TJ = 25C
D1 MUST BE FAST RECOVERY TYPE, eg:
RC
MSD6100 USED BELOW IB 100 mA SCOPE
TUT
t, TIME (s)
V2 RB tf

approx 1.0
+8.0 V 0.8
D1 8.0 k
0
51 60 tr
0.6
V1
approx +4.0 V 0.4
-12 V 25 s td @ VBE(off) = 0
for td and tr, D1 is disconnected
and V2 = 0, RB and RC are varied PNP
tr, tf 10 ns to obtain desired test currents. NPN
For NPN test circuit, reverse diode, 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
polarities and input pulses.
Figure 2. Switching Times Test Circuit Figure 3. Switching Times
1.0
0.7
r(t), TRANSIENT THERMAL RESISTANCE,
D = 0.5
0.5
0.3 0.2
0.2
NORMALIZED
0.1
0.1 0.05
JC = 3.12C/W MAX
0.02
0.01 READ TIME AT t1
0.03 t2
SINGLE PULSE TJ(pk) - TC = P(pk) JC(t)
0.02 DUTY CYCLE, D = t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)
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95
2N6035 2N6036 2N6038 2N6039
ACTIVEREGION SAFEOPERATING AREA

1.0 1.0
7.0 7.0
100 s 100 s
5.0 5.0ms 1.0ms 5.0 5.0ms

1.0ms
3.0 dc 3.0 dc
2.0 2.0
TJ = 150C TJ = 150C
1.0 BONDING WIRE LIMITED 1.0 BONDING WIRE LIMITED
0.7 THERMALLY LIMITED 0.7 THERMALLY LIMITED
0.5 0.5
@ TC = 25C (SINGLE PULSE) @ TC = 25C (SINGLE PULSE)
0.3 SECOND BREAKDOWN LIMITED 0.3 SECOND BREAKDOWN LIMITED
0.2 0.2
2N6036 2N6039
2N6035 2N6038
0.1 0.1
5.0 7.0 10 20 30 50 70 100 5.0 7.0 10 20 30 50 70 100
Figure 5. 2N6035, 2N6036 Figure 6. 2N6038, 2N6039
There are two limitations on the power handling ability of 200

breakdown. Safe operating area curves indicate IC VCE TC = 25C
100
C, CAPACITANCE (pF)
operation; i.e., the transistor must not be subjected to greater 70

50
The data of Figures 5 and 6 is based on TJ(pk) = 150C; Cob
TC is variable depending on conditions. Second breakdown
30 Cib
pulse limits are valid for duty cycles to 10% provided TJ(pk)
< 150C. TJ(pk) may be calculated from the data in Figure 4. 20
At high case temperatures, thermal limitations will reduce PNP
the power that can be handled to values less than the NPN
limitations imposed by second breakdown. 10
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 6.0 10 20 40
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitance
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96
2N6035 2N6036 2N6038 2N6039
PNP NPN
2N6035, 2N6036 2N6038, 2N6039
6.0 k 6.0 k
TC = 125C VCE = 3.0 V TJ = 125C VCE = 3.0 V
4.0 k 4.0 k
3.0 k 3.0 k

25C 25C
2.0 k 2.0 k
-55C -55C
1.0 k 1.0 k
800 800
600 600
400 400
300 300
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
3.4 3.4

3.0 3.0 IC =
IC = 0.5 A
2.6 0.5 A 2.6 1.0 A 2.0 A 4.0 A
1.0 A 2.0 A 4.0 A
2.2 2.2
1.8 1.8
1.4 1.4
1.0 1.0
0.6 0.6
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50
100 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
2.2 2.2
TJ = 25C TJ = 25C
1.8 1.8
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
VBE(sat) @ IC/IB = 250 VBE(sat) @ IC/IB = 250

1.4 VBE @ VCE = 3.0 V 1.4 VBE @ VCE = 3.0 V
1.0 1.0
0.6 0.6
0.2 0.2
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
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97
ON Semiconductor
PNP
Plastic Medium-Power 2N6040
Complementary Silicon 2N6042
Transistors
. . . designed for generalpurpose amplifier and lowspeed 2N6043 *
NPN
2N6045*
High DC Current Gain
hFE = 2500 (Typ) @ IC = 4.0 Adc
CollectorEmitter Sustaining Voltage @ 100 mAdc *ON Semiconductor Preferred Device
VCEO(sus) = 60 Vdc (Min) 2N6040, 2N6043

= 100 Vdc (Min) 2N6042, 2N6045 DARLINGTON
Low CollectorEmitter Saturation Voltage 8 AMPERE
COMPLEMENTARY
VCE(sat) = 2.0 Vdc (Max) @ IC = 4.0 Adc 2N6043,44 SILICON
= 2.0 Vdc (Max) @ IC = 3.0 Adc 2N6042, 2N6045 POWER TRANSISTORS

Monolithic Construction with BuiltIn BaseEmitter Shunt Resistors 60100 VOLTS

MAXIMUM RATINGS (1)

2N6040 2N6042
75 WATTS





Peak 16



Operating and Storage Junction,

Temperature Range

CASE 221A09
TO220AB



JC
JA
1.67
57
C/W
C/W
TA TC
4.0 80
3.0 60
TC
2.0 40
TA
1.0 20
0 0
0 20 40 60 80 100 120 140 160
T, TEMPERATURE (C)

May, 2001 Rev. 4 2N6040/D
2N6040 2N6042 2N6043 2N6045

OFF CHARACTERISTICS


(IC = 100 mAdc, IB = 0) 2N6040, 2N6043 60

100
2N6042, 2N6045

Collector Cutoff Current ICEO A

(VCE = 60 Vdc, IB = 0) 2N6040, 2N6043 20
(VCE = 100 Vdc, IB = 0) 2N6042, 2N6045 20


(VCE = 60 Vdc, VBE(off) = 1.5 Vdc) 2N6040, 2N6043
ICEX
20
A




Collector Cutoff Current ICBO A
(VCB = 60 Vdc, IE = 0) 2N6040, 2N6043 20

(VCB = 100 Vdc, IE = 0)

2N6042, 2N6045 20

Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0) IEBO 2.0 mAdc

ON CHARACTERISTICS

DC Current Gain hFE
(IC = 4.0 Adc, VCE = 4.0 Vdc) 2N6040, 2N6043, 1000 20.000

(IC = 3.0 Adc, VCE = 4.0 Vdc) 2N6042, 2N6045 1000 20,000

(IC = 8.0 Adc, VCE = 4.0 Vdc) All Types 100

(IC = 4.0 Adc, IB = 16 mAdc) 2N6040, 2N6043, 2.0

(IC = 3.0 Adc, IB = 12 mAdc) 2N6042, 2N6045 2.0

(IC = 8.0 Adc, IB = 80 Adc) All Types 4.0

BaseEmitter Saturation Voltage (IC = 8.0 Adc, IB = 80 mAdc) VBE(sat) 4.5 Vdc
BaseEmitter On Voltage (IC = 4.0 Adc, VCE = 4.0 Vdc) VBE(on) 2.8 Vdc

Small Signal Current Gain (IC = 3.0 Adc, VCE = 4.0 Vdc, f = 1.0 MHz) |hfe| 4.0
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
2N6040/2N6042
2N6043/2N6045
Cob

300
200
pF

SmallSignal Current Gain (IC = 3.0 Adc, VCE = 4.0 Vdc, f = 1.0 kHz) hfe 300
5.0
3.0 ts
VCC
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS -30 V 2.0
1N5825 USED ABOVE IB 100 mA tf
RC 1.0
t, TIME (s)
TUT 0.7

V2 RB 0.5
approx
+8.0 V 0.3
D1 tr
0
51 8.0 k 120 0.2 VCC = 30 V
IC/IB = 250
V1 IB1 = IB2
approx +4.0 V 0.1 TJ = 25C
-12 V 25 s 0.07 PNP td @ VBE(off) = 0 V
for td and tr, D1 is disconnected
NPN
tr, tf 10 ns
and V2 = 0 0.05
For NPN test circuit reverse all polarities and D1. 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
DUTY CYCLE = 1.0%
Figure 2. Switching Times Equivalent Circuit Figure 3. Switching Times
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99
2N6040 2N6042 2N6043 2N6045
1.0
0.7
THERMAL RESISTANCE (NORMALIZED) D = 0.5
0.5
0.3 0.2
0.2
0.1 JC(t) = r(t) JC P(pk)
0.1 JC = 1.67C/W
0.07
0.05
READ TIME AT t1 t2
SINGLE PULSE
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000

100 s

500 s limits of the transistor that must be observed for reliable
1.0ms
TJ = 150C 5.0ms
1.0 BONDING WIRE LIMITED
0.5 THERMALLY LIMITED @ TC = 25C The data of Figure 5 is based on TJ(pk) = 150C; TC is
(SINGLE PULSE) variable depending on conditions. Second breakdown pulse
0.2 SECOND BREAKDOWN LIMITED limits are valid for duty cycles to 10% provided TJ(pk)
0.1 < 150C. TJ(pk) may be calculated from the data in
2N6040, 2N6043
0.05 2N6045
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
10,000 300
5000 TJ = 25C
hfe, SMALL-SIGNAL CURRENT GAIN
3000 200
2000
C, CAPACITANCE (pF)
1000
Cob
500 TC = 25C
300 100
VCE = 4.0 Vdc
200 IC = 3.0 Adc
70 Cib
100
50 50
PNP
30 PNP
20 NPN
NPN
10 30
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
f, FREQUENCY (kHz) VR, REVERSE VOLTAGE (VOLTS)
Figure 6. SmallSignal Current Gain Figure 7. Capacitance
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100
2N6040 2N6042 2N6043 2N6045
PNP NPN
2N6040, 2N6042 2N6043, 2N6045
20,000 20,000
VCE = 4.0 V VCE = 4.0 V
10,000 10,000
7000 7000

5000 5000 TJ = 150C
TJ = 150C
3000 3000
2000 25C 2000
25C
1000 1000
700 700
500 -55C 500 -55C
300 300
200 200
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
3.0 3.0

2.6 2.6
IC = 2.0 A 4.0 A 6.0 A IC = 2.0 A 4.0 A 6.0 A
2.2 2.2
1.8 1.8
1.4 1.4
1.0 1.0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
3.0 3.0
TJ = 25C TJ = 25C
2.5 2.5
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0
1.5 VBE @ VCE = 4.0 V 1.5 VBE(sat) @ IC/IB = 250
VBE(sat) @ IC/IB = 250 VBE @ VCE = 4.0 V

1.0 1.0
0.5 0.5
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.010 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
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101
ON Semiconductor
Darlington Complementary PNP

Silicon Power Transistors 2N6052*
NPN
. . . designed for generalpurpose amplifier and low frequency
2N6058
High DC Current Gain 2N6059*
hFE = 3500 (Typ) @ IC = 5.0 Adc
CollectorEmitter Sustaining Voltage @ 100 mA
VCEO(sus) = 80 Vdc (Min) 2N6058 *ON Semiconductor Preferred Device
100 Vdc (Min) 2N6052, 2N6059
Monolithic Construction with BuiltIn BaseEmitter Shunt Resistors
DARLINGTON

MAXIMUM RATINGS (1) 12 AMPERE
COMPLEMENTARY

2N6052
Rating Symbol 2N6058 2N6059 Unit SILICON

POWER TRANSISTORS
80100 VOLTS


EmitterBase voltage
VCB
VEB
80
5.0
100 Vdc
Vdc
150 WATTS


Peak
IC 12
20
Adc


Total Device Dissipation PD 150 Watts

@TC = 25C

CASE 107
Operating and Storage Junction TJ, Tstg 65 to +200C C TO204AA

Temperature Range (TO3)

Characteristic Symbol Rating Unit

160
RJC 1.17 C/W
140
120
100
80
60
40
20
0
0 25 50 75 100 125 150 175 200


March, 2001 Rev. 2 2N6052/D
2N6052

OFF CHARACTERISTICS


(IC = 100 mAdc, IB = 0) 2N6058 80
2N6052, 2N6059

100

(VCE = 40 Vdc, IB = 0) 2N6058 1.0

(VCE = 50 Vdc, IB = 0) 2N6052, 2N6059 1.0


(VCE = Rated VCEO, VBE(off) = 1.5 Vdc)
(VCE = Rated VCEO, VBE(off) = 1.5 Vdc, TC = 150C)
ICEX
0.5
5.0
mAdc


(VBE = 5.0 Vdc, IC = 0)

IEBO 2.0 mAdc
DC Current Gain


hFE

(IC = 6.0 Adc, VCE = 3.0 Vdc) 750 18,000
(IC = 12 Adc, VCE = 3.0 Vdc)

100

(IC = 6.0 Adc, IB = 24 mAdc) 2.0

(IC = 12 Adc, IB = 120 mAdc) 3.0


(IC = 12 Adc, IB = 120 mAdc)

BaseEmitter On Voltage VBE(on) 2.8 Vdc
(IC = 6.0 Adc, VCE = 3.0 Vdc)


Magnitude of Common Emitter SmallSignal Short Circuit Forward |hfe| 4.0 MHz

Current Transfer Ratio

(IC = 5.0 Adc, VCE = 3.0 Vdc, f = 1.0 MHz)

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) 2N6058/2N6059 300


hfe 300
(2) Pulse test: Pulse Width = 300 s, Duty Cycle = 2.0%.
VCC 10
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS -30 V
D1 MUST BE FAST RECOVERY TYPE, eg: 2N6052
5.0 2N6059
1N5825 USED ABOVE IB 100 mA RC
MSD6100 USED BELOW IB 100 mA SCOPE ts
TUT
V2 RB 2.0
tf
t, TIME (s)
approx

+8.0 V
D1 1.0
51 5.0 k 50
0
tr
V1 0.5
approx +4.0 V
td @ VBE(off) = 0 VCC = 30 V
-8.0 V 25 s for td and tr, D1 is disconnected IC/IB = 250
and V2 = 0 0.2 IB1 = IB2
tr, tf 10 ns
DUTY CYCLE = 1.0% TJ = 25C
0.1
0.2 0.5 1.0 3.0 5.0 10 20
For NPN test circuit reverse diode and voltage polarities.
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103
2N6052
1.0
0.7
D = 0.5
0.5
0.3 0.2
0.2
0.1 P(pk)
RJC(t) = r(t) RJC
0.1 0.05 RJC = 1.17C/W MAX
0.02
READ TIME AT t1 t2
0.02 SINGLE
PULSE
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)
ACTIVEREGION SAFE OPERATING AREA

50 50
0.1 ms 0.1 ms
20 20

10 10
5.0 0.5 ms 5.0 0.5 ms
1.0 ms 1.0 ms
2.0 2.0 5.0 ms
5.0 ms
1.0 TJ = 200C 1.0 TJ = 200C
0.5 SECOND BREAKDOWN LIM 0.5
ITED SECOND BREAKDOWN LIMITED
0.2 d 0.2 BONDING WIRE LIMITED d
THERMAL LIMITATION
0.1 @TC = 25C (SINGLE PULSE) c 0.1 THERMAL LIMITATION c
@TC = 25C (SINGLE PULSE)
0.05 0.05
10 20 30 50 70 100 10 20 30 50 70 100
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR-EMITTER VOLTAGE
(VOLTS)
Figure 5. 2N6058
Figure 6. 2N6052, 2N6059
There are two limitations on the power handling ability of pulse limits are valid for duty cycles to 10% provided TJ(pk)
a transistor: average junction temperature and second 200C; TJ(pk) may be calculated from the data in Figure
breakdown. Safe operating area curves indicate IC VCE 4. At high case temperatures, thermal limitations will reduce
limits of the transistor that must be observed for reliable the power that can be handled to values less than the
operation; i.e., the transistor must not be subjected to greater limitations imposed by second breakdown.
The data of Figures 5, 6, and 7 is based on TJ(pk) = 200C;
TC is variable depending on conditions. Second breakdown
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104
2N6052
3000 500
2000 TC = 25C TJ = 25C
hfe, SMALL-SIGNAL CURRENT GAIN
VCE = 3.0 V
1000 IC = 5.0 A 300
C, CAPACITANCE (pF)
500 200 Cib
200 Cob
100
100
2N6052
2N6058/2N6059 70 2N6052
50 2N6058/2N6059
30 50
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
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105
2N6052
PNP NPN
2N6052 2N6058, 2N6059
20,000 40,000
VCE = 3.0 V VCE = 3.0 V
20,000 TJ = 150C
10,000
TJ = 150C

5000 10,000
3000 6,000 25C

25C
2000 4,000
1000 -55C 2,000
500 1,000 -55C

300 600
200 400
0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20
3.0 3.0
2.6 2.6 IC = 3.0 A 6.0 A 9.0 A 12 A

IC = 3.0 A 6.0 A 9.0 A 12 A
2.2 2.2
1.8 1.8
1.4 1.4
1.0 1.0
0.5 1.0 2.0 3.0 5.0 10 20 30 50 0.5 1.0 2.0 3.0 5.0 10 20 30 50
3.0 3.0
TJ = 25C TJ = 25C
2.5 2.5
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0

1.0 1.0

0.5 0.5
0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20
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106
ON Semiconductor
PNP
Complementary Silicon Plastic 2N6107
Power Transistors 2N6109 *
. . . designed for use in generalpurpose amplifier and switching
applications. 2N6111
DC Current Gain Specified to 7.0 Amperes NPN
hFE = 30150 @ IC 2N6288
= 3.0 Adc 2N6111, 2N6288
= 2.3 (Min) @ IC = 7.0 Adc All Devices

2N6292*
VCEO(sus) = 30 Vdc (Min) 2N6111, 2N6288 *ON Semiconductor Preferred Device
= 50 Vdc (Min) 2N6109

= 70 Vdc (Min) 2N6107, 2N6292 7 AMPERE
POWER TRANSISTORS
High Current Gain Bandwidth Product COMPLEMENTARY
fT = 4.0 MHz (Min) @ IC = 500 mAdc 2N6288, 90, 92 SILICON
= 10 MHz (Min) @ IC = 500 mAdc 2N6107, 09, 11 305070 VOLTS
TO220AB Compact Package 40 WATTS

*MAXIMUM RATINGS

2N6111 2N6107
Rating Symbol 2N6288 2N6109 2N6292 Unit


VCEO
VCB
30
40
50
60
70
80
Vdc
Vdc


Peak 10

Base Current

IB
PD
3.0
40
Adc
Watts CASE 221A09

Derate above 25C 0.32 W/C TO220AB

Temperature Range


RJC 3.125 C/W

March, 2001 Rev. 4 2N6107/D
2N6107 2N6109 2N6111 2N6288 2N6292
40

30
20
10
0
0 20 40 60 80 100 120 140 160
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108
2N6107 2N6109 2N6111 2N6288 2N6292

OFF CHARACTERISTICS


(IC = 100 mAdc, IB = 0) 2N6111, 2N6288 30
2N6109

50
2N6107, 2N6292 70


(VCE = 20 Vdc, IB = 0)

2N6111, 2N6288
ICEO
1.0
mAdc

(VCE = 40 Vdc, IB = 0) 2N6109 1.0
(VCE = 60 Vdc, IB = 0) 2N6107, 2N6292 1.0


(VCE = 40 Vdc, VEB(off) = 1.5 Vdc) 2N6111, 2N6288
ICEX
100
Adc

(VCE = 60 Vdc, VEB(off) = 1.5 Vdc) 2N6109 100
(VCE = 80 Vdc, VEB(off) = 1.5 Vdc) 2N6107, 2N6292 100

(VCE = 30 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 2N6111, 2N6288 2.0 mAdc

(VCE = 70 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 2N6107, 2N6292 2.0


(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc
DC Current Gain


hFE

(IC = 2.0 Adc, VCE = 4.0 Vdc) 2N6107, 2N6292 30 150
(IC = 2.5 Adc, VCE = 4.0 Vdc) 2N6109

30 150
(IC = 3.0 Adc, VCE = 4.0 Vdc) 2N6111, 2N6288 30 150

(IC = 7.0 Adc, VCE = 4.0 Vdc) All Devices 2.3

(IC = 7.0 Adc, IB = 3.0 Adc)

(IC = 7.0 Adc, VCE = 4.0 Vdc)
VBE(on) 3.0 Vdc

Current Gain Bandwidth Product (2) fT MHz

(IC = 500 mAdc, VCE = 4.0 Vdc, ftest = 1.0 MHz) 2N6288, 92 4.0
2N6107, 09, 11

10

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cob 250 pF
SmallSignal Current Gain (IC = 0.5 Adc, VCE = 4.0 Vdc, f = 50 kHz) hfe 20
(2) fT = |hfe| ftest.
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109
2N6107 2N6109 2N6111 2N6288 2N6292
VCC
+30 V 2.0
1.0 TJ = 25C
25 s RC VCC = 30 V
0.7
+11 V SCOPE 0.5 IC/IB = 10
RB
t, TIME (s)
0.3

0
D1 0.2 tr
51
-9.0 V 0.1
tr, tf 10 ns -4 V 0.07 td @ VBE(off) 5.0 V
RB and RC ARE VARIED TO OBTAIN DESIRED CURRENT LEVELS
0.03
0.02
1N5825 USED ABOVE IB 100 mA 0.07 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 7.0
MSD6100 USED BELOW IB 100 mA

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.0
0.7
D = 0.5
0.5
0.3
0.2
0.2
0.1
0.1 P(pk)
ZJC(t) = r(t) RJC
0.07 0.05 RJC = 3.125C/W MAX
0.03 t1
READ TIME AT t1 t2
0.02 0.01 TJ(pk) - TC = P(pk) ZJC(t) DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k
t, TIME (ms)

0.1 ms
7.0 0.5 ms breakdown. Safe operating area curves indicate IC VCE

5.0 limits of the transistor that must be observed for reliable
2.0 0.1 dissipation than the curves indicate.
ms
1.0 CURRENT LIMIT variable depending on conditions. Second breakdown pulse
0.7 SECONDARY
0.5 BREAKDOWN LIMIT 5.0 ms
THERMAL LIMIT 150C. TJ(pk) may be calculated from the data in
0.3 @ TC = 25C (SINGLE PULSE) Figure 4. At high case temperatures, thermal limitations will
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
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110
2N6107 2N6109 2N6111 2N6288 2N6292
5.0 300
3.0 TJ = 25C
2.0 VCC = 30 V 200 TJ = 25C
IC/IB = 10
ts
C, CAPACITANCE (pF)
1.0 IB1 = IB2
Cib
t, TIME (s)
0.7

0.5 100
0.3 tr
70 Cob
0.2
50
0.1
0.07
0.05 30
0.07 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 7.0 0.5 1.0 2.0 3.0 5.0 10 20 30 50
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111
ON Semiconductor
NPN
Darlington Complementary 2N6283
Silicon Power Transistors 2N6284
. . . designed for generalpurpose amplifier and lowfrequency
PNP
switching applications. 2N6286
High DC Current Gain @ IC = 10 Adc
hFE = 2400 (Typ) 2N6284 2N6287
= 4000 (Typ) 2N6287
VCEO(sus) = 100 Vdc (Min) DARLINGTON
Monolithic Construction with BuiltIn BaseEmitter Shunt Resistors 20 AMPERE
COMPLEMENTARY
SILICON
*MAXIMUM RATINGS
POWER TRANSISTORS

Symbo 2N6283 2N6284 100 VOLTS
Rating l 2N6286 2N6287 Unit

160 WATTS


EmitterBase Voltage
VCB
VEB
80
5.0
100 Vdc
Vdc


Peak
IC 20
40
Adc

Base Current

Total Device Dissipation @ TC =
IB
PD
0.5
160
Adc
Watts CASE 107

25C 0.915 W/C TO204AA
Derate above 25C (TO3)


Temperature Range
TJ,Tstg 65 to +200 C
*THERMAL CHARACTERISTICS


RJC 1.09 C/W
160
140
120
100
80
60
40
20
0
0 25 50 75 100 125 150 175 200

May, 2001 Rev. 1 2N6284/D
2N6283 2N6284 2N6286 2N6287

OFF CHARACTERISTICS


(IC = 0.1 Adc, IB = 0) 2N6283, 2N6286 80
2N6284, 2N6287

100

(VCE = 40 Vdc, IB = 0) 1.0

(VCE = 50 Vdc, IB = 0) 1.0


(VCE = Rated VCB, VBE(off) = 1.5 Vdc) 0.5
(VCE = Rated VCB, VBE(off) = 1.5 Vdc, TC = 150C) 5.0


(VBE = 5.0 Vdc, IC = 0)

IEBO 2.0 mAdc
DC Current Gain


hFE

(IC = 10 Adc, VCE = 3.0 Vdc) 750 18,000
(IC = 20 Adc, VCE = 3.0 Vdc) 100


(IC = 10 Adc, IB = 40 mAdc)

VCE(sat)
2.0
Vdc

(IC = 20 Adc, IB = 200 mAdc) 3.0

(IC = 10 Adc, VCE = 3.0 Vdc)

BaseEmitter Saturation Voltage
(IC = 20 Adc, IB = 200 mAdc)
VBE(sat) 4.0 Vdc


Magnitude of Common Emitter SmallSignal ShortCircuit |hfe| 4.0 MHz

Forward Current Transfer Ratio
(IC = 10 Adc, VCE = 3.0 Vdc, f = 1.0 MHz)
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) 2N6283, 2N6284
Cob
400
pF

2N6286, 2N6287 600

SmallSignal Current Gain hfe 300
(IC = 10 Adc, VCE = 3.0 Vdc, f = 1.0 kHz)
(1) Pulse test: Pulse Width = 300 s, Duty Cycle = 2%
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113
2N6283 2N6284 2N6286 2N6287
10
VCC 7.0 ts 2N6284 (NPN)
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS - 30 V 2N6287 (PNP)
5.0
D1 MUST BE FAST RECOVERY TYPE e.g.,
RC
MSD6100 USED BELOW IB 100 mA SCOPE 2.0
TUT
t, TIME (s)
tf tr

V2 RB
1.0
APPROX 0.7
+ 8.0 V D1
51 8.0 k 50 0.5
0
0.3 VCC = 30 Vdc
V1 + 4.0 V I /I = 250
0.2 C B
APPROX 25 s FOR td AND tr, D1 IS DISCONNECTED IB1 = IB2
- 12 V TJ = 25C td @ VBE(off) = 0 V
AND V2 = 0
tr, tf 10 ns 0.1
FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
DUTY CYCLE = 1.0%
1.0
0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
P(pk)
0.1 0.05 RJC(t) = r(t) RJC
0.07 RJC = 1.09C/W MAX
0.02
0.02 TJ(pk) - TC = P(pk) RJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
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114
2N6283 2N6284 2N6286 2N6287

0.1 ms a transistor: average junction temperature and second
IC, COLLECTOR CURRENT (AMP) 20 0.5 ms breakdown. Safe operating area curves indicate IC VCE
10
1.0 ms limits of the transistor that must be observed for reliable
5.0 operation; i.e. the transistor must not be subjected to greater
5.0 ms dissipation than the curves indicate.
2.0 dc
1.0 TJ = 200C variable depending on conditions. Second breakdown pulse
0.5 limits are valid for duty cycles to 10% provided TJ(pk) <
200C. TJ(pk) may be calculated from the data in Figure 4.
BONDING WIRE LIMITED At high case temperatures, thermal limitations will reduce
0.1 THERMAL LIMITATION @ TC = 25C
the power that can be handled to values less than the
SINGLE PULSE
2.0 5.0 10 20 50 100
Figure 5. 2N6284, 2N6287
10,000 1000
5000 TJ = 25C TJ = 25C
hFE, SMALL-SIGNAL CURRENT GAIN
VCE = 3.0 Vdc 700

2000 IC = 10 A
C, CAPACITANCE (PF)
500
1000
500
300 Cib
200
100 Cob
200
50
2N6284 (NPN) 2N6284 (NPN)
20 2N6287 (PNP) 2N6287 (PNP)
10 100
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
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115
2N6283 2N6284 2N6286 2N6287
NPN PNP
2N6284 2N6287
20,000 30,000
VCE = 3.0 V 20,000 VCE = 3.0 V
10,000
TJ = 150C
7000 TJ = 150C 10,000

5000 7000
5000
3000 25C
2000 25C 3000
2000
1000
-55C -55C
700 1000
500 700
300 500
200 300
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
3.0 3.0
VCE , COLLECTOREMITTER VOLTAGE (VOLTS)
VCE , COLLECTOREMITTER VOLTAGE (VOLTS)

TJ = 25C TJ = 25C
2.6 IC = 5.0 A 10 A 15 A 2.6 15 A

IC = 5.0 A 10 A
2.2 2.2
1.8 1.8
1.4 1.4
1.0 1.0
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
3.0 3.0
TJ = 25C TJ = 25C
2.5 2.5
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0

1.5 1.5 VBE(sat) @ IC/IB = 250

1.0 1.0
0.5 0.5
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
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116
2N6283 2N6284 2N6286 2N6287
NPN PNP
2N6284 2N6287
+5.0 +5.0

+4.0 hFE@VCE 3.0V +4.0 hFE@VCE 3.0V
*APPLIES FOR IC/IB *APPLIES FOR IC/IB
+3.0 250 +3.0 250
+2.0 +2.0 25C to 150C

25C to 150C
+1.0 +1.0
-55C to + 25C
0 -55C to + 25C 0
-1.0 *VC for VCE(sat) -1.0 *VC for VCE(sat)
-2.0 -2.0
25C to + 150C 25C to + 150C
-3.0 -3.0 VB for VBE
VB for VBE
-4.0 -55C to + 25C -4.0 -55C to + 25C
-5.0 -5.0
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20
Figure 11. Temperature Coefficients
105 103
VCE = 30 V VCE = 30 V
104 102

TJ = 150C
103 101
TJ = 150C
102 100 100C
100C
101 10-1
REVERSE FORWARD REVERSE FORWARD
100 10-2 25C
25C
10-1 10-3
-0.6 -0.4 -0.2 0 +0.2 +0.4 +0.6 +0.8 +1.0 +1.2 + 1.4 +0.6 +0.4 +0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4
Figure 12. Collector CutOff Region
COLLECTOR COLLECTOR
NPN PNP
2N6284 2N6287
BASE BASE
8.0 k 60 8.0 k 60
EMITTER EMITTER
Figure 13. Darlington Schematic
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117
ON Semiconductor
High-Power NPN Silicon 2N6338

Transistors 2N6341*
. . . designed for use in industrialmilitary power amplifier and
switching circuit applications.
High CollectorEmitter Sustaining Voltage
VCEO(sus) = 100 Vdc (Min) 2N6338
= 150 Vdc (Min) 2N6341 25 AMPERE
High DC Current Gain POWER TRANSISTORS
hFE = 30 120 @ IC = 10 Adc NPN SILICON
= 12 (Min) @ IC = 25 Adc 100, 120, 140, 150 VOLTS
200 WATTS
VCE(sat) = 1.0 Vdc (Max) @ IC = 10 Adc
Fast Switching Times @ IC = 10 Adc
tr = 0.3 ms (Max)
ts = 1.0 ms (Max)
tf = 0.25 ms (Max)

*MAXIMUM RATINGS

Rating Symbol 2N6338 2N6341 Unit CASE 107

TO204AA
(TO3)



Collector Current IC Adc
Continuous 25

Peak 50

Total Device Dissipation PD

@ TC = 25C

Derate above 25C

Operating and Storage Junction TJ, Tstg
200
1.14
65 to +200
Watts
W/C
C

Temperature Range

200
175
150
125
100
75
50
25
0
0 25 50 75 100 125 150 175 200

May, 2001 Rev. 10 2N6338/D
2N6338 2N6341

OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage (1) 2N6338 VCEO(sus) 100 Vdc

(IC = 50 mAdc, IB = 0) 2N6341 150
Adc

Collector Cutoff Current ICEO
(VCE = 50 Vdc, IB = 0) 2N6338 50

(VCE = 75 Vdc, IB = 0) 2N6341 50

Collector Cutoff Current ICEX

(VCE = Rated VCEO, VEB(off) = 1.5 Vdc) 10 Adc
(VCE = Rated VCEO, VEB(off) = 1.5 Vdc, TC = 150C) 1.0 mAdc

Collector Cutoff Current (VCB = Rated VCB, IE = 0)

Emitter Cutoff Current (VBE = 6.0 Vdc, IC = 0)
ICBO
IEBO

10
100
Adc
Adc
DC Current Gain)


hFE

(IC = 0.5 Adc, VCE = 2.0 Vdc) 50
(IC = 10 Adc, VCE = 2.0 Vdc) 30 120

(IC = 25 Adc, VCE = 2.0 Vdc) 12

Collector Emitter Saturation Voltage VCE(sat) Vdc

(IC = 10 Adc, IB = 1.0 Adc) 1.0
(IC = 25 Adc, IB = 2.5 Adc) 1.8


(IC = 10 Adc, IB = 1.0 Adc)
VBE(sat)
1.8
Vdc

(IC = 25 Adc, IB = 2.5 Adc) 2.5
BaseEmitter On Voltage (IC = 10 Adc, VCE = 2.0 Vdc) VBE(on) 1.8 Vdc

CurrentGain Bandwidth Product (2) (IC = 1.0 Adc, VCE = 10 Vdc, ftest = 10 MHz)

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
fT
Cob
40

300
MHz
pF

Rise Time (VCC 80 Vdc, IC = 10Adc, IB1 = 1.0 Adc, VBE(off) = 6.0 Vdc) tr 0.3 s

Storage Time (VCC 80 Vdc, IC = 10 Adc, IB1 = IB2 = 1.0 Adc) ts 1.0 s
Fall Time (VCC 80 Vdc, IC = 10 Adc, IB1 = IB2 = 1.0 Adc) tf 0.25 s
VCC 1000
700
+ 80 V VCC = 80 V
500
RC IC/IB = 10
8.0 OHMS td @ VBE(off) = 6.0 V TJ = 25C
300
10 s RB SCOPE 200
t, TIME (ns)
+ 11 V 10 OHMS
0 100 tr
70
1N4933
- 9.0 V 50
tr, tf 10 ns 30
- 5.0 V
DUTY CYCLE = 1.0%
20
NOTE: For information on Figures 3 and 6, RB and RC were 10

varied to obtain desired test conditions. 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
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119
2N6338 2N6341
1.0

0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1 P(pk)
0.1 JC = r(t) JC
0.05 JC = 0.875C/W MAX
0.07 0.02
t1 PULSE TRAIN SHOWN
0.03 0.01 t2 READ TIME AT t1
0.02 SINGLE PULSE TJ(pk) - TC = P(pk) JC(t)
DUTY CYCLE, D = t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)

200 s
20 breakdown. Safe operating area curves indicate ICVCE

10 1.0 ms limits of the transistor that must be observed for reliable
dc
5.0 5.0 ms operation; i.e., the transistor must not be subjected to greater
2.0 TJ = 200C dissipation than the curves indicate.
1.0 BONDING WIRE LIMITED The data of Figure 5 is based on TJ(pk) = 200C; TC is
0.5 THERMALLY LIMITED @ variable depending on conditions. Second breakdown pulse
0.2 TC = 25C (SINGLE PULSE) limits are valid for duty cycles to 10% provided TJ(pk)
SECOND BREAKDOWN
0.1 200C. TJ(pk) may be calculated from the data in
LIMITED CURVES APPLY 2N6338
0.05 Figure 4. At high case temperatures, thermal limitations will
BELOW RATED VCEO 2N6341
2.0 3.0 5.0 7.0 10 20 30 50 70 100 200
5.0 5000
3.0 VCC = 80 V 3000 TJ = 25C
ts IB1 = IB2 Cib
2.0 2000
IC/IB = 10
C, CAPACITANCE (pF)
TJ = 25C
1.0 1000
t, TIME (s)
0.7 700

0.5 500
0.3 300
0.2 tf 200 Cob
0.1 100
0.07 70
0.05 50
0.3 0.5 0.7 1.0 2.0 3.0 5.0 10 20 30 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
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120
ON Semiconductor
2N6387
Plastic Medium-Power
2N6388*
Silicon Transistors
. . . designed for generalpurpose amplifier and lowspeed
switching applications. DARLINGTON
8 AND 10 AMPERE
High DC Current Gain NPN SILICON
hFE = 2500 (Typ) @ IC POWER TRANSISTORS
= 4.0 Adc 6080 VOLTS
CollectorEmitter Sustaining Voltage @ 100 mAdc 65 WATTS
VCEO(sus) = 60 Vdc (Min) 2N6387
= 80 Vdc (Min) 2N6388
VCE(sat) = 2.0 Vdc (Max) @ IC
= 5.0 Adc 2N6387, 2N6388
TO220AB Compact Package
*MAXIMUM RATINGS


CollectorEmitter Voltage VCEO 60 80 Vdc CASE 221A09
CollectorBase Voltage VCB 60 80 Vdc TO220AB

EmitterBase Voltage

VEB
IC 10
5.0
10
Vdc
Adc

Peak 15 15

Total Power Dissipation PD

@ TC = 25C

Derate above 25C
65
0.52
Watts
W/C

Total Power Dissipation PD
@ TA = 25C 2.0 Watts


Operating and Storage Junction, TJ, Tstg 65 to +150 C
Temperature Range


Characteristics Symbol Max Unit

Thermal Resistance, Junction to Ambient RJA 62.5 C/W

March, 2001 Rev. 9 2N6387/D
2N6387 2N6388
TA TC
4.0 80

3.0 60
TC
2.0 40
TA
1.0 20
0
0 20 40 60 80 100 120 140 160
T, TEMPERATURE (C)
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122
2N6387 2N6388

OFF CHARACTERISTICS


(IC = 200 mAdc, IB = 0) 2N6387 60
2N6388

80

(VCE = 60 Vdc, IB = 0) 2N6387 1.0

(VCE = 80 Vdc, IB = 0) 2N6388 1.0


(VCE 80 Vdc, VEB(off) = 1.5 Vdc)
2N6387
2N6388
ICEX

300
300
Adc

(VCE = 60 Vdc, VEB(off) = 1.5 Vdc, TC = 125C) 2N6387 3.0 mAdc


(VBE = 5.0 Vdc, IC = 0)

DC Current Gain

hFE

(IC = 5.0 Adc, VCE = 3.0 Vdc)

(IC = 1 0 Adc, VCE = 3.0 Vdc)
2N6387, 2N6388
2N6387, 2N6388
1000
100
20,000

(IC = 5.0 Adc, IB = 0.01 Adc) 2N6387, 2N6388

2.0
(IC = 10 Adc, IB = 0.1 Adc) 2N6387, 2N6388 3.0


(IC = 5.0 Adc, VCE = 3.0 Vdc) 2N6387, 2N6388
VBE(on)
2.8
Vdc

(IC = 10 Adc, VCE = 3.0 Vdc) 2N6387, 2N6388 4.5


SmallSignal Current Gain |hfe| 20
(IC = 1.0 Adc, VCE = 5.0 Vdc, ftest = 1.0 MHz)
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)
Cob 200 pF


*Indicates JEDEC Registered Data
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123
2N6387 2N6388
7.0
VCC 5.0
RB AND RC VARIED TO OBTAIN DESIRED CURRENT LEVELS + 30 V
D1 MUST BE FAST RECOVERY TYPES, e.g., 3.0
ts
1N5825 USED ABOVE IB 100 mA RC
MSD6100 USED BELOW IB 100 mA SCOPE tf
TUT
t, TIME (s)
1.0

V1 RB
0.7 tr
APPROX
+ 12 V
51 D1 8.0 k 120
0 0.3 VCC = 30 V
0.2 IC/IB = 250 td
V2 - 4.0 V IB1 = IB2
APPROX 25 s FOR td AND tr, D1 IS DISCONNECTED TJ = 25C
-8V AND V2 = 0 0.1
tr, tf 10 ns 0.07
0.1 0.2 0.5 1.0 2.0 5.0 10
DUTY CYCLE = 1.0%
1.0
0.7
D = 0.5
0.5
0.3
0.2
0.2
(NORMALIZED)
0.1
0.1 P(pk)
ZJC (t) = r(t) RJC
0.07 0.05
RJC = 1.92C/W MAX
0.02
PULSE TRAIN SHOWN
0.03 t1
READ TIME AT t1 t2
0.02 0.01 TJ(pk) - TC = P(pk) ZJC(t)
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k
t, TIME (ms)
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124
2N6387 2N6388

10 s
5.0
dc 50 s limits of the transistor that must be observed for reliable
1 ms
2.0 50 ms operation; i.e., the transistor must not be subjected to greater
1.0 5 ms dissipation than the curves indicate.
TJ = 150C The data of Figure 5 is based on TJ(pk) = 150C; TC is
0.5
0.2 limits are valid for duty cycles to 10% provided TJ(pk)
THERMALLY LIMITED @ TC = 100C
0.1 SECOND BREAKDOWN LIMITED < 150C. TJ(pk) may be calculated from the data in Figure
CURVES APPLY BELOW RATED VCEO 4. At high case temperatures, thermal limitations will reduce
2N6387
2N6388
0.03 limitations imposed by second breakdown
1.0 2.0 4.0 6.0 10 20 40 60 80
Figure 5. Active-Region Safe Operating Area
10,000 300
5000 TJ = 25C
3000 200
2000 C, CAPACITANCE (pF)
1000
500 Cob
300 TC = 25C 100
200 VCE = 4.0 Vdc
IC = 3.0 Adc 70 Cib
100
50 50
30
20
10 30
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
20,000 3.0
VCE = 4.0 V TJ = 25C

10,000
2.6
5000 TJ = 150C IC = 2.0 A 4.0 A 6.0 A
3000 2.2
2000
25C
1.8
1000
-55C
500 1.4
300
200 1.0
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
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125
2N6387 2N6388
3.0 + 5.0

TJ = 25C + 4.0 hFE@VCE 4.0V
*IC/IB
+ 3.0 3
2.5 25C to 150C
V, VOLTAGE (VOLTS)
+ 2.0
2.0 + 1.0
*VC for VCE(sat) -55C to 25C
0
1.5 VBE(sat) @ IC/IB = 250 - 1.0
- 2.0
VBE @ VCE = 4.0 V 25C to 150C
1.0 - 3.0 VB for VBE
-55C to 25C
- 4.0
0.5 - 5.0
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
105
REVERSE FORWARD COLLECTOR
104

VCE = 30 V
103
102 BASE
TJ = 150C
101
8.0 k 120
100 100C
25C
10-1 EMITTER
-0.6 -0.4 -0.2 0 +0.2 +0.4 +0.6 +0.8 +1.0 +1.2 + 1.4
VBE, BASE-EMITTER VOLTAGE (VOLTS)
Figure 12. Collector CutOff Region Figure 13. Darlington Schematic
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126
ON Semiconductor
NPN
Complementary Silicon Plastic 2N6487
Power Transistors
2N6488 *
. . . designed for use in generalpurpose amplifier and switching PNP
applications.
2N6490
DC Current Gain Specified to 15 Amperes
hFE = 20150 @ IC = 5.0 Adc
= 5.0 (Min) @ IC = 15 Adc
2N6491*
CollectorEmitter Sustaining Voltage *ON Semiconductor Preferred Device
VCEO(sus) = 60 Vdc (Min) 2N6487, 2N6490

15 AMPERE
= 80 Vdc (Min) 2N6488, 2N6491
COMPLEMENTARY
High Current Gain Bandwidth Product SILICON
fT = 5.0 MHz (Min) @ IC = 1.0 Adc POWER TRANSISTORS
TO220AB Compact Package 6080 VOLTS
75 WATTS
MAXIMUM RATINGS (1)

2N6487 2N6488



EmitterBase Voltage
VCB
VEB
70
5.0
90 Vdc
Vdc


Base Current

IC
IB
15
5.0
Adc
Adc


Derate above 25C 0.6 W/C CASE 221A09
TO220AB
Total Power Dissipation @ TA = 25C

PD

1.8

Watts


Temperature Range



RJA 70 C/W

March, 2001 Rev. 9 2N6487/D
2N6487 2N6488 2N6490 2N6491
TA TC
4.0 80

3.0 60
TC
2.0 40
TA
1.0 20
0 0
0 20 40 60 80 100 120 140 160
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128
2N6487 2N6488 2N6490 2N6491

OFF CHARACTERISTICS


(IC = 200 mAdc, IB = 0) 2N6487, 2N6490 60
2N6488, 2N6491

80

CollectorEmitter Sustaining Voltage (1) VCEX Vdc
(IC = 200 mAdc, VBE = 1.5 Vdc) 2N6487, 2N6490 70

2N6488, 2N6491 90

(VCE = 30 Vdc, IB = 0)
(VCE = 40 Vdc, IB = 0)


2N6487, 2N6490
2N6488, 2N6491
ICEO

1.0
1.0
mAdc


(VCE = 65 Vdc, VEB(off) = 1.5 Vdc) 2N6487, 2N6490
ICEX
500
Adc

(VCE = 85 Vdc, VEB(off) = 1.5 Vdc) 2N6488, 2N6491 500
(VCE = 60 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 2N6487, 2N6490

5.0
(VCE = 80 Vdc, VEB(off) = 1.5 Vdc, TC = 150C) 2N6488, 2N6491 5.0


(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc
ON CHARACTERISTICS

DC Current Gain hFE
(IC = 5.0 Adc, VCE = 4.0 Vdc)

20 150
(IC = 15 Adc, VCE = 4.0 Vdc) 5.0


(IC = 5.0 Adc, IB = 0.5 Adc)
VCE(sat)
1.3
Vdc

(IC = 15 Adc, IB = 5.0 Adc) 3.5

(IC = 5.0 Adc, VCE = 4.0 Vdc) 1.3

(IC = 15 Adc, VCE = 4.0 Vdc) 3.5



(IC = 1.0 Adc, VCE = 4.0 Vdc, ftest = 1.0 MHz)

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129
2N6487 2N6488 2N6490 2N6491
VCC
+ 30 V 1000
25 s RC 500
+ 10 V tr
SCOPE
RB 200
0
t, TIME (ns)
- 10 V 100
51 D1
tr, tf 10 ns 50 NPN td @ VBE(off) 5.0 V
DUTY CYCLE = 1.0% -4V PNP
RB AND RC VARIED TO OBTAIN DESIRED CURRENT LEVELS. TC = 25C
FOR PNP, REVERSE ALL POLARITIES. 20
VCC = 30 V
IC/IB = 10
D1 MUST BE FAST RECOVERY TYPE, e.g.: 10
1N5825 USED ABOVE IB 100 mA 0.2 0.5 1.0 2.0 5.0 10 20
1.0
0.7
D = 0.5
0.5
0.3
0.2
0.2
(NORMALIZED)
0.1
0.1 ZJC (t) = r(t) RJC P(pk)
0.07 0.05
RJC = 1.67C/W MAX
0.02
PULSE TRAIN SHOWN
0.03 t1
READ TIME AT t1 t2
0.02 0.01 TJ(pk) - TC = P(pk) ZJC(t)
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k
t, TIME (ms)

10 100 s a transistors average junction temperature and second

5.0 500 s limits of the transistor that must be observed for reliable
2.0 1.0 ms dissipation than the curves indicate.
TJ = 150C
1.0 SECOND BREAKDOWN LIMITED 5.0 ms
0.5 THERMALLY LIMITED @ TC = 25C
0.2 2N6487, 2N6490 dc
2N6488, 2N6491 reduce the power that can be handled to values less than the
0.1 limitations imposed by second breakdown
2.0 4.0 10 20 40 60 80
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130
2N6487 2N6488 2N6490 2N6491
5000 1000
700
ts
Cob
C, CAPACITANCE (pF)
1000
300 Cib
t, TIME (ns)
500 tf Cob
200
NPN
200 PNP VCC = 30 V
100 NPN
IC/IB = 10
100 IB1 = IB2 PNP
70
TJ = 25C TJ = 25C
50 50
0.2 0.5 1.0 2.0 5.0 10 20 0.5 1.0 2.0 5.0 10 20 50
Figure 6. TurnOff Time Figure 7. Capacitances
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131
2N6487 2N6488 2N6490 2N6491
NPN PNP
2N6487, 2N6488 2N6490, 2N6491
500 500
TJ = 150C
200 25C 200 TJ = 150C

25C
100 100
-55C -55C
50 50
20 20
VCE = 2.0 V
10 10 VCE = 2.0 V
5.0 5.0
0.2 0.5 1.0 2.0 5.0 10 20 0.2 0.5 1.0 2.0 5.0 10 20
2.0 2.0

1.8 TJ = 25C 1.8 TJ = 25C
1.6 1.6
1.4 1.4
1.2 1.2
1.0 IC = 1.0 A 1.0 IC = 1.0 A 4.0 A 8.0 A
0.8 0.8
4.0 A 8.0 A
0.6 0.6
0.4 0.4
0.2 0.2
0 0
5.0 10 20 50 100 200 500 1000 2000 5000 5.0 10 20 50 100 200 500 1000 2000 5000
2.8 2.8
2.4 TJ = 25C 2.4 TJ = 25C

V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0
1.6 1.6
1.2 1.2
VBE(sat) = IC/IB = 10 VBE(sat) @ IC/IB = 10
0.8 0.8
0.4 0.4
0 0
0.2 0.5 1.0 2.0 5.0 10 20 0.2 0.5 1.0 2.0 5.0 10 20
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132
ON Semiconductor
High Voltage NPN Silicon 2N6497

Power Transistors
. . . designed for high voltage inverters, switching regulators and
lineoperated amplifier applications. Especially well suited for 5 AMPERE
switching power supply applications. POWER TRANSISTORS
NPN SILICON
High CollectorEmitter Sustaining Voltage 250 VOLT
VCEO(sus) = 250 Vdc (Min) 80 WATTS
Excellent DC Current Gain
hFE = 1075 @ IC = 2.5 Adc
Low CollectorEmitter Saturation Voltage @ IC = 2.5 Adc
VCE(sat) = 1.0 Vdc (Max)
MAXIMUM RATINGS (1)




EmitterBase Voltage VEB 6.0 Vdc CASE 221A09

Collector Current Continuous IC 5.0 Adc TO220AB
Peak 10

Base Current

IB
PD
2.0
80
Adc
Watts

Derate above 25C

Operating and Storage Junction TJ,Tstg
0.64
65 to +150
W/C
C

Temperature Range



May, 2001 Rev. 10 2N6497/D
2N6497

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS


(IC = 25 mAdc, IB = 0) 250


(VCE = 350 Vdc, VBE(off) = 1.5 Vdc) 1.0


(VBE = 6.0 Vdc, IC = 0)

IEBO 1.0 mAdc


DC Current Gain hFE
(IC = 2.5 Adc, VCE = 10 Vdc) 10 75

(IC = 5.0 Adc, VCE = 10 Vdc) 3.0


(IC = 2.5 Adc, IB = 500 mAdc)
(IC = 5.0 Adc, IB = 2.0 Adc)
VCE(sat)
1.0
Vdc

5.0

BaseEmitter Saturation Voltage VBE(sat) Vdc
(IC = 2.5 Adc, IB = 500 mAdc) 1.5

(IC = 5.0 Adc, IB = 2.0 Adc) 2.5

(IC = 250 mAdc, VCE = 10 Vdc, f = 1.0 MHz)
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 100 kHz)
Cob 150 pF
Rise Time

(VCC = 125 Vdc, IC = 2.5 Adc, IB1 = 0.5 Adc)
tr 0.4 1.0 s

Storage Time ts 1.4 2.5 s
(VCC = 125 Vdc, IC = 2.5 Adc, VBE = 5.0 Vdc, IB1 = IB2 = 0.5 Adc)
Fall Time

(VCC = 125 Vdc, IC = 2.5 Adc, IB1 = IB2 = 0.5 Adc)
tf 0.45 1.0 s

VCC
+ 125 V 1.0
0.7 VCC = 125 V
25 s RC 50 0.5 IC/IB = 5.0
+ 11 V TJ = 25C
SCOPE 0.3
0 RB 20 0.2
tr
t, TIME (s)

0.1
- 9.0 V D1 0.07
tr, tf 10 ns 0.05
DUTY CYCLE = 1.0% - 5.0 V
0.03 td @ VBE(off) = 5.0 V
RB AND RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
0.02
D1 MUST BE FAST RECOVERY TYPE, e.g.:
MSD6100 USED BELOW IB 100 mA 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0
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134
2N6497
1.0

0.7 D = 0.5
0.5
r(t) EFFECTIVE TRANSIENT
0.3 0.2
0.2
0.1
P(pk)
0.1 0.05 RJC(max) = 1.56C/W
t1 SINGLE READ TIME AT t1
0.03 SINGLE PULSE t2 PULSE TJ(pk) - TC = P(pk) RJC(t)
0.02 0.01
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000

5.0
2.0 dc 5.0 ms 1.0 ms 100 s
1.0 dissipation than the curves indicate.
TC = 25C The data of Figure 14 is based on TC = 25C; TJ(pk) is
0.5
0.2 BONDING WIRE LIMITED
pulse limits are valid for duty cycles to 10% provided TJ(pk)
THERMAL LIMIT (SINGLE PULSE)
0.1 SECOND BREAKDOWN LIMIT 150C. TJ(pk) may be calculated from the data in
0.05 CURVES APPLY BELOW RATED VCEO Figure 13. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
0.02 the limitations imposed by second breakdown. Second
5.0 7.0 10 20 30 50 70 100 200 300 500
breakdown limitations do not derate the same as thermal
limitations. Allowable current at the voltage shown on
Figure 14. ActiveRegion Safe Operating Area Figure 14 may be found at any case temperature by using the
appropriate curve on Figure 16.
10 100
7.0 VCC = 125 V
5.0 ts IC/IB = 5.0 SECOND BREAKDOWN DERATING
POWER DERATING FACTOR (%)
TJ = 25C 80
3.0
2.0
t, TIME (s)
60

1.0
0.7 THERMAL DERATING
40
0.5
0.3 tf
20
0.2
0.1 0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 0 20 40 60 80 100 120 140 160
IC, COLLECTOR CURRENT (AMP) TC, CASE TEMPERATURE (C)
Figure 15. TurnOff Time Figure 16. Power Derating
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135
2N6497
100 4.0

TJ = 150C TJ = 25C
VCE = 10 V
70
3.2
50
25C
30 2.4
20 -55C
1.6
IC = 1.0 A 2.0 A 3.0 A 5.0 A

10
0.8
7.0
5.0 0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
1.4 +4.0

TJ = 25C hFE@VCE 10V
1.2 +3.0 *APPLIES FOR IC/IB
3
1.0 +2.0
V, VOLTAGE (VOLTS)
VBE(sat) @ IC/IB = 5.0

+1.0 *VC for VCE(sat) 25C to 150C
0.8
0.6 VBE @ VCE = 10 V 0

-55C to 25C
0.4 -1.0
25C to 150C
VB for VBE
0.2 VCE(sat) @ IC/IB = 5.0 -2.0
IC/IB = 2.5 -55 to 25C
0 -3.0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0
104 1000
VCE = 200 V 700
103 500 Cib

300
C, CAPACITANCE (pF)
102 TJ = 150C
200
TJ = 25C
101 100C
100
70
100 50
30 Cob
10-1 25C 20
REVERSE FORWARD
10-2 10
-0.1 -0.2 0 +0.2 +0.4 +0.6 0.4 0.6 1.0 2.0 4.0 6.0 10 20 40 60 100 200 400
VBE, BASE-EMITTER VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS)
Figure 21. Collector Cutoff Region Figure 22. Capacitance
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136
ON Semiconductor
2N6667
Darlington Silicon
2N6668
Power Transistors
. . . designed for generalpurpose amplifier and low speed
switching applications. PNP SILICON
DARLINGTON
High DC Current Gain POWER TRANSISTORS
hFE = 3500 (Typ) @ IC = 4 Adc 10 AMPERES
CollectorEmitter Sustaining Voltage @ 200 mAdc 6080 VOLTS
VCEO(sus) = 60 Vdc (Min) 2N6667 65 WATTS
= 80 Vdc (Min) 2N6668
VCE(sat) = 2 Vdc (Max)@ IC = 5 Adc
Complementary to 2N6387, 2N6388
COLLECTOR
CASE 221A09
TO220AB
BASE
8k 120
EMITTER
MAXIMUM RATINGS (1)


Rating Symbol
VCEO
2N6667
60
2N6668
80
Unit
Vdc


EmitterBase Voltage

VCB
VEB
60
5
80 Vdc
Vdc


Peak

IC 10
15
Adc


Total Device Dissipation @ TC = 25C PD 65 watts


Total Device Dissipation @ TA = 25C PD 2 Watts

Operating and Storage Junction Temperature Range

March, 2001 Rev. 3 2N6667/D
2N6667 2N6668



RJC
RJA
1.92
62.5
C/W
C/W
OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage (2) 2N6667 VCEO(sus) 60 Vdc

(IC = 200 mAdc, IB = 0) 2N6668 80

Collector Cutoff Current (VCE = 60 Vdc, IB = 0) 2N6667 ICEO 1 mAdc
(VCE = 80 Vdc, IB = 0) 2N6668 1


2N6667
2N6668
ICEX

300
300
Adc


2N6667
2N6668

3
3
mAdc
Emitter Cutoff Current (VBE = 5 Vdc, IC = 0) IEBO 5 mAdc

DC Current Gain (IC = 5 Adc, VCE = 3 Vdc) hFE 1000 20000


CollectorEmitter Saturation Voltage (IC = 5 Adc, IB = 0.01 Adc) VCE(sat)
100

2 Vdc

(IC = 10 Adc, IB = 0.1 Adc) 3

BaseEmitter Saturation Voltage(IC = 5 Adc, IB = 0.01 Adc) VBE(sat) 2.8 Vdc
(IC = 10 Adc, IB = 0.1 Adc) 4.5


Current Gain Bandwidth Product (IC = 1 Adc, VCE = 5 Vdc, ftest = 1 MHz) |hfe| 20

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1 MHz) Cob 200 pF

SmallSignal Current Gain (IC = 1 Adc, VCE = 5 Vdc, f = 1 kHz) hfe 1000
(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
VCC
- 30 V
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS RC

D1, MUST BE FAST RECOVERY TYPES e.g., SCOPE
1N5825 USED ABOVE IB 100 mA TUT
V2 RB
MSD6100 USED BELOW IB 100 mA
APPROX
FOR td AND tr, D1 IS DISCONNECTED AND V2 = 0 +8V
51 D1 8k 120
tr, tf 10 ns 0
DUTY CYCLE = 1.0% V1 + 4.0 V
APPROX
- 12 V 25 s
Figure 2. Switching Times Test Circuit
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138
2N6667 2N6668
TA TC
4 80 10
7 VCC = 30 V
5 IC/IB = 250
IB1 = IB2
3 60 3
tr TJ = 25C
2
TC
t, TIME (s)

ts
2 40 1
0.7
0.5
TA
1 20 0.3 .td
tf
0.2
0.1
0
0 20 40 60 80 100 120 140 160 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10
T, TEMPERATURE (C) IC, COLLECTOR CURRENT (AMPS)
Figure 3. Power Derating Figure 4. Typical Switching Times
1
D = 0.5
TRANSIENT THERMAL RESISTANCE
0.5
r(t) NORMALIZED EFFECTIVE
0.3
0.2
0.2
0.1
0.1 P(pk)
ZJC(t) = r(t) RJC
0.05 RJC = 1.92C/W MAX
0.05
0.03 0.02 t1 PULSE TRAIN SHOWN
t2 READ TIME AT t1
0.02 0.01 SINGLE PULSE
TJ(pk) - TC = P(pk) RJC(t)
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000
t, TIME (ms)
20
10 5 ms 100 s There are two limitations on the power handling ability of
5
dc breakdown. Safe operating area curves indicate IC VCE
3
2 1 ms limits of the transistor that must be observed for reliable
0.5
TJ = 150C
0.3 2N6667 The data of Figure 6 is based on TJ(pk) = 150C; TC is
0.2 BONDING WIRE LIMIT 2N6668 variable depending on conditions. Second breakdown pulse
0.1 THERMAL LIMIT @ TC = 25C limits are valid for duty cycles to 10% provided TJ(pk)
SECOND BREAKDOWN LIMIT < 150C. TJ(pk) may be calculated from the data in Figure 5.
0.05
CURVES APPLY BELOW RATED VCEO At high case temperatures, thermal limitations will reduce
0.03
0.02 the power that can be handled to values less than the
1 2 3 5 7 10 20 30 50 70 100
Figure 6. Maximum Safe Operating Area
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139
2N6667 2N6668
10,000 300
5000
hFE , SMALL-SIGNAL CURENT GAIN
2000 TJ = 25C
C, CAPACITANCE (pF)
1000 200
500
TC = 25C
Cib Cob
200 VCE = 4 VOLTS
IC = 3 AMPS 100
100
70
50
50
20
10 30
1 2 3 5 7 10 20 30 50 70 100 200 300 500 1000 0.1 0.2 0.5 1 2 5 10 20 50 100
Figure 7. Typical SmallSignal Current Gain Figure 8. Typical Capacitance
20,000 2.6

VCE = 3 V TJ = 25C
10,000
TJ = 150C 2.2
7000
IC = 2 A 4A 6A
5000
3000 1.8
2000
TJ = 25C
1.4
1000
700
500 1
TJ = - 55C
300
200 0.6
0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 0.3 0.5 0.7 1 2 3 5 7 10 20 30
IC, COLLECTOR CURRENT (AMPS) IB, BASE CURRENT (mA)
Figure 9. Typical DC Current Gain Figure 10. Typical Collector Saturation Region
3 +5
+4 hFE@VCE 3.0V

TJ = 25C *IC/IB
2.5 +3 3
V, VOLTAGE (VOLTS)
+2 25C to 150C
2 +1
-55C to 25C
0
1.5 -1
VC for VCE(sat)
-2
VBE @ VCE = 3 V 25C to 150C
1 -3
VB for VBE
-4 -55C to 25C
0.5 -5
0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10
IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMP)
Figure 11. Typical On Voltages Figure 12. Typical Temperature Coefficients
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140
2N6667 2N6668
105
REVERSE FORWARD
104

103 VCE = 30 V
102
TJ = 150C
101
100C
100
25C
10-1
+0.6 +0.4 +0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4
Figure 13. Typical Collector CutOff Region
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141
ON Semiconductor
BD135
Plastic Medium Power Silicon BD137
NPN Transistor BD139
. . . designed for use as audio amplifiers and drivers utilizing
complementary or quasi complementary circuits. 1.5 AMPERE
POWER TRANSISTORS
DC Current Gain NPN SILICON
hFE = 40 (Min) @ IC = 0.15 Adc 45, 60, 80 VOLTS
BD 135, 137, 139 are complementary with BD 136, 138, 140 10 WATTS
CASE 7709
TO225AA TYPE
MAXIMUM RATINGS

Rating Symbol Type Value Unit


VCEO BD 135
BD 137
45
60
Vdc

BD 139 80

CollectorBase Voltage VCBO BD 135 45 Vdc
BD 137 60

EmitterBase Voltage
VEBO
BD 139 100
5 Vdc

Collector Current

Base Current

IC
IB
1.5
0.5
Adc
Adc

Derate above 25C

Total Device Dissipation @ TA = 25C

PD 1.25
10
Watts
mW/C

Total Device Dissipation @ TC = 25C PD 12.5 Watt

Temperature Range


March, 2001 Rev. 9 BD135/D
BD135 BD137 BD139



JC
JA
10
100
C/W
C/W

Characteristic

CollectorEmitter Sustaining Voltage*
Symbol
BVCEO*
Type Min Max UnIt
Vdc

(IC = 0.03 Adc, IB = 0) BD 135 45

BD 137 60
BD 139 80


(VCB = 30 Vdc, IE = 0)

(VCB = 30 Vdc, IE = 0, TC = 125C)
ICBO

0.1
10
Adc


(VBE = 5.0 Vdc, IC = 0)

IEBO 10 Adc
DC Current Gain

(IC = 0.005 A, VCE = 2 V)
(IC = 0.15 A, VCE = 2 V)

hFE*
25

40 250
(IC = 0.5 A VCE = 2 V) 25

CollectorEmitter Saturation Voltage*

(IC = 0.5 Adc, IB = 0.05 Adc)
VCE(sat)* 0.5 Vdc

BaseEmitter On Voltage* VBE(on)* 1 Vdc
(IC = 0.5 Adc, VCE = 2.0 Vdc)
*Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
10.0
5.0
0.1 ms
2.0 5 ms 0.5 ms
1.0
TJ = 125C dc
0.5
0.1
0.05
BD135
0.02 BD137
BD139
0.01
1 2 5 10 20 50 80
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143
ON Semiconductor
BD136
PNP Transistor BD140
BD140-10
. . . designed for use as audio amplifiers and drivers utilizing
complementary or quasi complementary circuits. 1.5 AMPERE
DC Current Gain hFE = 40 (Min) @ IC = 0.15 Adc POWER TRANSISTORS
BD 136, 138, 140 are complementary with BD 135, 137, 139 PNP SILICON
45, 60, 80 VOLTS
10 WATTS
CASE 7709
TO225AA TYPE

MAXIMUM RATINGS

Rating Symbol Type Value Unit

CollectorEmitter Voltage VCEO BD 136 45 Vdc
BD 138 60

BD 140 80

CollectorBase Voltage VCBO BD 136 45 Vdc

BD 138 60
BD 140 100

EmitterBase Voltage

Collector Current

VEBO
IC
5
1.5
Vdc
Adc
Base Current

Total Device Dissipation@ TA = 25C PD
IB 0.5
1.25
Adc
Watts


Total Device Dissipation @ TC = 25C PD 12.5 Watt


Temperature Range

BD136 BD138 BD140 BD14010



JC
JA
10
100
C/W
C/W

Characteristic Symbol Type Min Max Unit

(IC = 0.03 Adc, IB = 0)

BVCEO
BD 136 45
Vdc

BD 138 60

BD 140 80
Adc

Collector Cutoff Current ICBO
(VCB = 30 Vdc, IE = 0) 0.1

(VCB = 30 Vdc, IE = 0, TC = 125 C) 10

Emitter Cutoff Current IEBO 10 Adc

(VBE = 5.0 Vdc, IC = 0)

DC Current Gain
(IC = 0.005 A, VCE = 2 V) ALL hFE* 25

(IC = 0.15 A, VCE = 2 V)

ALL
BD14010
40
63
250
160

(IC = 0.5 A, VCE = 2 V)

CollectorEmitter Saturation Voltage* VCE(sat)*
25

0.5 Vdc

(IC = 0.5 Adc, IB = 0.05 Adc)

BaseEmitter On Voltage* VBE(on)* 1 Vdc
(IC = 0.5 Adc, VCE = 2.0 Vdc)
10
5.0
0.1 ms
2.0 5 ms 0.5 ms
1.0
TJ = 125C dc
0.5
0.2
0.1
0.05
BD136
0.02 BD138
BD140
0.01
1 2 5 10 20 50 80
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145
ON Semiconductor
Plastic Medium Power NPN

BD159
Silicon Transistor
. . . designed for power output stages for television, radio,
phonograph and other consumer product applications. 0.5 AMPERE
Suitable for Transformerless, LineOperated Equipment POWER TRANSISTOR
Thermopad Construction Provides High Power Dissipation Rating for NPN SILICON
350 VOLTS
High Reliability
20 WATTS

MAXIMUM RATINGS

Rating Symbol Max Unit


VCEO
VCB
350
375
Vdc
Vdc

EmitterBase Voltage

VEB
IC
5.0
0.5
Vdc
Adc

Peak 1.0



C

Temperature Range

Characteristic

Symbol
JC
Max
6.25
Unit
C/W
CASE 7709
TO225AA TYPE


OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage BVCEO 350 Vdc
(IC = 1.0 mAdc, IB = 0)

(At rated voltage)

ICBO 100 Adc

Emitter Cutoff Current IEBO 100 Adc
(VEB = 5.0 Vdc, IC = 0)

ON CHARACTERISTICS

DC Current Gain hFE 30 240
(IC = 50 mAdc, VCE = 10 Vdc)

BD159
25 1.0
0.8 VBE @ IC/IB = 10

20
V, VOLTAGE (VOLTS)
0.6 VBE @ VCE = 10 V
15
0.4
10 VCE(sat) @ IC/IB = 10
0.2 TJ = +25C
IC/IB = 5.0
5.0 0
0 20 40 60 80 100 120 140 160 10 20 30 50 100 200 300 500
TC, CASE TEMPERATURE (C) IC, COLLECTOR CURRENT (mA)
Figure 2. PowerTemperature Derating Curve Figure 3. On Voltages
1.0 The Safe Operating Area Curves indicate IC VCE limits

0.7 10 s below which the device will not enter secondary breakdown.
0.5 500 s Collector load lines for specific circuits must fall within the
0.3 TJ = 150C 1.0 ms applicable Safe Area to avoid causing a catastrophic failure.
dc
0.2 To insure operation below, the maximum TJ,
powertemperature derating must be observed for both
0.1 steady state and pulse power conditions.
0.07
0.05
0.03
THERMALLY LIMITED @ TC = 25C
0.02 (SINGLE PULSE)
SECOND BREAKDOWN LIMITED
0.01
10 20 30 50 100 200 300
Figure 4. DC Safe Operating Area
300
VCE = 10 V
200 VCE = 2.0 V
TJ = 150C
100
70 + 100C
50 + 25C
30
20 - 55C
10
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
IC, COLLECTOR CURRENT (mAdc)
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147
ON Semiconductor
BD179
Plastic Medium Power Silicon
BD179-10
NPN Transistor
. . . designed for use in 5.0 to 10 Watt audio amplifiers and drivers
utilizing complementary or quasi complementary circuits. 3.0 AMPERES
DC Current Gain hFE = 40 (Min) @ IC = 0.15 Adc POWER TRANSISTORS
NPN SILICON
BD179 is complementary with BD180
80 VOLTS
30 WATTS

MAXIMUM RATINGS *ON Semiconductor Preferred Device




EmitterBase Voltage VEBO 5.0 Vdc



Derate above 25C 240 mw/C


Temperature Range



CASE 7709
Thermal Resistance, Junction to Case JC 4.16 C/W TO225AA TYPE


CollectorEmitter Sustaining Voltage* V(BR)CEO 80 Vdc

(IC = 0.1 Adc, IB = 0)

(VCB = 80 Vdc, IE = 0)


(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc
DC Current Gain

(IC = 0.15 A, VCE = 2.0 V)
(IC = 1.0 A, VCE = 2.0 V)

BD17910
ALL
hFE
63
15
160


(IC = 1.0 Adc, IB = 0.1 Adc)
VCE(sat) 0.8 Vdc

BaseEmitter On Voltage*

(IC = 1.0 Adc, VCE = 2.0 Vdc)
VBE(on) 1.3 Vdc

*Pulse Test: Pulse Width 300 As, Duty Cycle 2.0%.

BD179 BD17910
The Safe Operating Area Curves indicate IC VCE limits

below which the device will not enter secondary breakdown.
10
100 s
Collector load lines for specific circuits must fall within the
7.0
applicable Safe Area to avoid causing a catastrophic failure.

5.0 1.0 ms To insure operation below the maximum TJ,
3.0
5.0 ms
powertemperature derating must be observed for both
2.0
steady state and pulse power conditions.
dc
1.0 TJ = 150C
0.7
0.5 SECONDARY BREAKDOWN LIMITATION
0.3 THERMAL LIMITATION
(BASE-EMITTER DISSIPATION IS
0.2 SIGNIFICANT ABOVE IC = 2.0 AMP)
PULSE DUTY CYCLE < 10%
0.1
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
1.0
0.8
IC = 0.1 A 0.25 A 0.5 A 1.0 A
0.6
TJ = 25C
0.4
0.2
0
0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200
1000 1.5
hFE, DC CURRENT GAIN (NORMALIZED)
700
VCE = 2.0 V
500 TJ = 25C
1.2
300
VOLTAGE (VOLTS)
200
0.9
100 TJ = + 150C VBE(sat) @ IC/IB = 10
70 TJ = + 25C 0.6
50 VBE @ VCE = 2.0 V
30 TJ = + 55C 0.3
20
10 0
2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
Figure 3. Current Gain Figure 4. On Voltages
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149
BD179 BD17910
1.0
r(t), NORMALIZED EFFECTIVE TRANSIENT
0.7 D = 0.5
0.5
D = 0.2
THERMAL RESISTANCE
0.3
0.2 D = 0.1
SINGLE PULSE
0.1 D = 0.05
JC = 4.16C/W MAX
0.07 D = 0.01 JC = 3.5C/W TYP
t1
t2
READ TIME AT t1
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME or PULSE WIDTH (ms)
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150
ON Semiconductor
BD180
Plastic Medium Power Silicon
PNP Transistor 3.0 AMPERES
POWER TRANSISTOR
. . . designed for use in 5.0 to 10 Watt audio amplifiers and drivers PNP SILICON
utilizing complementary or quasi complementary circuits. 80 VOLTS
30 WATTS
DC Current Gain hFE = 40 (Min) @ IC = 0.15 Adc
BD180 is complementary with BD179
MAXIMUM RATINGS









Temperature Range

CASE 7709

Characteristic Symbol Max Unit TO225AA TYPE

Characteristic
Symbol
V(BR)CEO
Min
80
Max

Unit
Vdc

(IC = 0.1 Adc, IB = 0)


(VCB = 45 Vdc, IE = 0)
(VCB = 80 Vdc, IE = 0)

BD180
ICBO

1.0
mAdc

(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc
DC Current Gain

(IC = 0.15 A, VCE = 2.0 V)
(IC = 1.0 A, VCE = 2.0 V)

hFE
40 250

15

CollectorEmitter Saturation Voltage* VCE(sat) 0.8 Vdc
(IC = 1.0 Adc, IB = 0.1 Adc)


(IC = 1.0 Adc, VCE = 2.0 Vdc)
VBE(on) 1.3 Vdc



BD180
10 The Safe Operating Area Curves indicate IC VCE limits

7.0 100 s
5.0
1.0 ms Collector load lines for specific circuits must fall within the
3.0 applicable Safe Area to avoid causing a catastrophic failure.
2.0 5.0 ms
To insure operation below the maximum TJ,
dc powertemperature derating must be observed for both
1.0 TJ = 150C
0.7 steady state and pulse power conditions.
0.5 SECONDARY BREAKDOWN LIMITATION
THERMAL LIMITATION
0.3
(BASEEMITTER DISSIPATION IS
0.2 SIGNIFICANT ABOVE IC = 20 AMP)
PULSE DUTY CYCLE < 10% BD180
0.1
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100

1.0
TJ = 25C
0.8
IC = 0.1 A 0.25 A 0.5 A 1.0 A
0.6
0.4
0.2
0
0.2 0.5 1.0 2.0 5.0 10 20 50 100 200

1000 1.5
700
500 VCE = 2.0 V

TJ = 25C
1.2
300
VOLTAGE (VOLTS)
200 TJ = + 150C
0.9
100 TJ = + 25C VBE(sat) @ IC/IB = 10
70 0.6
50 TJ = - 55C VBE @ VCE = 2.0 V
30 0.3
20
10 0
2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000

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152
BD180
r(t), NORMALIZED EFFECTIVE TRANSIENT 1.0

0.7 D = 0.5
0.5
0.3 D = 0.2
THERMAL RESISTANCE
0.2 D = 0.1
SINGLE PULSE
0.1 D = 0.05
JC = 4.16C/W MAX
0.07 D = 0.01 JC = 3.5C/W TYP
t1
t2
READ TIME AT t1
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
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153
ON Semiconductor
NPN
BD237
Plastic Medium Power Silicon PNP
. . . designed for use in 5.0 to 10 Watt audio amplifiers and drivers
utilizing complementary or quasi complementary circuits. 2.0 AMPERES
POWER TRANSISTORS
DC Current Gain NPN SILICON
hFE = 40 (Min) @ IC = 0.15 Adc 80 VOLTS
25 WATTS
MAXIMUM RATINGS







Temperature Range


CASE 7709
TO225AA TYPE


Characteristic
Symbol
V(BR)CEO
Min
80
Max

Unit
Vdc

(IC = 0.1 Adc, IB = 0)


(VCB = 100 Vdc, IE = 0)

(VBE = 5.0 Vdc, IC = 0)
DC Current Gain

(IC = 0.15 A, VCE = 2.0 V)

hFE1 40

(IC = 1.0 A, VCE = 2.0 V) hFE2 25

CollectorEmitter Saturation Voltage* VCE(sat) 0.6 Vdc
(IC = 1.0 Adc, IB = 0.1 Adc)


(IC = 1.0 Adc, VCE = 2.0 Vdc)
VBE(on) 1.3 Vdc


fT 3.0 MHz

April, 2001 Rev. 10 BD237/D
BD238
10 The Safe Operating Area Curves indicate IC VCE limits

100 s
1 ms
Collector load lines for specific circuits must fall within the
3
5 ms applicable Safe Area to avoid causing a catastrophic failure.
To insure operation below the maximum TJ,
TJ = 150C dc powertemperature derating must be observed for both
1
steady state and pulse power conditions.
0.3
BD236
0.1 BD237
1 3 10 30 100
1.0
0.8
IC = 0.1 A 0.25 A 0.5 A 1.0 A
0.6
TJ = 25C
0.4
0.2
0
0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200
1000 1.5
700
500 VCE = 2.0 V TJ = 25C
1.2
300
VOLTAGE (VOLTS)
200 0.9
TJ = + 150C
100 VBE(sat) @ IC/IB = 10
70 TJ = + 25C 0.6
50 VBE @ VCE = 2.0 V
30 TJ = + 55C 0.3
20
10 0
2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 2000
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155
BD238
1.0
r(t), NORMALIZED EFFECTIVE TRANSIENT 0.7 D = 0.5
0.5
0.3 D = 0.2
THERMAL RESISTANCE
0.2 D = 0.1
SINGLE PULSE
0.1 D = 0.05
JC = 4.16C/W MAX
0.07 D = 0.01 JC = 3.5C/W TYP
t1
t2
READ TIME AT t1
0.02 TJ(pk) - TC = P(pk) JC(t) DUTY CYCLE, D = t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
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156
ON Semiconductor
Complementary Silicon Plastic NPN

Power Transistors BD241C*
PNP
. . . designed for use in general purpose amplifier and switching
applications.
BD242C*
CollectorEmitter Saturation Voltage *ON Semiconductor Preferred Device
VCE = 1.2 Vdc (Max) @ IC = 3.0 Adc 3 AMPERE

CollectorEmitter Sustaining Voltage POWER TRANSISTORS
VCEO(sus) = 100 Vdc (Min.) BD241C, BD242C COMPLEMENTARY
High Current Gain Bandwidth Product SILICON
80, 100 VOLTS
fT = 3.0 MHz (Min) @ IC = 500 mAdc
40 WATTS
Compact TO220 AB Package
MAXIMUM RATINGS

Rating Symbol
BD241C
BD242C Unit


CollectorEmitter Voltage VCES 115 Vdc



Peak 5.0 Adc CASE 221A09
TO220AB




Temperature Range



RJA
RJC
62.5
3.125
C/W
C/W

May, 2001 Rev. 3 BD241C/D
BD241C BD242C
40

30
20
10
0
0 20 40 60 80 100 120 140 160
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158
BD241C BD242C

Characteristic Symbol Min. Max. Unit
OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage1 VCEO Vdc

(IC = 30 mAdc, IB = 0) BD241C, BD242C 100


(VCE = 60 Vdc, IB = 0) BD241C, BD242C
Adc

Collector Cutoff Current ICES
(VCE = 100 Vdc, VEB = 0) BD241C, BD242C 200


(VBE = 5.0 Vdc, IC = 0)

IEBO
1.0
mAdc
DC Current Gain

ON CHARACTERISTICS1

hFE

(IC = 1.0 Adc, VCE = 4.0 Vdc) 25
(IC = 3.0 Adc, VCE = 4.0 Vdc) 10


(IC = 3.0 Adc, IB = 600 Adc)
VCE(sat)
1.2
Vdc


(IC = 3.0 Adc, VCE = 4.0 Vdc)
VBE(on)
1.8
Vdc

Current Gain Bandwidth Product2 fT MHz

(IC = 500 mAdc, VCE = 10 Vdc, ftest = 1 MHz) 3.0

SmallSignal Current Gain hfe
(IC = 0.5 Adc, VCE = 10 Vdc, f = 1 kHz) 20
1 Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
2 fT = |hfe| ftest.
2.0
TURNON PULSE VCC IC/IB = 10
RL 1.0
APPROX TJ = 25C
+ 11 V Vin SCOPE 0.7 tr @ VCC = 30 V
RK 0.5
Vin 0 CjdCeb
t, TIME (s)
0.3

VEB(off) tr @ VCC = 10 V
t1
- 4.0 V
t3
APPROX t1 7.0 ns
+ 11 V 0.1
100 t2 500 s
0.07 td @ VBE(off) = 2.0 V
t3 15 ns
0.05
Vin
0.03
DUTY CYCLE 2.0% 0.02
t2 0.03 0.05 0.07 0.1 0.3 0.5 0.7 1.0 3.0
TURNOFF PULSE APPROX - 9.0 V
Figure 2. Switching Time Equivalent Circuit Figure 3. TurnOn Time
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159
BD241C BD242C
1.0
r(t), TRANSIENT THERMAL RESISTANCE 0.7
D = 0.5
0.5
0.3
0.2
0.2
(NORMALIZED)
0.1
0.1 P(pk)
0.05 ZJC (t) = r(t) RJC
0.07 RJC = 3.125C/W MAX
0.02
t1
READ TIME AT t1 t2
0.02 0.01 TJ(pk) - TC = P(pk) ZJC(t)
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k
t, TIME (ms)
10

5.0
1.0 ms breakdown. Safe operating area curves indicate IC VCE
100 s
2.0 operation, i.e., the transistor must not be subjected to greater
1.0 SECOND BREAKDOWN The data of Figure 5 is based on TJ(pk) = 150C; TC is
LIMITED @ TJ 150C variable depending on conditions. Second breakdown pulse
0.5 THERMAL LIMITATION @ TC = 25C limits are valid for duty cycles to 10% provided TJ(pk)
150C, TJ(pk) may be calculated from the data in
0.2 CURVES APPLY BELOW Figure 4. At high case temperatures, thermal limitations will
RATED VCEO
BD241C, BD242C reduce the power that can be handled to values less than the
5.0 10 20 50 100
3.0 300
IB1 = IB2
2.0 TJ = + 25C
ts IC/IB = 10
ts = ts - 1/8 tf 200
1.0 TJ = 25C
0.7 tf @ VCC = 30 V
CAPACITANCE (pF)
0.5
t, TIME (s)

0.3 100
tf @ VCC = 10 V Ceb
0.2
70
0.1
0.07 50 Ccb
0.05
0.03 30
0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 40
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160
BD241C BD242C
500 2.0

300 VCE = 2.0 V TJ = 25C
TJ = 150C
1.6
25C
100
70 1.2
-55C IC = 0.3 A 1.0 A 3.0 A
50
30 0.8
0.4
10
7.0
5.0 0
0.03 0.05 0.07 0.1 0.3 0.5 0.7 1.0 3.0 1.0 2.0 5.0 10 20 50 100 200 500 1000
1.4 +2.5

TJ = 25C +2.0 *APPLIES FOR IC/IB 5.0
1.2 TJ = - 65C TO + 150C
+1.5
1.0
V, VOLTAGE (VOLTS)
+1.0
+0.5 *VC FOR VCE(sat)
0.8
VBE(sat) @ IC/IB = 10 0
0.6 -0.5
VBE @ VCE = 2.0 V
0.4 -1.0
-1.5
0.2 VCE(sat) @ IC/IB = 10 VB FOR VBE
-2.0
0 -2.5
0.003 0.005 0.01 0.020.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 0.003 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0
103 107
VCE = 30 V
VCE = 30 V IC = 10 x ICES
102
106

TJ = 150C
101
105
100 100C IC ICES
IC = 2 x ICES
104
10-1
REVERSE FORWARD
10-2 103 (TYPICAL ICES VALUES
25C
ICES
10-3 102
-0.4 -0.3 -0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 20 40 60 80 100 120 140 160
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161
ON Semiconductor
NPN
Complementary Silicon Plastic BD243B
Power Transistors
. . . designed for use in general purpose amplifier and switching BD243C *
applications. PNP
Collector Emitter Saturation Voltage BD244B
BD244C *
VCE(sat) = 1.5 Vdc (Max) @ IC = 6.0 Adc
Collector Emitter Sustaining Voltage
VCEO(sus) = 80 Vdc (Min) BD243B, BD244B
= 100 Vdc (Min) BD243C, BD244C
High Current Gain Bandwidth Product 6 AMPERE
fT = 3.0 MHz (Min) @ IC = 500 mAdc POWER TRANSISTORS

Compact TO220 AB Package COMPLEMENTARY

SILICON

MAXIMUM RATINGS

BD243B BD243C
80100 VOLTS
65 WATTS

Rating Symbol BD244B BD244C Unit




Peak 10

Base Current
IB 2.0 Adc

Total Device Dissipation

@ TC = 25C

PD
65
Watts

CASE 221A06

Operating and Storage Junction TJ, Tstg 65 to +150 C TO220AB
Temperature Range


80
60
40
20
0
0 20 40 60 80 100 120 140 160

March, 2001 Rev. 9 BD243B/D
BD243B BD243C BD244B BD244C

(IC = 30 mAdc,

mAdc IB = 0)

CollectorEmitter Sustaining Voltage (1)

BD243B,
BD243B BD244B
VCEO(sus)
80
Vdc

BD243C, BD244C 100

(VCE = 60 Vdc, IB = 0) BD243B, BD243C, BD244B, BD244C


(VCE = 80 Vdc, VEB = 0)
(VCE = 100 Vdc, VEB = 0)

BD243B, BD244B
BD243C, BD244C
ICES

400
400
Adc


(VBE = 5.0 Vdc, IC = 0)

IEBO 1.0 mAdc
DC Current Gain


hFE

(IC = 0.3 Adc, VCE = 4.0 Vdc) 30
(IC = 3.0 Adc, VCE = 4.0 Vdc)

15

(IC = 6.0 Adc, IB = 1.0 Adc)


(IC = 6.0 Adc, VCE = 4.0 Vdc)
VBE(on) 2.0 Vdc


(IC = 500 mAdc, VCE = 10 Vdc, ftest = 1.0 MHz)

(IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 kHz)
(1) Pulse Test: Pulsewidth 300 s, Duty Cycle 2.0%.
(2) fT = hfe ftest
VCC 2.0
- 30 V
TJ = 25C
1.0
VCC = 30 V
25 s RC 0.7 IC/IB = 10
+ 11 V 0.5
SCOPE
t, TIME (s)
RB 0.3

0
0.2 tr
- 9.0 V 51 D1
0.1
tr, tf 10 ns
0.07 td @ VBE(off) = 5.0 V
DUTY CYCLE = 1.0% -4V
0.05
0.03
D1 MUST BE FAST RECOVERY TYPE eg.
0.02
1N5825 USED ABOVE IB 100 mA 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 6.0
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163
1.0
THERMAL RESISTANCE (NORMALIZED) 0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
P(pk)
0.1 0.05 RJC(max) = 1.92C/W
t1 SINGLE READ TIME AT t1
0.03 SINGLE PULSE t2 PULSE TJ(pk) - TC = P(pk) RJC(t)
0.02 0.01
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000

5.0 0.5 ms a transistor: average junction temperature and second

2.0 1.0 limits of the transistor that must be observed for reliable
ms
TJ = 150C
5.0 ms dissipation than the curves indicate.
1.0 SECOND BREAKDOWN LIMITED The data of Figure 5 is based on TJ(pk) = 150C: TC is
THERMAL LIMITATION @ TC = 25C
0.5
0.3 150C, TJ(pk) may be calculated from the data in
BD243B, BD244B
BD243C, BD244C reduce the power that can be handled to values less than the
5.0 10 20 40 60 80 100
5.0 300
3.0 TJ = 25C TJ = 25C
VCC = 30 V 200
2.0
ts IC/IB = 10
IB1 = IB2
1.0 Cib
CAPACITANCE (pF)
t, TIME (s)
0.7

0.5 100
0.3 70
0.2 Cob
tf
50
0.1
0.07
0.05 30
0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 6.0 0.5 1.0 2.0 3.0 5.0 10 20 30 50
Figure 6. Turn-Off Time Figure 7. Capacitance
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164
500 2.0

VCE = 2.0 V TJ = 25C
300
200 TJ = 150C
1.6
100 IC = 1.0 A 2.5 A 5.0 A

70 25C 1.2
50
30 0.8
20 -55C
10 0.4
7.0
5.0 0
0.06 0.1 0.2 0.3 0.4 0.6 1.0 2.0 4.0 6.0 10 20 30 50 100 200 300 500 1000
2.0 +2.5

TJ = 25C +2.0 *APPLIES FOR IC/IB 5.0
1.6 +1.5
V, VOLTAGE (VOLTS)
+1.0
VBE(sat) @ IC/IB = 10 + 25C to + 150C
1.2 +0.5
*VC FOR VCE(sat)
0
VBE @ VCE = 4.0 V - 55C to + 25C
0.8 -0.5
-1.0 + 25C to + 150C
0.4 VCE(sat) @ IC/IB = 10 -1.5 VB FOR VBE

-2.0 - 55C to + 25C
0 -2.5
0.06 0.1 0.2 0.3 0.4 0.6 1.0 2.0 3.0 4.0 6.0 0.06 0.1 0.2 0.3 0.5 1.0 2.0 3.0 0.4 0.6
103 10M
VCE = 30 V VCE = 30 V
102
TJ = 150C 1.0M IC = 10 x ICES

101
100C IC = 2 x ICES
100k
25C
100
10k IC ICES
10-1 IC = ICES
10-2 REVERSE FORWARD 1.0k

(TYPICAL ICES VALUES
10-3 0.1k
-0.3 -0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 20 40 60 80 100 120 140 160
VBE, BASEEMITTER VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (C)
Figure 12. Collector Cut-Off Region Figure 13. Effects of BaseEmitter Resistance
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165
ON Semiconductor
BD437
. . . for amplifier and switching applications. Complementary types 4.0 AMPERES

are BD438 and BD442. POWER TRANSISTORS
NPN SILICON
MAXIMUM RATINGS


CollectorEmitter Voltage BD437 VCEO 45 Vdc
BD439 60

BD441 80

CollectorBase Voltage BD437 VCBO 45 Vdc

BD439 60
BD441 80 CASE 7709

TO225AA TYPE

Collector Current

Base Current

IC
IB
4.0
1.0
Adc
Adc


Derate above 25C
PD 36
288
Watts
W/C

Temperature Range



May, 2001 Rev. 10 BD437/D
BD437 BD439 BD441


(IC = 100 mA, IB = 0)

CollectorEmitter Breakdown Voltage

BD437
V(BR)CEO
45
Vdc

BD439 60
BD441 80

(IC = 100 A, IB = 0)

CollectorBase Breakdown Voltage

BD437
V(BR)CBO
45
Vdc

BD439 60
BD441 80

(IE = 100 A, IC = 0)

EmitterBase Breakdown Voltage

V(BR)EBO 5.0 Vdc


(VCB = 45 V, IE = 0)
(VCB = 60 V, IE = 0)

BD437
BD439
ICBO
0.1
mAdc

0.1
(VCB = 80 V, IE = 0) BD441 0.1
(VEB = 5.0 V)

IEBO 1.0 mAdc

DC Current Gain hFE

(IC = 10 mA, VCE = 5.0 V) BD437 30
BD439 20

BD441 15
DC Current Gain

(IC = 500 mA, VCE = 1.0 V)

BD437
BD439, BD441
hFE
85 375

40 475

DC Current Gain hFE
(IC = 2.0 A, VCE = 1.0 V) BD437 40

BD439 25

BD441 15

Collector Saturation Voltage VCE(sat) Vdc
(IC = 3.0 A, IB = 0.3 A) BD437, BD439, BD441 0.8


(IC = 2.0 A, VCE = 1.0 V)

VBE(on) 1.1 Vdc


(VCE = 1.0 V, IC = 250 mA, f = 1.0 MHz)
fT 3.0 MHz
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167
BD437 BD439 BD441
2.0
1.6
IC = 10 A 100 mA 1.0 A 3.0 A
1.2
0.8
TJ = 25C
0.4
0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
200
hFE, CURRENT GAIN (NORMALIZED)
180 BD433, 435, 437

160
140
120 BD439, 441
100
80
60
40
20
0
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5
2.0 10
TJ = 25C
1.6 4.0 5 ms
TJ = 150C
VOLTAGE (VOLTS)
1.2 dc
1.0 SECONDARY BREAKDOWN

0.8 VBE(sat) @ IC/IB = 10 THERMAL LIMIT TC = 25C
VBE @ VCE = 2.0 V 0.5 BONDING WIRE LIMIT
0.6 BD437
VCE(sat) @ IC/IB = 10 BD439
BD441
0 0.1
0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0 1.0 2.0 5.0 10 20 50 100
IC, COLLECTOR CURRENT (AMP) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 3. On Voltage Figure 4. Active Region Safe Operating Area
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168
ON Semiconductor
BD438
PNP Transistor BD442
. . . for amplifier and switching applications. Complementary types
are BD437 and BD441.
4.0 AMPERES
POWER TRANSISTORS
PNP SILICON

MAXIMUM RATINGS



BD438
BD440
BD442
VCEO 45
60
80
Vdc


BD438
BD440
VCBO 45
60
Vdc

BD442 80

CASE 7709

Collector Current IC 4.0 Adc TO225AA TYPE


Derate above 25C 288 W/C


Temperature Range




March, 2001 Rev.9 BD438/D
BD438 BD440 BD442


(IC = 100 mA, IB = 0)


BD438
V(BR)CEO
45
Vdc

BD440 60
BD442 80

(IC = 100 A, IB = 0)


BD438
BD440
V(BR)CBO
45
60

Vdc

BD442 80

(IE = 100 A, IC = 0)

EmitterBase Breakdown Voltage

V(BR)EBO 5.0 Vdc

(VCB = 45 V, IE = 0) BD438 0.1

(VCB = 60 V, IE = 0)

(VCB = 80 V, IE = 0)

BD440
BD442

0.1
0.1

(VEB = 5.0 V)
DC Current Gain

(IC = 10 mA, VCE = 5.0 V)
BD438
hFE
30

BD440 20
BD442 15
DC Current Gain

(IC = 500 mA, VCE = 1.0 V)

BD438
hFE
85 375

BD440 40 475
BD442 40 475
DC Current Gain

(IC = 2.0 A, VCE = 1.0 V)

BD438
hFE
40

BD440 25
BD442 15

Collector Saturation Voltage

(IC = 3.0 A, IB = 0.3 A)

BD438
VCE(sat)
0.7
Vdc

BD440 0.8
BD442 0.8


(IC = 2.0 A, VCE = 1.0 V)

BD438
BD440/442
VBE(ON)

1.1
1.5
Vdc

(VCE = 1.0 V, IC = 250 mA, f = 1.0 MHz)
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170
BD438 BD440 BD442
2.0
1.6
IC = 10 mA 100 mA 1.0 A 3.0 A
1.2
0.8
TJ = 25C
0.4
0
0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
200
hFE, CURRENT GAIN (NORMALIZED)
100
80
60
40
20
0
10 2 3 100 1 5
2.0 10
TJ = 25C
1.6 4.0 5 ms
TJ = 150C
VOLTAGE (VOLTS)
1.2 dc
SECONDARY BREAKDOWN
1.0 THERMAL LIMIT TC = 25C
0.8 VBE(sat) @ IC/IB = 10 BONDING WIRE LIMIT
VBE @ VCE = 2.0 V 0.5 CURVES APPLY BELOW RATED VCEO
0.4 BD438
VCE(sat) @ IC/IB = 10 BD440
BD442
0 0.1
0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0 1.0 2.0 5.0 10 20 50 100
IC, COLLECTOR CURRENT (AMP) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 3. On Voltage Figure 4. Active Region Safe Operating Area
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171
ON Semiconductor
BD675
Plastic Medium-Power BD675A
Silicon NPN Darlingtons BD677
. . . for use as output devices in complementary generalpurpose BD677A
amplifier applications.
BD679
hFE = 750 (Min) @ IC BD679A
= 1.5 and 2.0 Adc

Monolithic Construction
BD681*
BD675, 675A, 677, 677A, 679, 679A, 681 are complementary with *ON Semiconductor Preferred Device
BD676, 676A, 678, 678A, 680, 680A, 682
4.0 AMPERE
BD 677, 677A, 679, 679A are equivalent to MJE 800, 801, 802, 803
DARLINGTON
MAXIMUM RATINGS POWER TRANSISTORS

BD675 BD677 BD679 NPN SILICON
60, 80, 100 VOLTS

Symbo BD675 BD677 BD679 BD68
Rating l A A A 1 Unit 40 WATTS


VCEO 45 60 80 100 Vdc


EmitterBase Voltage
VCB
VEB
45 60
5.0
80 100 Vdc
Vdc

Collector Current

Base Current

IC
IB
4.0
0.1
Adc
Adc


@TC = 25C

PD
40 Watts

CASE 7709
C

Operating and Storage TJ, Tstg 55 to +150
TO225AA TYPE
Junction

Temperating Range


50
45
JC 3.13 C/W
40
35
30
25
20
15
10
5.0
0
15 30 45 60 75 90 105 120 135 150 165
Figure 1. Power Temperature Derating

March, 2001 Rev.9 BD675/D
BD675 BD675A BD677 BD677A BD679 BD679A BD681


OFF CHARACTERISTICS

CollectorEmitter Breakdown Voltage(1) BD675, 675A BVCEO 45 Vdc

(IC = 50 mAdc, IB = 0) BD677, 677A 60
BD679, 679A 80

Collector Cutoff Current (VCE = Half Rated VCEO, IB = 0)
BD681
ICEO
100

500 Adc


(VCB = Rated BVCEO, IE = 0)
(VCB = Rated BVCEO, IE = 0, TC = 100C)
ICBO

0.2
2.0
mAdc

ON CHARACTERISTICS
IEBO 2.0 mAdc

DC Currert Gain(1)

(IC = 1.5 Adc,VCE = 3.0 Vdc) BD675, 677, 679, 681
hFE
750

(IC = 2.0 Adc, VCE = 3.0 Vdc) BD675A, 677A, 679A 750
CollectorEmitter Saturation Voltage(1)

(IC = 1.5 Adc, IB = 30 mAdc)

(IC = 2.0 Adc, IB = 40 mAdc)
BD677, 679, 681
BD675A, 677A, 679A
VCE(sat)

2.5
2.8
Vdc

BaseEmitter On Voltage(1) VBE(on) Vdc

(IC = 1.5 Adc, VCE = 3.0 Vdc) BD677, 679, 681 2.5
(IC = 2.0 Adc, VCE = 3 0 Vdc) BD675A, 677A, 679A 2.5


Small Signal Current Gain (IC = 1.5 Adc, VCE = 3.0 Vdc, f = 1.0 MHz)
hfe 1.0

a transistor average junction temperature and secondary

1.0 operation; e.g., the transistor must not be subjected to greater
BONDING WIRE LIMIT dissipation than the curves indicate.
0.5 THERMALLY LIMIT at TC = 25C At high case temperatures, thermal limitations will reduce
SECONDARY BREAKDOWN LIMIT the power that can be handled to values less than the
0.2 limitations imposed by secondary breakdown.
BD675, 675A
TC = 25C BD677, 677A
0.1 BD679, 679A
BD681
0.05
1.0 2.0 5.0 10 20 50 100
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173
BD675 BD675A BD677 BD677A BD679 BD679A BD681
NPN COLLECTOR
BD675, 675A
BD677, 677A
BD679, 679A
BD681
BASE
8.0 k 120
EMITTER
Figure 3. Darlington Circuit Schematic
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174
BD676, BD676A, BD678,
BD678A, BD680, BD680A,
BD682
Plastic Medium-Power
Silicon PNP Darlingtons
http://onsemi.com
...for use as output devices in complementary generalpurpose
4.0 AMPERE
hFE = 750 (Min) @ IC = 1.5 and 2.0 Adc DARLINGTON
Monolithic Construction POWER TRANSISTORS
BD676, 676A, 678, 678A, 680, 680A, 682 are complementary with PNP SILICON
BD675, 675A, 677, 677A, 679, 679A, 681 45, 60, 80, 100 VOLTS
BD 678, 678A, 680, 680A are equivalent to MJE 700, 701, 702, 703 40 WATTS
MAXIMUM RATINGS
Collector-Emitter Voltage VCEO Vdc
BD676, BD676A 45
BD678, BD678A 60
BD680, BD680A 80
BD682 100
Collector-Base Voltage VCB Vdc
BD676, BD676A 45 TO225AA
BD678, BD678A 60 CASE 77
BD680, BD680A 80 STYLE 1
BD682 100
Emitter-Base Voltage VEB 5.0 Vdc MARKING DIAGRAM

Base Current IB 0.1 Adc YWW
BD6xxx
Total Device Dissipation PD
@ TC = 25C 40 W
Derate above 25C 0.32 W/C Y = Year
WW = Work Week
Operating and Storage Junction TJ, Tstg 55 to +150 C BD6xxx = Specific Device Code
Temperature Range xxx = 76, 76A, 78, 78A, 80, 80A or 82
Characteristic Symbol Max Unit ORDERING INFORMATION
Thermal Resistance RJC 3.13 C/W Device Package Shipping

Junction to Case
BD676 TO225AA 500 Units/Box
BD676A TO225AA 500 Units/Box
Semiconductor Components Industries, LLC, 2001 Publication Order Number:

BD676, BD676A, BD678, BD678A, BD680, BD680A, BD682

OFF CHARACTERISTICS

CollectorEmitter Breakdown Voltage (Note 1.) BD676, 676A BVCEO 45 Vdc

(IC = 50 mAdc, IB = 0) BD678, 678A 60
BD680, 680A 80

Collector Cutoff Current (VCE = Half Rated VCEO, IB = 0)
BD682
ICEO
100

500 Adc


(VCB = Rated BVCEO, IE = 0)

(VCB = Rated BVCEO. IE = 0, TC = 100C)
ICBO

0.2
2.0
mAdc

ON CHARACTERISTICS
IEBO 2.0 mAdc

DC Current Gain (Note 1.)

(IC = 1.5 Adc, VCE = 3.0 Vdc) BD676, 678, 680, 682
hFE
750

(IC = 2.0 Adc, VCE = 3.0 Vdc) BD676A, 678A, 680A 750

CollectorEmitter Saturation Voltage (Note 1.)
(IC = 1.5 Adc, IB = 30 mAdc) BD678, 680, 682 VCE(sat) 2.5 Vdc

(IC = 2.0 Adc, IB = 40 mAdc) BD676A, 678A, 680A 2.8

BaseEmitter On Voltage (Note 1.) VBE(on) Vdc

(IC = 1.5 Adc, VCE = 3.0 Vdc) BD678, 680, 682 2.5
(IC = 2.0 Adc, VCE = 3.0 Vdc) BD676A, 678A, 680A 2.5


SmallSignal Current Gain (IC = 1.5 Adc, VCE = 3.0 Vdc, f = 1.0 MHz) hfe 1.0
1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
50
45
40
35
30
25
20
15
10
5.0
0
15 30 45 60 75 90 105 120 135 150 165
Figure 1. Power Temperature Derating
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176
BD676, BD676A, BD678, BD678A, BD680, BD680A, BD682

a transistor average junction temperature and secondary

1.0 operation; e.g., the transistor must not be subjected to greater
BONDING WIRE LIMIT dissipation than the curves indicate.
0.5 THERMAL LIMIT at TC = 25C At high case temperatures, thermal limitations will reduce
SECONDARY BREAKDOWN LIMIT the power that can be handled to values less than the
0.2 limitations imposed by secondary breakdown.
BD676, 676A
TC = 25C BD678, 678A
0.1 BD680, 680A
BD682
0.05
1.0 2.0 5.0 10 20 50 100
PNP COLLECTOR
BD676, 676A
BD678, 678A
BD680, 680A
BD682
BASE
8.0 k 120
EMITTER
Figure 3. Darlington Circuit Schematic
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177
ON Semiconductor
NPN
Complementary Plastic Silicon BD787
PNP
Power Transistors BD788
. . . designed for lower power audio amplifier and low current,
highspeed switching applications.
Low CollectorEmitter Sustaining Voltage 4 AMPERE
VCEO(sus) 60 Vdc (Min) BD787, BD788 POWER TRANSISTORS
High CurrentGain Bandwidth Product COMPLEMENTARY
fT = 50 MHz (Min) @ IC = 100 mAdc SILICON
CollectorEmitter Saturation Voltage Specified at 0.5, 1.0, 2.0 and 60 VOLTS
15 WATTS
4.0 Adc
MAXIMUM RATINGS

BD787
Rating Symbol BD788 Unit


VCEO
VCBO
60
80
Vdc
Vdc

EmitterBase Voltage

VEBO 6.0
4.0
Vdc
Adc

Peak IC 8.0 Adc CASE 7709

TO225AA TYPE


Derate Above 25C PD
15
0.12
Watts
W/C

Temperature Range


16 1.6
12 1.2
TA
TC
8.0 0.8
4.0 0.4
0 0
20 40 60 80 100 120 140 160
T, TEMPERATURE (C)

BD787 BD788

OFF CHARACTERISTICS


(IC = 10 mAdc, IB = 0)

Collector Cutoff Current ICEO 100 Adc

(VCE = 20 Vdc, IB = 0)
(VCE = 30 Vdc, IB = 0)


(VCE = 80 Vdc, VBE(off) = 1.5 Vdc)
(VCE = 40 Vdc, VBE(off) = 1.5 Vdc, TC = 125C)
ICEX

1.0
0.1
Adc
mAdc


(VEB = 6.0 Vdc, IC = 0)

IEBO 1.0 Adc
DC Current Gain

ON CHARACTERISTICS(1)

hFE

(IC = 200 mAdc, VCE = 3.0 Vdc) 40 250
(IC = 1.0 Adc, VCE = 3.0 Vdc) 25

(IC = 2.0 Adc, VCE = 3.0 Vdc)

(IC = 4.0 Adc, VCE = 3.0 Vdc)
20
5.0

(IC = 500 mAdc, IB = 50 mAdc) 0.4

(IC = 1.0 Adc, IB = 100 mAdc) 0.6

(IC = 2.0 Adc, IB = 200 mAdc) 0.8
(IC = 4.0 Adc, IB = 800 mAdc) 2.5


(IC = 2.0 Adc, IB = 200 mAdc)
VBE(sat) 2.0 Vdc


(IC = 2.0 Adc, VCE = 3.0 Vdc)


CurrentGain Bandwidth Product fT 50 MHz
(IC = 100 mAdc, VCE = 10 Vdc, f = 10 MHz)
Output Capacitance

(VCB = 10 Vdc, IC = 0)

BD787
Cob
50
pF

(f = 0.1 MHz) BD788 70

(IC = 200 mAdc, VCE = 10 Vdc, f = 1.0 kHz)
(1) Pulse Test; Pulse Width 300 s, Duty Cycle 2.0%.
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179
BD787 BD788
+ 30 V 500
VCC 300 VCC = 30 V
25 s RC 200 IC/IB = 10
+ 11 V TJ = 25C
SCOPE
RB 100 tr
0
t, TIME (ns)
70
- 9.0 V 50
51 D1
tr, tf 10 ns 30
td @ VBE(off) = 5.0 V
DUTY CYCLE = 1.0% -4V 20
10 BD787 (NPN)
D1 MUST BE FAST RECOVERY TYPE, e.g.: BD788 (PNP)
7.0
1N5825 USED ABOVE IB 100 mA
5.0
MSD6100 USED BELOW IB 100 mA 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
FOR PNP TEST CIRCUIT, REVERSE ALL POLARITIES. IC, COLLECTOR CURRENT (AMP)
1.0
0.7 D = 0.5
0.5
0.3 0.2
(NORMALIZED)
0.2 0.1
0.05 P(pk)
0.1 RJC(t) = r(t) RJC
0.07 RJC = 8.34C/W MAX
0.03 0.01 t2 READ TIME AT t1
0.02 0 (SINGLE PULSE) TJ(pk) - TC = P(pk) RJC(t)
0.01
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200
t, TIME (ms)

1.0 ms 100 s a transistor: average junction temperature and second
5.0
500 s breakdown. Safe operating area curves indicate IC VCE

2.0
dc
TJ = 150C
1.0 dissipation than the curves indicate.
BONDING WIRE LIMITED The data of Figure 5 is based on TJ(pk) = 150C: TC is
0.5
THERMALLY LIMITED @ TC = 25C variable depending on conditions. Second breakdown pulse
0.1 (SINGLE PULSE) limits are valid for duty cycles to 10% provided TJ(pk)
0.05 150C, TJ(pk) may be calculated from the data in
0.02
BD787 (NPN) BD788 (PNP) 60 V reduce the power that can be handled to values less than the
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
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180
BD787 BD788
2000 200
VCC = 30 V TJ = 25C
1000 ts IC/IB = 10
700 IB1 = IB2 100
Cib
C, CAPACITANCE (pF)
500 TJ = 25C
70
t, TIME (ns)
300 50
200
100 tf 30 Cob
70
20
50
(NPN) (NPN)
30 (PNP) (PNP)
20 10
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
NPN NPN
BD787 BD788
400 200
300 TJ = 150C VCE = 1.0 V VCE = 1.0 V
VCE = 3.0 V TJ = 150C VCE = 3.0 V
200 25C 100
70 25C
100 -55C
50
70 -55C
30
50
20
30
20 10
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
2.0 2.0
TJ = 25C TJ = 25C
1.6 1.6
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
1.2 1.2
VBE(sat) @ IC/IB = 10 VBE(sat) @ IC/IB = 10

0.8 0.8
VBE(on) @ VCE = 3.0 V VBE @ VCE = 3.0 V
0.4 0.4

0 0
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
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181
BD787 BD788
+2.5 +2.5

*APPLIES FOR IC/IB hFE/3 *APPLIES FOR IC/IB hFE/3
+2.0 +2.0
+1.5 +1.5
+1.0 +1.0
*VC FOR VCE(sat) *VC FOR VCE(sat) 25C to 150C
+0.5 25C to 150C +0.5
0 0 - 55C to 25C
-0.5 - 55C to 25C
-0.5
-1.0 -1.0 25C to 150C
25C to 150C
-1.5 VB FOR VBE -1.5 VB FOR VBE
-2.0 -2.0 - 55C to 25C
- 55C to 25C
-2.5 -2.5
0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0
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182
ON Semiconductor
NPN
Plastic High Power Silicon BD809
PNP
Transistor BD810
. . . designed for use in high power audio amplifiers utilizing
complementary or quasi complementary circuits.
10 AMPERE
DC Current Gain POWER TRANSISTORS
hFE = 30 (Min) @ IC = 2.0 Adc PNP SILICON

60, 80 VOLTS
MAXIMUM RATINGS
90 WATTS





Collector Current IC 10 Adc


Total Device Dissipation TC = 25C PD 90 Watts

C

Temperature Range

CASE 221A09
TO220AB

May, 2001 Rev. 0 BD809/D
BD809 BD810



(IC = 0.1 Adc, IB = 0)
BVCEO
80

Vdc


(VCB = 80 Vdc, IE = 0)
ICBO
1.0
mAdc


(VBE = 5.0 Vdc, IC = 0)

DC Current Gain hFE
(IC = 2.0 A, VCE = 2.0 V) 30

(IC = 4.0 A, VCE = 2.0 V) 15


(IC = 3.0 Adc, IB = 0.3 Adc)
VCE(sat) 1.1 Vdc

BaseEmitter On Voltage* VBE(on) 1.6 Vdc
(IC = 4.0 Adc, VCE = 2.0 Vdc)


fT 1.5 MHz
90
.5 ms 80
1 ms
10 5 ms 1 ms
70
60
3 dc 50
40
1
30
0.3 20
10
0.1 0
1 3 10 30 100 0 25 50 75 100 125 150 175
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) TC, CASE TEMPERATURE (C)
Figure 1. Active Region DC Safe Operating Area Figure 2. PowerTemperature Derating Curve
(see Note 1)
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184
BD809 BD810
NPN PNP
BD809 BD810
500 500
TJ = 150C
200 25C 200 TJ = 150C

25C
100 100
-55C -55C
50 50
20 20
VCE = 2.0 V
10 10 VCE = 2.0 V
5.0 5.0
0.2 0.5 1.0 2.0 5.0 10 20 0.2 0.5 1.0 2.0 5.0 10 20
2.0 2.0

1.8 TJ = 25C 1.8 TJ = 25C
1.6 1.6
1.4 1.4
1.2 1.2
1.0 IC = 1.0 A 1.0 IC = 1.0 A 4.0 A 8.0 A
0.8 0.8
4.0 A 8.0 A
0.6 0.6
0.4 0.4
0.2 0.2
0 0
5.0 10 20 50 100 200 500 1000 2000 5000 5.0 10 20 50 100 200 500 1000 2000 5000
2.8 2.8
2.4 TJ = 25C 2.4 TJ = 25C

V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0
1.6 1.6
1.2 1.2
VBE(sat) = IC/IB = 10 VBE(sat) @ IC/IB = 10
0.8 0.8
0.4 0.4
0 0
0.2 0.5 1.0 2.0 5.0 10 20 0.2 0.5 1.0 2.0 5.0 10 20
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185
BD809 BD810
1.0
r(t), NORMALIZED EFFECTIVE TRANSIENT 0.7 D = 0.5
0.5
0.2
THERMAL RESISTANCE
0.3
0.2 0.1
0.1 0.05 SINGLE P(pk)

0.02 JC(t) = r(t) JC PULSE
0.07
0.03 SINGLE PULSE t2
READ TIME AT t1
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 20 30 50 100 200 300 500 1000
t, PULSE WIDTH (ms)
Note 1: The data of Figure 1 is based on TJ(pk) = 150C; TC is

There are two limitations on the power handling ability of variable depending on conditions. Second breakdown pulse
a transistor: average junction temperature and second limits are valid for duty cycles to 10% provided TJ(pk)
breakdown. Safe operating area curves indicate IC VCE 150C. At high case temperatures, thermal limitations
limits of the transistor that must be observed for reliable will reduce the power that can be handled to values less than
operation, i.e., the transistor must not be subjected to greater the limitations imposed by second breakdown.
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186
ON Semiconductor
NPN
Complementary Silicon Plastic BDV65B
PNP
Power Darlingtons BDV64B
. . . for use as output devices in complementary general purpose
DARLINGTONS
HFE = 1000 (min.) @ 5 Adc 10 AMPERES
Monolithic Construction with Builtin Base Emitter Shunt Resistors COMPLEMENTARY

SILICON
MAXIMUM RATINGS

POWER TRANSISTORS
6080100120 VOLTS
125 WATTS


VCEO
VCB
100
100
Vdc
Vdc

EmitterBase Voltage

VEB
IC
5.0
10
Vdc
Adc

Base Current
Peak
IB
20
0.5 Adc


@ TC = 25C

Derate above 25C
PD
125
1.0
Watts
W/C


Temperature Range
CASE 340D02
SOT 93, TO218 TYPE


Characteristic

Symbol
JC
Max
1.0
Unit
C/W
1.0
0.8
DERATING FACTOR
0.6
0.4
0.2
0
0 25 50 75 100 125 150

March, 2001 Rev. 10 BDV65B/D
BDV65B BDV64B


OFF CHARACTERISTICS


(IC = 30 mAdc, IB = 0)


(VCE = 50 Vdc, IB = 0)

(VCB = 100 Vdc, IE = 0)


(VCB = 50 Vdc, IE = 0, TC = 150C)
ICBO 2.0 mAdc

(VBE = 5.0 Vdc, IC = 0)

ON CHARACTERISTICS

DC Current Gain hFE 1000
(IC = 5.0 Adc, VCE = 4.0 Vdc)


(IC = 5.0 Adc, IB = 0.02 Adc)
VCE(sat) 2.0 Vdc

BaseEmitter Saturation Voltage VBE(on) 2.5 Vdc
(IC = 5.0 Adc, VCE = 4.0 Vdc)
NPN PNP
10K
VCE = 4 V
10K
1K
1K
4 1
0.1 1 10 0.1 1 10
IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)
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188
BDV65B BDV64B
10 10
V, VOLTAGE (V)
V, VOLTAGE (V)
1 VBE(sat) @ IC/IB = 250 1 VBE(sat) @ IC/IB = 250
0.1 0.1
0.1 1 10 0.1 1 10
Figure 4. On Voltages Figure 5. On Voltages

100 s a transistor: average junction temperature and second
50
20
5.0 ms 1.0 ms limits of the transistor that must be observed for reliable
10 dc operation i.e., the transistor must not be subjected to greater
5 dissipation than the curves indicate.
SECONDARY BREAKDOWN The data of Figure 6 is based on TJ(pk) = 150C, TC is
LIMITED @ TJ 150C variable depending on conditions. Second breakdown pulse
1 THERMAL LIMIT @ TC = 25C
BONDING WIRE LIMIT
BDV65B, BDV64B Figure 7. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
1 10 30 50 100
VCE, COLLECTOR-EMITTER VOLTAGE (V)
1.0
D = 0.5
0.5
0.2
(NORMALIZED)
0.2
0.1 P(pk)
0.1 ZJC(t) = r(t) RJC
0.05 RJC = 1.0C/W MAX
0.02 t1 PULSE TRAIN SHOWN
0.03 t2 READ TIME AT t1
0.01 TJ(pk) - TC = P(pk) ZJC(t)
(SINGLE PULSE) DUTY CYCLE, D = t1/t2
0.01
0.01 0.05 0.1 0.5 1.0 5 10 50 100 500 1000
t, TIME (ms)
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189
ON Semiconductor
NPN
Darlington Complementary BDW42 *
PNP
Silicon Power Transistors
. . . designed for general purpose and low speed switching BDW46
BDW47 *
applications.
High DC Current Gain hFE = 2500 (typ.) @ IC = 5.0 Adc.
Collector Emitter Sustaining Voltage @ 30 mAdc: *ON Semiconductor Preferred Device
VCEO(sus) = 80 Vdc (min.) BDW46
100 Vdc (min.) BDW42/BDW47 DARLINGTON
Low Collector Emitter Saturation Voltage 15 AMPERE
COMPLEMENTARY
VCE(sat) = 2.0 Vdc (max.) @ IC = 5.0 Adc
SILICON
3.0 Vdc (max.) @ IC = 10.0 Adc POWER TRANSISTORS
Monolithic Construction with BuiltIn Base Emitter Shunt resistors
80100 VOLTS
TO220AB Compact Package 85 WATTS

MAXIMUM RATINGS

BDW42

Rating
Symbol
VCEO
BDW46
80
BDW47
100
Unit
Vdc


EmitterBase Voltage
VCB
VEB
80
5.0
100 Vdc
Vdc


Base Current

IC
IB
15
0.5
Adc
Adc

@ TC = 25C


Derate above 25C
PD
85
0.68
Watts
W/C
CASE 221A09
TO220AB


Temperature Range


90
RJC 1.47 C/W
80
70
60
50
40
30
20
10
0
25 50 75 100 125 150
Figure 1. Power Temperature Derating Curve


March, 2001 Rev. 9 BDW42/D
BDW42 BDW46 BDW47

OFF CHARACTERISTICS

Collector Emitter Sustaining Voltage (1) VCEO(sus) Vdc

(IC = 30 mAdc, IB = 0) BDW46 80
BDW42/BDW47 100


(VCE = 40 Vdc, IB = 0)

BDW46
ICEO
2.0
mAdc

(VCE = 50 Vdc, IB = 0) BDW42/BDW47 2.0

(VCB = 80 Vdc, IE = 0) BDW41/BDW46 1.0

(VCB = 100 Vdc, IE = 0)


BDW42/BDW47
IEBO

1.0
2.0 mAdc

(VBE = 5.0 Vdc, IC = 0)

DC Current Gain hFE
(IC = 5.0 Adc, VCE = 4.0 Vdc) 1000

(IC = 10 Adc, VCE = 4.0 Vdc) 250


(IC = 10 Adc, IB = 50 mAdc)

(IC = 5.0 Adc, IB = 10 mAdc)
VCE(sat)

2.0
3.0
Vdc


(IC = 10 Adc, VCE = 4.0 Vdc)
VBE(on) 3.0 Vdc
SECOND BREAKDOWN (2)

Second Breakdown Collector

IS/b Adc

Current with Base Forward Biased
BDW42 VCE = 28.4 Vdc 3.0

VCE = 40 Vdc 1.2

BDW46/BDW47 VCE = 22.5 Vdc 3.8
VCE = 36 Vdc 1.2


Magnitude of common emitter small signal short circuit current transfer ratio fT 4.0 MHz


Output Capacitance Cob pF
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) BDW42 200


BDW46/BDW47
hfe

300
300

(1) Pulse Test: Pulse Width = 300 s, Duty Cycle = 2.0%.
(2) Pulse Test non repetitive: Pulse Width = 250 ms.
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191
BDW42 BDW46 BDW47
5.0
VCC ts
RB AND RC VARIED TO OBTAIN DESIRED CURRENT LEVELS - 30 V 3.0
D1 MUST BE FAST RECOVERY TYPES, e.g.: 2.0
1N5825 USED ABOVE IB 100 mA
RC
MSD6100 USED BELOW IB 100 mA SCOPE tf
1.0
TUT
t, TIME (s)
0.7

V2 RB
0.5
APPROX
+ 8.0 V 51 D1 0.3
8.0 k 150 tr
0 0.2 VCC = 30 V
V1 + 4.0 V IC/IB = 250
APPROX 0.1 IB1 = IB2
25 s
- 12 V for td and tr, D1 id disconnected 0.07 TJ = 25C td @ VBE(off) = 0 V
tr, tf 10 ns
and V2 = 0 0.05
For NPN test circuit reverse all polarities 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
DUTY CYCLE = 1.0%
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192
BDW42 BDW46 BDW47
1.0

0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
P(pk)
0.1 0.05 RJC(t) = r(t) RJC
0.07 0.02 RJC = 1.92C/W
0.03 SINGLE PULSE t2
READ TIME AT t1
0.02 0.01
DUTY CYCLE, D = t1/t2 TJ(pk) - TC = P(pk) RJC(t)
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000

50 50
0.1 ms 0.1 ms
20 20
10 TJ = 25C 10 TJ = 25C
1.0 ms 1.0 ms
0.5 ms 0.5 ms
5.0 5.0
SECOND BREAKDOWN LIMIT dc SECOND BREAKDOWN LIMIT
2.0 BONDING WIRE LIMIT 2.0 BONDING WIRE LIMIT
dc
1.0 THERMAL LIMITED 1.0 THERMAL LIMITED
@ TC = 25C (SINGLE PULSE) @ TC = 25C (SINGLE PULSE)
0.5 0.5
0.2 0.2
0.1 0.1 BDW46
BDW42 BDW47
0.05 0.05
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
Figure 5. BDW42 Figure 6. BDW46 and BDW47
There are two limitations on the power handling ability of a Second breakdown pulse limits are valid for duty cycles to
transistor: average junction temperature and second 10% provided TJ(pk) 200C. TJ(pk) may be calculated from
breakdown. Safe operating area curves indicate IC VCE limits the data in Figure 4. At high case temperatures, thermal
of the transistor that must be observed for reliable operation; limitations will reduce the power that can be handled to values
i.e., the transistor must not be subjected to greater dissipation less than the limitations imposed by second breakdown.
than the curves indicate. The data of Figure 5 and 6 is based on *Linear extrapolation
TJ(pk) = 200C; TC is variable depending on conditions.
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193
BDW42 BDW46 BDW47
10,000 300
5000 TJ = + 25C
3000 200
2000
C, CAPACITANCE (pF)
1000
500
100 Cob
300 TJ = 25C
200
VCE = 3.0 V
70 Cib
100 IC = 3.0 A
50 50
30 BDW46, 47 (PNP) BDW46, 47 (PNP)
20 BDW42 (NPN) BDW42 (NPN)
10 30
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
BDW40, 41, 42 (NPN) BDW45, 46, 47 (PNP)
20,000 20,000
VCE = 3.0 V VCE = 3.0 V
10,000 10,000
7000
5000 TJ = 150C 5000 TJ = 150C

3000 3000
2000 2000 25C
25C
1000 1000
-55C 700
500 -55C
500
300 300
200 200
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10

3.0
3.0
TJ = 25C
TJ = 25C
2.6
2.6
IC = 2.0 A 4.0 A 6.0 A
IC = 2.0 A 4.0 A 6.0 A
2.2
2.2
1.8
1.8
1.4
1.4
1.0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 1.0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
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BDW42 BDW46 BDW47
BDW40, 41, 42 (NPN) BDW45, 46, 47 (PNP)
3.0 3.0
TJ = 25C TJ = 25C
2.5 2.5
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0

1.5 1.5 VBE @ VCE = 4.0 V
VBE @ VCE = 4.0 V VBE(sat) @ IC/IB = 250

1.0 1.0
0.5 0.5
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
+5.0 +5.0
V, TEMPERATURE COEFFICIENT (mV/ C)
+4.0 +4.0
*IC/IB 250 *IC/IB 250
+3.0 +3.0
+25C to 150C
+2.0 25C to 150C +2.0
+1.0 +1.0
-55C to 25C
0 0
-2.0 -2.0
25C to 150C VB for VBE -55C to +25C
-3.0 VB for VBE -3.0 +25C to 150C -55C to +25C
-4.0 -55C to 25C -4.0
-5.0 -5.0
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10
105 105
104 104

VCE = 30 V VCE = 30 V
103 103
102 102
TJ = 150C TJ = 150C
101 101
100C
100 100 100C
25C
25C
10-1 10-1
+0.6 +0.4 +0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -0.6 -0.4 -0.2 0 +0.2 +0.4 +0.6 +0.8 +1.0 +1.2 + 1.4
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195
BDW42 BDW46 BDW47
NPN COLLECTOR PNP COLLECTOR

BDW42 BDW46
BDW47
BASE BASE
8.0 k 60 8.0 k 60
EMITTER EMITTER
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196
ON Semiconductor
NPN
Darlington Complementary BDX33B
Silicon Power Transistors
. . . designed for general purpose and low speed switching
BDX33C*
applications. PNP
High DC Current Gain BDX34B
hFE = 2500 (typ.) at IC = 4.0
*
CollectorEmitter Sustaining Voltage at 100 mAdc BDX34C
VCEO(sus) = 80 Vdc (min.) BDX33B, 34B
100 Vdc (min.) BDX33C, 34C
Low CollectorEmitter Saturation Voltage DARLINGTON
VCE(sat) = 2.5 Vdc (max.) at IC = 3.0 Adc BDX33B, 10 AMPERE
33C/34B, 34C COMPLEMENTARY
Monolithic Construction with BuildIn BaseEmitter Shunt resistors SILICON
POWER TRANSISTORS
TO220AB Compact Package 80100 VOLTS
70 WATTS
MAXIMUM RATINGS

Rating Symbol
BDX33B
BDX34B
BDX33C
BDX34C Unit


VCEO 80 100 Vdc


EmitterBase Voltage
VCB
VEB
80
5.0
100 Vdc
Vdc


Peak
IC 10
15
Adc


Total Device Dissipation PD CASE 221A09
@ TC = 25C 70 Watts

TO220AB


Temperature Range



March, 2001 Rev. 9 BDX33B/D
BDX33B BDX33C BDX34B BDX34C
80

60
40
20
0
0 20 40 60 80 100 120 140 160
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198

OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage1 VCEO(sus) Vdc

(IC = 100 mAdc, IB = 0) BDX33B/BDX34B 80
BDX33C/BDX34C 100

CollectorEmitter Sustaining Voltage1

(IC = 100 mAdc, IB = 0, RBE = 100) BDX33B/BDX34B
VCER(sus)
80
Vdc

BDX33C/BDX33C 100

CollectorEmitter Sustaining Voltage1 VCEX(sus) Vdc
(IC = 100 mAdc, IB = 0, VBE = 1.5 Vdc) BDX33B/BDX34B 80


BDX33C/BDX34C
ICEO
100
mAdc

(VCE = 1/2 rated VCEO, IB = 0) TC = 25C 0.5
TC = 100C 10


(VCB = rated VCBO, IE = 0) TC = 25C
ICBO
1.0
mAdc

TC = 100C 5.0

Emitter Cutoff Current IEBO 10 mAdc
(VBE = 5.0 Vdc, IC = 0)
ON CHARACTERISTICS
DC Current Gain1

hFE 750

(IC = 3.0 Adc, VCE = 3.0 Vdc) BDX33B, 33C/34B, 34C


(IC = 3.0 Adc, IB = 6.0 mAdc) BDX33B, 33C/34B, 34C

(IC = 3.0 Adc, VCE = 3.0 Vdc) BDX33B, 33C/34B, 34C

Diode Forward Voltage
1
(IC = 8.0 Adc)

Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
VF 4.0 Vdc
2 Pulse Test non repetitive: Pulse Width = 0.25 s.
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199
1.0
0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
P(pk)
0.1 0.05 RJC(t) = r(t) RJC
0.07 0.02 RJC = 1.92C/W
t1 SINGLE PULSE TRAIN SHOWN
0.03 SINGLE PULSE t2 PULSE READ TIME AT t1
0.02 0.01
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
20 100 20 100
10 s 10 s
500 s IC, COLLECTOR CURRENT (AMP) 500 s
5.0 ms 5.0 ms
5.0 5.0
1.0 ms 1.0 ms
TC = 25C dc TC = 25C dc
2.0 2.0
1.0 1.0
BONDING WIRE LIMITED BONDING WIRE LIMITED
0.5 THERMALLY LIMITED @ TC = 25C 0.5 THERMALLY LIMITED @ TC = 25C
(SINGLE PULSE) (SINGLE PULSE)
0.2 0.2 SECOND BREAKDOWN LIMITED
0.1 CURVES APPLY BELOW RATED VCEO 0.1 CURVES APPLY BELOW RATED VCEO
0.05 BDX34B 0.05 BDX33B
BDX34C BDX33C
0.02 0.02
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
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200
There are two limitations on the power handling ability of conditions. Second breakdown pulse limits are valid for
a transistor: average junction temperature and second duty cycles to 10% provided TJ(pk) = 150C. TJ(pk) may be
breakdown. Safe operating area curves indicate IC VCE calculated from the data in Figure 4. At high case
limits of the transistor that must be observed for reliable temperatures, thermal limitations will reduce the power that
operation, i.e., the transistor must not be subjected to greater can be handled to values less than the limitations imposed by
dissipation than the curves indicate. The data of Figure 3 is second breakdown.
based on TJ(pk) = 150C; TC is variable depending on
10,000 300
5000 TJ = 25C
3000 200
2000
C, CAPACITANCE (pF)
1000
500 TJ = 25C
100 Cob
300 VCE = 4.0 Vdc
200 IC = 3.0 Adc
70 Cib
100
50 50
30 PNP PNP
20 NPN NPN
10 30
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
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NPN PNP
BDX33B, 33C BDX34B, 34C
20,000 20,000
VCE = 4.0 V VCE = 4.0 V
10,000 10,000

5000 TJ = 150C 5000 TJ = 150C
3000 3000
2000 2000 25C
25C
1000 1000
-55C -55C
500 500
300 300
200 200
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
3.0 3.0
2.6 2.6
IC = 2.0 A 4.0 A 6.0 A IC = 2.0 A 4.0 A 6.0 A
2.2 2.2
1.8 1.8
1.4 1.4
1.0 1.0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
3.0 3.0
TJ = 25C TJ = 25C
2.5 2.5
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0
1.5 VBE(sat) @ IC/IB = 250 1.5 VBE @ VCE = 4.0 V

1.0 1.0
0.5 0.5
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
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ON Semiconductor
NPN
Plastic Medium-Power BDX53B
Complementary Silicon
BDX53C
Transistors PNP
. . . designed for generalpurpose amplifier and lowspeed BDX54B
High DC Current Gain BDX54C
hFE = 2500 (Typ) @ IC = 4.0 Adc
Collector Emitter Sustaining Voltage @ 100 mAdc
VCEO(sus) = 80 Vdc (Min) BDX53B, 54B DARLINGTON
= 100 Vdc (Min) BDX53C, 54C 8 AMPERE
Low CollectorEmitter Saturation Voltage COMPLEMENTARY
SILICON
VCE(sat) = 2.0 Vdc (Max) @ IC = 3.0 Adc
POWER TRANSISTORS
= 4.0 Vdc (Max) @ IC = 5.0 Adc 80100 VOLTS
Monolithic Construction with BuiltIn BaseEmitter Shunt Resistors 65 WATTS
MAXIMUM RATINGS

BDX53B BDX53C

Rating
Symbol
VCEO
BDX54B
80
BDX54C
100
Unit
Vdc



Peak 12

Base Current

IB
PD
0.2
60
Adc
Watts
CASE 221A09
TO220AB


Temperature Range



RJA
RJC
70
70
C/W
C/W

March, 2001 Rev. 9 BDX53B/D
TA TC
4.0 80

3.0 60
TC
2.0 40
TA
1.0 20
0
0 20 40 60 80 100 120 140 160
T, TEMPERATURE (C)
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204

OFF CHARACTERISTICS


(IC = 100 mAdc, IB = 0) BDX53B, BDX54B 80
BDX53C, BDX54C 100


(VCE = 40 Vdc, IB = 0)

BDX53B, BDX54B
ICEO
0.5
mAdc

(VCE = 50 Vdc, IB = 0) BDX53C, BDX54C 0.5

(VCB = 80 Vdc, IE = 0) BDX53B, BDX54B 0.2

(VCB = 100 Vdc, IE = 0)
BDX53C, BDX54C 0.2
DC Current Gain

(IC = 3.0 Adc, VCE = 3.0 Vdc)
hFE 750

(IC = 3.0 Adc, IB = 12 mAdc) 2.0

4.0


(IC = 3.0 Adc, IC = 12 mA)

VBE(sat) 2.5 Vdc


SmallSignal Current Gain hfe 4.0
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) BDX53B, 53C
BDX54B, 54C
Cob

300
200
pF
VCC 5.0
RB AND RC VARIED TO OBTAIN DESIRED CURRENT LEVELS -30 V ts
D1 MUST BE FAST RECOVERY TYPES, e.g.: 3.0
RC
TUT 1.0 tf
t, TIME (s)
V2 RB 0.7

APPROX 0.5
+8.0 V 51 D1 8.0 k 120 0.3
0 tr
0.2 VCC = 30 V
V1 +4.0 V
IC/IB = 250
APPROX 25 s
-12 V for td and tr, D1 is disconnected 0.1 IB1 = IB2
and V2 = 0 0.07 TJ = 25C td @ VBE(off) = 0 V
tr, tf 10 ns
For NPN test circuit reverse all polarities 0.05
DUTY CYCLE = 1.0% 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
Figure 3. Switching Times
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205
1.0

0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
P(pk)
0.1 0.05 RJC(t) = r(t) RJC
0.07 0.02 RJC = 1.92C/W
t1 SINGLE PULSE TRAIN SHOWN
0.03 SINGLE PULSE t2 PULSE READ TIME AT t1
0.02 0.01
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000

100 s
10 500 s a transistor average junction temperature and second

2.0 1.0 ms
dc
TJ = 150C operation, i.e., the transistor must not be subjected to greater
1.0 BONDING WIRE LIMITED dissipation than the curves indicate.
THERMALLY LIMITED @ TC = 25C The data of Figure 5 is based on TJ(pk) = 150C; TC is
0.5
(SINGLE PULSE) variable depending on conditions. Second breakdown pulse
0.1 150C. TJ(pk) may be calculated from the data in
BDX53B, BDX54B
BDX53C, BDX54C reduce the power that can be handled to values less than the
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
10,000 300
5000 TJ = + 25C
3000 200
2000
C, CAPACITANCE (pF)
1000
500
100 Cob
300 TJ = 25C
200
VCE = 3.0 V
70 Cib
100 IC = 3.0 A
50 50
30 PNP PNP
20 NPN NPN
10 30
1.0 2.0 5.0 10 20 50 100 200 500 1000 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
Figure 6. Small-Signal Current Gain Figure 7. Capacitance
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206
NPN PNP
BDX53B, 53C BDX54B, 54C
20,000 20,000
VCE = 4.0 V VCE = 4.0 V
10,000 10,000

5000 TJ = 150C 5000 TJ = 150C
3000 3000
2000 2000 25C
25C
1000 1000
-55C -55C
500 500
300 300
200 200
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
3.0 3.0
2.6 2.6
IC = 2.0 A 4.0 A 6.0 A IC = 2.0 A 4.0 A 6.0 A
2.2 2.2
1.8 1.8
1.4 1.4
1.0 1.0
0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
3.0 3.0
TJ = 25C TJ = 25C
2.5 2.5
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0 2.0
1.5 VBE(sat) @ IC/IB = 250 1.5 VBE @ VCE = 4.0 V

1.0 1.0
0.5 0.5
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
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NPN PNP
BDX53B, BDX53C BDX54B, BDX54C
+5.0 +5.0

+4.0 +4.0
*IC/IB hFE/3 *IC/IB hFE/3
+3.0 +3.0
+2.0 25C to 150C +2.0 25C to 150C
+1.0 +1.0
-55C to 25C -55C to 25C
0 0
-2.0 -2.0
25C to 150C 25C to 150C
-3.0 VB for VBE -3.0 VB for VBE
-4.0 -55 to 150C -4.0 -55 to 150C
-5.0 -5.0
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
105 105
104 104

VCE = 30 V VCE = 30 V
103 103
102 102
TJ = 150C
TJ = 150C
101 101
100C
100C
100 100
25C
25C
10-1 10-1
-0.6 -0.4 -0.2 0 +0.2 +0.4 +0.6 +0.8 +1.0 +1.2 + 1.4 +0.6 +0.4 +0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4
VBE, BASEEMITTER VOLTAGE (VOLTS) VBE, BASEEMITTER VOLTAGE (VOLTS)
NPN COLLECTOR PNP COLLECTOR

BDX53B BDX54B
BDX53C BDX54C
BASE BASE
8.0 k 120 8.0 k 120
EMITTER EMITTER
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ON Semiconductor
BU323Z
NPN Silicon Power Darlington
High Voltage Autoprotected AUTOPROTECTED
DARLINGTON
The BU323Z is a planar, monolithic, highvoltage power 10 AMPERES
Darlington with a builtin active zener clamping circuit. This device is 360450 VOLTS CLAMP
specifically designed for unclamped, inductive applications such as 150 WATTS
Electronic Ignition, Switching Regulators and Motor Control, and
exhibit the following main features:
Integrated HighVoltage Active Clamp
Tight Clamping Voltage Window (350 V to 450 V) Guaranteed
Over the 40C to +125C Temperature Range
Clamping Energy Capability 100% Tested in a Live
Ignition Circuit 360 V
CLAMP
High DC Current Gain/Low Saturation Voltages
Specified Over Full Temperature Range
Design Guarantees Operation in SOA at All Times
Offered in Plastic SOT93/TO218 Type or CASE 340D02
SOT93/TO218 TYPE
TO220 Packages
MAXIMUM RATINGS




VCEO
VEBO
350
6.0
Vdc
Vdc


Peak

IC
ICM
10
20
Adc


Peak IBM 6.0

Total Power Dissipation (TC = 25C) PD 150 Watts

Operating and Storage Junction Temperature Range

Characteristic

Symbol
RJC
Max
1.0
Unit
C/W

Maximum Lead Temperature for Soldering Purposes:

1/8 from Case for 5 Seconds
TL 260 C

March, 2001 Rev. 10 BU323Z/D
BU323Z



CollectorEmitter Clamping Voltage (IC = 7.0 A) VCLAMP 350 450 Vdc

(TC = 40C to +125C)

CollectorEmitter Cutoff Current ICEO 100 Adc

(VCE = 200 V, IB = 0)

EmitterBase Leakage Current IEBO 50 mAdc
(VEB = 6.0 Vdc, IC = 0)


(IC = 8.0 Adc, IB = 100 mAdc)
(IC = 10 Adc, IB = 0.25 Adc)
VBE(sat)

2.2
2.5
Vdc


(IC = 7.0 Adc, IB = 70 mAdc)
VCE(sat)
1.6
Vdc

(TC = 125C) 1.8
(IC = 8.0 Adc, IB = 0.1 Adc) 1.8

(IC = 10 Adc, IB = 0.25 Adc)
(TC = 125C)

2.1
1.7

(IC = 5.0 Adc, VCE = 2.0 Vdc) (TC = 40C to +125C) 1.1 2.1

(IC = 8.0 Adc, VCE = 2.0 Vdc) 1.3 2.3

Diode Forward Voltage Drop VF 2.5 Vdc

(IF = 10 Adc)

DC Current Gain hFE
(IC = 6.5 Adc, VCE = 1.5 Vdc) (TC = 40C to +125C) 150

(IC = 5.0 Adc, VCE = 4.6 Vdc) 500 3400


Current Gain Bandwidth

fT 2.0 MHz


Output Capacitance Cob 200 pF
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)

Input Capacitance

(VEB = 6.0 V)

Cib 550 pF
CLAMPING ENERGY (see notes)

Repetitive NonDestructive Energy Dissipated at turnoff:
(IC = 7.0 A, L = 8.0 mH, RBE = 100 ) (see Figures 2 and 4)
WCLAMP 200 mJ

SWITCHING CHARACTERISTICS: Inductive Load (L = 10 mH)

Fall Time tfi 625 ns
(IC = 6.5 A, IB1 = 45 mA,
s

Storage Time VBE(off) = 0, RBE(off) = 0, tsi 10 30
VCC = 14 V V, VZ = 300 V)
Crossover Time tc 1.7 s
(1) Pulse Test: Pulse Width 300 s, Duty Cycle = 2.0%.
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BU323Z
IC
L INDUCTANCE
INOM = 6.5 A MERCURY CONTACTS (8 mH)
WETTED RELAY
IC CURRENT
Output transistor turns on: IC = 40 mA VCE SOURCE
MONITOR
(VGATE)
High Voltage Circuit turns on: IC = 20 mA

RBE = 100
0.1
IC
Avalanche diode turns on: IC = 100 A IB CURRENT NON
VBEoff MONITOR
SOURCE INDUCTIVE
IB2 SOURCE
VCE
250 V 300 V 340 V
VCLAMP NOMINAL
Icer Leakage Current = 400 V
Figure 1. IC = f(VCE) Curve Shape Figure 2. Basic Energy Test Circuit
By design, the BU323Z has a builtin avalanche diode and The bias parameters, VCLAMP, IB1, VBE(off), IB2, IC, and
a special high voltage driving circuit. During an the inductance, are applied according to the Device Under
autoprotect cycle, the transistor is turned on again as soon Test (DUT) specifications. VCE and IC are monitored by the
as a voltage, determined by the zener threshold and the test system while making sure the load line remains within
network, is reached. This prevents the transistor from going the limits as described in Figure 4.
into a Reverse Bias Operating limit condition. Therefore, the Note: All BU323Z ignition devices are 100% energy
device will have an extended safe operating area and will tested, per the test circuit and criteria described in Figures 2
always appear to be in FBSOA. Because of the builtin and 4, to the minimum guaranteed repetitive energy, as
zener and associated network, the IC = f(VCE) curve exhibits specified in the device parameter section. The device can
an unfamiliar shape compared to standard products as sustain this energy on a repetitive basis without degrading
shown in Figure 1. any of the specified electrical characteristics of the devices.
The units under test are kept functional during the complete
test sequence for the test conditions described:
IC(peak) = 7.0 A, ICH = 5.0 A, ICL = 100 mA, IB = 100 mA,
RBE = 100 , Vgate = 280 V, L = 8.0 mH
10
300s
1ms
TC = 25C
1
10ms
250ms
0.1
THERMAL LIMIT
0.01
CURVES APPLY BELOW
RATED VCEO
0.001
10 100 340V 1000
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211
BU323Z
IC
ICPEAK The shaded area represents the amount of energy the de-
IC HIGH vice can sustain, under given DC biases (IC/IB/VBE(off)/
RBE), without an external clamp; see the test schematic dia-
gram, Figure 2.
The transistor PASSES the Energy test if, for the inductive
load and ICPEAK/IB/VBE(off) biases, the VCE remains outside
the shaded area and greater than the VGATE minimum limit,
IC LOW Figure 4a.
VCE
(a) VGATE MIN
IC
ICPEAK
IC HIGH
IC LOW
VCE
(b) VGATE MIN The transistor FAILS if the VCE is less than the VGATE
(minimum limit) at any point along the VCE/IC curve as
IC
shown on Figures 4b, and 4c. This assures that hot spots and
ICPEAK uncontrolled avalanche are not being generated in the die,
IC HIGH and the transistor is not damaged, thus enabling the sustained
energy level required.
IC LOW
VCE
(c) VGATE MIN
IC
ICPEAK
IC HIGH
The transistor FAILS if its Collector/Emitter breakdown

voltage is less than the VGATE value, Figure 4d.
IC LOW
VCE
(d) VGATE MIN
Figure 4. Energy Test Criteria for BU323Z
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212
BU323Z
10000 10000
TYPICAL
TJ = 125C

1000 1000
TYP - 6
-40C
TYP + 6
100 25C 100
VCE = 5 V, TJ = 25C
VCE = 1.5 V
10 10
100 1000 10000 100 1000 10000 100000
IC, COLLECTOR CURRENT (MILLIAMPS) IC, COLLECTOR CURRENT (MILLIAMPS)


5.0
2.4
4.5 TJ = 25C
IC = 3 A IC/IB = 150
2.2
4.0
2.0 TJ = 125C
3.5
1.8
3.0 5A 8A 1.6
2.5 10 A
1.4
2.0 1.2
7A
1.5 1.0
1.0 0.8 25C
0.5 0.6
0 0.4
1 10 100 0.1 1 10
IB, BASE CURRENT (MILLIAMPS) IC, COLLECTOR CURRENT (AMPS)
Figure 7. Collector Saturation Region Figure 8. CollectorEmitter Saturation Voltage
2.0 2.0
VBE(on), BASE-EMITTER VOLTAGE (VOLTS)
VCE = 2 VOLTS
IC/IB = 150
1.8 1.8
1.6
1.6 TJ = 25C
1.4 TJ = 25C
1.4
1.2
1.2 125C
1.0 125C
1.0 0.8
0.8 0.6
0.1 1 10 0.1 1 10
Figure 9. BaseEmitter Saturation Voltage Figure 10. BaseEmitter ON Voltages
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ON Semiconductor
BU406
NPN Power Transistors BU407
These devices are high voltage, high speed transistors for horizontal
deflection output stages of TVs and CRTs.
High Voltage: VCEV = 330 or 400 V 7 AMPERES
NPN SILICON
Fast Switching Speed: tf = 750 ns (max) POWER TRANSISTORS
Low Saturation Voltage: VCE(sat) = 1 V (max) @ 5 A 60 WATTS
Packaged in Compact JEDEC TO220AB 150 and 200 VOLTS
MAXIMUM RATINGS

Rating Symbol BU406 BU407 Unit


CollectorEmitter Voltage VCEV 400 330 Vdc

CollectorBase Voltage VCBO 400 330 Vdc

Emitter Base Voltage VEBO 6 Vdc


Peak Repetitive 10
Peak (10 ms) 15

Base Current

Total Device Dissipation, TC = 25C
IB
PD
4
60
Adc
Watts

Derate above TC = 25C 0.48 W/C

Operating and Storage TJ, Tstg 65 to 150 C
Junction Temperature Range



Thermal Resistance, Junction to Ambient RJA 70 C/W CASE 221A09

Lead Temperature for Soldering Purposes: TL 275 C TO220AB
1/8 from Case for 5 Seconds

March, 2001 Rev. 4 BU406/D
BU406 BU407


OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage(1) BU406 VCEO(sus) 200 Vdc

(IC = 100 mAdc, IB = 0) BU407 150

Collector Cutoff Current ICES mAdc

(VCE = Rated VCEV, VBE = 0) 5
(VCE = Rated VCEO + 50 Vdc, VBE = 0) 0.1

(VCE = Rated VCEO + 50 Vdc, VBE = 0, TC = 150C) 1


(VEB = 6 Vdc, IC = 0)
BU406, BU407 IEBO 1 mAdc

CollectorEmitter Saturation Voltage (IC = 5 Adc, IB = 0.5 Adc) VCE(sat) 1 Vdc

BaseEmitter Saturation Voltage (IC = 5 Adc, IB = 0.5 Adc) VBE(sat) 1.2 Vdc

Forward Diode Voltage (IEC = 5 Adc) D only VEC 2 Volts


CurrentGain Bandwidth Product fT 10 MHz
(IC = 0.5 Adc, VCE = 10 Vdc, ftest = 20 MHz)

Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 1 MHz)
Cob 80 pF


Inductive Load Crossover Time tc 0.75 s

(VCC = 40 Vdc, IC = 5 Adc,
IB1 = IB2 = 0.5 Adc, L = 150 H)
100 10
70 TJ = 100C
dc
25C
50
1 BONDING WIRE LIMIT

30 VCE = 5 V THERMAL LIMIT
0.1
20
BU407
TC = 25C
BU406
10
0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 2 3 5 7 10 20 30 50 70 100 200
IC, COLLECTOR CURRENT (AMPS) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 11. DC Current Gain Figure 12. Maximum Rated Forward
Bias Safe Operating Area
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ON Semiconductor
BUD44D2
High Speed, High Gain Bipolar
NPN Power Transistor with POWER TRANSISTORS
Integrated Collector-Emitter 2 AMPERES

700 VOLTS
Diode and Built-in Efficient 25 WATTS
Antisaturation Network
The BUD44D2 is stateofart High Speed High gain BIPolar
transistor (H2BIP). High dynamic characteristics and lot to lot
minimum spread (150 ns on storage time) make it ideally suitable for
light ballast applications. Therefore, there is no need to guarantee an
hFE window.
Main features:
Low Base Drive Requirement
High Peak DC Current Gain (55 Typical) @ IC = 100 mA
Extremely Low Storage Time Min/Max Guarantees Due to the
H2BIP Structure which Minimizes the Spread
Integrated CollectorEmitter Free Wheeling Diode
Fully Characterized and Guaranteed Dynamic VCE(sat) CASE 36907
Six Sigma Process Providing Tight and Reproductible Parameter
Spreads
Its characteristics make it also suitable for PFC application.
MAXIMUM RATINGS

Rating Symbol Value Unit CASE 369A13


VCEO
VCBO
400
700
Vdc
Vdc

MINIMUM PAD SIZES REC-
CollectorEmitter Breakdown Voltage VCES 700 Vdc

OMMENDED FOR
EmitterBase Voltage VEBO 12 Vdc SURFACE MOUNTED

APPLICATIONS

Peak (1) ICM 5

6.7
Base Current Continuous IB 1 Adc 0.265

Base Current Peak (1) IBM 2
0.265

6.7
*Total Device Dissipation @ TC = 25C PD 25 Watt

*Derate above 25C 0.2 W/C

0.118 .070
1.8
Operating and Storage Temperature TJ, Tstg 65 to 150 C
30

THERMAL CHARACTERISTICS 1.6 1.6
0.063 0.063
C/W

Thermal Resistance 2.3 2.3
Junction to Case RJC 5 0.090 0.090

Junction to Ambient RJA 71.4

Maximum Lead Temperature for Soldering TL 260 C
Purposes: 1/8 from case for 5 seconds

March, 2001 Rev.2 BUD44D2/D
BUD44D2


OFF CHARACTERISTICS

CollectorEmitter Sustaining Voltage VCEO(sus) 400 470 Vdc

(IC = 100 mA, L = 25 mH)

CollectorBase Breakdown Voltage VCBO 700 920 Vdc

(ICBO = 1 mA)

EmitterBase Breakdown Voltage VEBO 12 14.5 Vdc
(IEBO = 1 mA)


(VCE = Rated VCEO, IB = 0)

@ TC = 25C
@ TC = 125C
ICEO 50
500
Adc

Collector Cutoff Current (VCE = Rated VCES, VEB = 0) @ TC = 25C ICES 50 Adc

@ TC = 125C 500
Collector Cutoff Current (VCE = 500 V, VEB = 0) @ TC = 125C 100

EmitterCutoff Current

(VEB = 10 Vdc, IC = 0)

IEBO 100 Adc
ON CHARACTERISTICS


(IC = 0.4 Adc, IB = 40 mAdc) @ TC = 25C 0.78 0.9
@ TC = 125C 0.65 0.8

(IC = 1 Adc, IB = 0.2 Adc)

@ TC = 25C
@ TC = 125C
0.87
0.76
1
0.9


(IC = 0.4 Adc, IB = 20 mAdc) @ TC = 25C 0.45 0.65
@ TC = 125C 0.67 1

(IC = 0.4 Adc, IB = 40 mAdc)

@ TC = 25C
@ TC = 125C
0.25
0.27
0.4
0.5

(IC = 1 Adc, IB = 0.2 Adc) @ TC = 25C 0.28 0.5

@ TC = 125C 0.35 0.6

DC Current Gain hFE

(IC = 0.4 Adc, VCE = 1 Vdc) @ TC = 25C 20 32


@ TC = 125C
@ TC = 25C
18
10
26
14

@ TC = 125C 7 9.5

(IC = 2 Adc, VCE = 5 Vdc) @ TC = 25C 8 11
DIODE CHARACTERISTICS

Forward Diode Voltage VEC 0.8 1 V

(IEC = 0.2 Adc) @ TC = 25C

(IEC = 0.2 Adc) @ TC = 125C 0.6

(IEC = 0.4 Adc) @ TC = 25C 0.9 1.2

(IEC = 1 Adc) @ TC = 25C 1.1 1.5

Forward Recovery Time (see Figure 22 bis) Tfr 415 ns
(IF = 0.2 Adc, di/dt = 10 A/s) @ TC = 25C

(IF = 0.4 Adc, di/dt = 10 A/s)

(IF = 1 Adc, di/dt = 10 A/s)
@ TC = 25C
@ TC = 25C
390
340
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BUD44D2


DYNAMIC SATURATION VOLTAGE

@ 1 s @ TC = 25C VCE(dsat) 3.3 V

IC = 0.4 A @ TC = 125C 6.8
Dynamic Saturation
IB1 = 40 mA

Voltage:
VCC = 300 V @ 3 s @ TC = 25C 0.5
Determined 1 s and

@ TC = 125C 1.3
3 s respectively
@ 1 s

after rising IB1 @ TC = 25C 4.4
reaches 90% of final IC = 1 A @ TC = 125C 12.8

IB1 IB1 = 0
0.2
2A
VCC = 300 V @ 3 s @ TC = 25C 0.5

@ TC = 125C 1.8



fT 13 MHz

(IC = 0.5 Adc, VCE = 10 Vdc, f = 1 MHz)

Output Capacitance Cob 50 75 pF
(VCB = 10 Vdc, IE = 0, f = 1 MHz)

Input Capacitance

(VEB = 8 Vdc)

Cib 240 500 pF
SWITCHING CHARACTERISTICS: Resistive Load (D.C. 10%, Pulse Width = 40 s)

Turnon Time @ TC = 25C ton 90 150 ns
IC = 1 Adc, IB1 = 0.2 Adc

@ TC = 125C 105
IB2 = 0.5
0 5 Adc
s

Turnoff Time VCC = 300 Vdc @ TC = 25C toff 1.1 1.25
@ TC = 125C 1.5

Turnon Time

IC = 0.5 Adc, IB1 = 50 mAdc
IB2 = 250 mAdc
@ TC = 25C
@ TC = 125C
ton 400
600
600 ns

Turnoff Time VCC = 300 Vdc @ TC = 25C toff 750 1000 ns
@ TC = 125C 1300
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BUD44D2

Characteristic
Symbol Min
SWITCHING CHARACTERISTICS: Inductive Load (Vclamp = 300 V, VCC = 15 V, L = 200 H)
Typ Max Unit

Fall Time

@ TC = 25C
@ TC = 125C
tf 110
105
150 ns

Storage Time IC = 0.4 Adc @ TC = 25C ts 0.55 0.75 s
IB1 = 40 mAdc @ TC = 125C 0.7

IB2 = 0.2 Adc
Crossover Time @ TC = 25C tc 85 150 ns
Fall Time

@ TC = 125C
@ TC = 25C tf
80
100 150 ns

@ TC = 125C 90

Storage Time IC = 1 Adc @ TC = 25C ts 1.05 1.5 s
IB1 = 0.2 Adc

@ TC = 125C 1.45
IB2 = 0.5 Adc

@ TC = 125C 100

Fall Time

@ TC = 25C
@ TC = 125C
tf 110
180
150 ns

IB1 = 160 mAdc

@ TC = 125C 2.8
IB2 = 160 mAdc

@ TC = 125C 400

Fall Time

@ TC = 25C
@ TC = 125C
tf 150
175
225 ns

IB1 = 40 mAdc

@ TC = 125C 2.2
IB2 = 40 mAdc

@ TC = 125C 330
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BUD44D2
TYPICAL STATIC CHARACTERISTICS
100 100
VCE = 1 V VCE = 5 V
80 80

TJ = 125C TJ = 125C
60 TJ = 25C 60 TJ = 25C
40 40
TJ = -20C TJ = -20C
20 20
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Figure 13. DC Current Gain @ 1 Volt Figure 14. DC Current Gain @ 5 Volt
4 10
TJ = 25C IC/IB = 5 TJ = 25C
3 2A
VCE , VOLTAGE (VOLTS)
1.5 A TJ = 125C
1A
2 1
400 mA
TJ = -20C
1
IC = 200 mA
0 0.1
1 10 100 1000 0.001 0.01 0.1 1 10
IB, BASE CURRENT (mA) IC, COLLECTOR CURRENT (AMPS)
Figure 15. Collector Saturation Region Figure 16. CollectorEmitter Saturation

Voltage
10 10
IC/IB = 10 IC/IB = 20
TJ = 25C TJ = 25C
1 1
TJ = 125C
TJ = -20C TJ = 125C
TJ = -20C
0.1 0.1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1
Figure 17. CollectorEmitter Saturation Figure 18. CollectorEmitter Saturation

Voltage Voltage
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BUD44D2
10 10
IC/IB = 5 IC/IB = 10
VBE , VOLTAGE (VOLTS)

1 TJ = -20C 1 TJ = -20C
TJ = 125C TJ = 125C
TJ = 25C TJ = 25C
0.1 0.1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Figure 7A. BaseEmitter Saturation Region Figure 7B. BaseEmitter Saturation Region
10 10
IC/IB = 20 FORWARD DIODE VOLTAGE (VOLTS)
25C
1 TJ = -20C 1
125C
TJ = 125C
TJ = 25C
0.1 0.1
0.001 0.01 0.1 1 0.01 0.1 1 10
IC, COLLECTOR CURRENT (AMPS) REVERSE EMITTER-COLLECTOR CURRENT (AMPS)
Figure 7C. BaseEmitter Saturation Region Figure 8. Forward Diode Voltage
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BUD44D2
TYPICAL SWITCHING CHARACTERISTICS
1000 1000
TJ = 25C TJ = 125C IBon = IBoff
Cib (pF) f(test) = 1 MHz TJ = 25C VCC = 300 V
800 IC/IB = 10 PW = 40 s
C, CAPACITANCE (pF)
100
600
t, TIME (ns)
Cob (pF)
400
IC/IB = 5
10
200
1 0
1 10 100 0.2 0.8 1.4 2
VR, REVERSE VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (AMPS)
Figure 9. Capacitance Figure 10. Resistive Switch Time, ton
4000 3
IBon = IBoff
IC/IB = 10 VCC = 300 V
3500 2.5
PW = 40 s
3000 2
IC/IB = 5
t, TIME (s)
t, TIME (s)

2500 1.5
2000 1 IBon = IBoff

VCC = 15 V
1500 TJ = 125C 0.5 TJ = 125C VZ = 300 V
TJ = 25C TJ = 25C LC = 200 H
1000 0
0 1 2 0.4 0.8 1.2 1.6 2
Figure 11. Resistive Switch Time, toff Figure 12. Inductive Storage Time,
tsi @ IC/IB = 5
700 4
TJ = 125C IC/IB = 5 TJ = 125C
600 TJ = 25C TJ = 25C
IBon = IBoff 3
t si , STORAGE TIME (s)
500 VCC = 15 V
VZ = 300 V IC = 1 A
tc
t, TIME (ns)
400 LC = 200 H
2
300
200 tfi IBon = IBoff

1
IC = 0.3 A VCC = 15 V
100 VZ = 300 V
LC = 200 H
0 0
0 0.5 1 1.5 2 3 6 9 12 15
IC, COLLECTOR CURRENT (AMPS) hFE, FORCED GAIN
Figure 13. Inductive Switching, Figure 14. Inductive Storage Time

tc & tfi @ IC/IB = 5
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BUD44D2
700 1000
IBoff = IBon TJ = 125C IC = 0.3 A IBon = IBoff TJ = 125C
600 VCC = 15 V TJ = 25C VCC = 15 V TJ = 25C
VZ = 300 V 800 VZ = 300 V
t c , CROSSOVER TIME (ns)

500 LC = 200 H LC = 200 H
t fi , FALL TIME (ns)
IC = 1 A
400 600
300 400
200
200
100
IC = 1 A IC = 0.3 A
0 0
3 5 7 9 11 13 15 3 6 9 12 15
hFE, FORCED GAIN hFE, FORCED GAIN
Figure 15. Inductive Fall Time Figure 16. Inductive Crossover Time
900 2000
TJ = 125C IBoff = IC/2 TJ = 125C
800 TJ = 25C VCC = 15 V TJ = 25C
700 VZ = 300 V
IC/IB = 20 1500 LC = 200 H
600 IC/IB = 20
t, TIME (ns)
t, TIME (ns)
500
1000
400
300
IC/IB = 10
500
200
100 IBon = IBoff VZ = 300 V IC/IB = 10

VCC = 15 V LC = 200 H
0 0
0.4 0.8 1.2 1.6 2 0.4 0.8 1.2 1.6 2
Figure 17. Inductive Switching, tfi Figure 18. Inductive Switching, tc
3000 3000
IC/IB = 5 IBon = IBoff IBon = IBoff
VCC = 15 V VCC = 15 V
VZ = 300 V 2500 VZ = 300 V
LC = 200 H LC = 200 H
2000
2000
t, TIME (ns)
t, TIME (ns)
IB = 50 mA 1500
1000 IC/IB = 20
IB = 100 mA
IB = 200 mA 1000
IC/IB = 10
TJ = 125C
IB = 500 mA TJ = 25C
0 500
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2
Figure 19. Inductive Storage Time, tsi Figure 20. Inductive Storage Time, tsi
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BUD44D2
10
VCE
9 IC 90% IC
dyn 1 s
8
tsi tfi
dyn 3 s 7
6 10% IC
0V 10% Vclamp
5 Vclamp tc
4
90% IB 3 IB 90% IB1
1 s 2
3 s 1
IB
0
TIME 0 1 2 3 4 5 6 7 8
TIME
Figure 21. Dynamic Saturation Figure 22. Inductive Switching Measurements

Voltage Measurements
VFRM
VFR (1.1 VF unless otherwise specified)
VF VF
tfr
0.1 VF
0
IF
10% IF
0 2 4 6 8 10
Figure 22 bis. tfr Measurements
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BUD44D2
Table 1. Inductive Load Switching Drive Circuit
+15 V
IC PEAK
1 F 100 MTP8P10 100 F
150
3W 3W VCE PEAK
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
+10 V MPF930 Iout IB
A
IB2
50 RB2
MJE210
COMMON MTP12N10 V(BR)CEO(sus) Inductive Switching RBSOA
150
L = 10 mH L = 200 H L = 500 H
500 F 3W
RB2 = RB2 = 0 RB2 = 0
VCC = 20 Volts VCC = 15 Volts VCC = 15 Volts
1 F IC(pk) = 100 mA RB1 selected for RB1 selected for
desired IB1 desired IB1
-Voff
1100 440
TJ = 25C dI/dt = 10 A/s
t fr , FORWARD RECOVERY TIME (ns)
1000 420 TC = 25C

BVCER (VOLTS) @ 10 mA
900 400
BVCER (VOLTS)
800 380
700 360
BVCER(sus) @ 200 mA
600 340
500 320
400 300
10 100 1000 0 0.5 1 1.5 2
RBE () IF, FORWARD CURRENT (AMP)
Figure 23. BVCER Figure 24. Forward Recovery Time tfr
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ON Semiconductor
BUH100
SWITCHMODE NPN Silicon
Planar Power Transistor POWER TRANSISTOR
10 AMPERES
The BUH100 has an application specific stateofart die designed 700 VOLTS
for use in 100 Watts Halogen electronic transformers. 100 WATTS
This power transistor is specifically designed to sustain the large
inrush current during either the startup conditions or under a short
circuit across the load.
This High voltage/High speed product exhibits the following main
features:
Improved Efficiency Due to the Low Base Drive Requirements:
High and Flat DC Current Gain hFE
Fast Switching
Robustness Thanks to the Technology Developed to Manufacture
this Device
ON Semiconductor Six Sigma Philosophy Provides Tight and
Reproducible Parametric Distributions
CASE 221A09
TO220AB
MAXIMUM RATINGS


CollectorEmitter Sustaining Voltage VCEO 400 Vdc

CollectorBase Breakdown Voltage VCBO 700 Vdc



Peak (1) ICM 20

Base Current Peak (1)

Base Current Continuous IB
IBM
4
10
Adc

*Derate above 25C
*Total Device Dissipation @ TC = 25C

PD 100
0.8
Watt
W/C


Thermal Resistance

C/W

Junction to Case RJC 1.25


1/8 from case for 5 seconds
TL 260 C

March, 2001 Rev. 2 BUH100/D
BUH100


OFF CHARACTERISTICS


(IC = 100 mA, L = 25 mH)


(ICBO = 1 mA)

(IEBO = 1 mA)



ICEO 100 Adc

Collector Cutoff Current @ TC = 25C ICES 100 Adc

(VCE = Rated VCES, VEB = 0) @ TC = 125C 1000

Collector Base Current @ TC = 25C ICBO 100 Adc
(VCB = Rated VCBO, VEB = 0) @ TC = 125C 1000


(VEB = 9 Vdc, IC = 0)

IEBO 100 Adc

ON CHARACTERISTICS

BaseEmitter Saturation Voltage @ TC = 25C VBE(sat) 1 1.1 Vdc


CollectorEmitter Saturation Voltage @ TC = 25C VCE(sat) 0.37 0.6 Vdc
(IC = 5 Adc, IB = 1 Adc) @ TC = 125C 0.37 0.6

(IC = 7 Adc, IB = 1.5 Adc)

@ TC = 25C
@ TC = 125C
0.5
0.6
0.75
1.5
Vdc

DC Current Gain (IC = 1 Adc, VCE = 5 Vdc)

@ TC = 25C
@ TC = 125C
hFE 15
16
24
28

DC Current Gain (IC = 5 Adc, VCE = 5 Vdc) @ TC = 25C 10 15

@ TC = 125C 10 14.5

DC Current Gain (IC = 7 Adc, VCE = 5 Vdc) @ TC = 25C 8 12

@ TC = 125C

10.5

DC Current Gain (IC = 10 Adc, VCE = 5 Vdc) @ TC = 25C
@ TC = 125C
6
4
9.5
8

Dynamic Saturation

@ TC = 25C VCE(dsat) 1.1 V

IC = 5 Adc, IB1 = 1 Adc ( )
V lt
Voltage: VCC = 300 V @ TC = 125C 2.1 V

Determined 3 s after
rising IB1 reaches

IC = 7.5 Adc, IB1 = 1.5 Adc @ TC = 25C 1.7 V
90% of final IB1
VCC = 300 V
(See Figure 19) @ TC = 125C 5 V


Current Gain Bandwidth fT 23 MHz

Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 1 MHz)
Cob 100 150 pF

Input Capacitance Cib 1300 1750 pF
(VEB = 8 Vdc, f = 1 MHz)
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BUH100



Turnon Time


@ TC = 25C ton 130 200 ns

IC = 1 Adc, IB1 = 0.2 Adc @ TC = 125C 140
IB2 = 0.2
0 2 Adc

Turnoff Time VCC = 300 Vdc @ TC = 25C toff 6.8 8 s

@ TC = 125C 8.5

IC = 1 Adc, IB1 = 0.2 Adc @ TC = 125C 150

IB2 = 0.4
0 4 Adc

@ TC = 125C 4.3


IC = 5 Adc, IB1 = 1 Adc @ TC = 125C 800
IB2 = 1 Adc

Turnoff Time VCC = 300 Vdc @ TC = 25C toff 2.9 3.5 s
@ TC = 125C 3.6

Turnon Time

IC = 7.5 Adc, IB1 = 1.5 Adc
@ TC = 25C
@ TC = 125C
ton 500
900
700 ns

IB2 = 1.5
1 5 Adc

@ TC = 125C 2.5


Fall Time @ TC = 25C tfi 150 250 ns
@ TC = 125C 180

Storage Time

IC = 1 Adc
IB1 = 0.2 Adc
IB2 = 0.2 Adc
@ TC = 25C
@ TC = 125C
tsi 5.1
5.8
6 s

Crossover Time

@ TC = 25C
@ TC = 125C
tc 230
300
325 ns

@ TC = 125C 170

Storage Time

IC = 1 Adc
IB1 = 0.2 Adc
IB2 = 0.5 Adc
@ TC = 25C
@ TC = 125C
tsi 2.5
2.8
3 s

Crossover Time

@ TC = 25C
@ TC = 125C
tc 260
300
350 ns

@ TC = 125C 140

Storage Time

IC = 5 Adc
IB1 = 1 Adc
@ TC = 25C
@ TC = 125C
tsi 2.9
4.6
3.5 s

IB2 = 1 Adc

@ TC = 125C 450


@ TC = 125C

150

Storage Time

IC = 7.5 Adc
IB1 = 1.5 Adc
@ TC = 25C
@ TC = 125C
tsi 2
2.5
2.5 s

IB2 = 1.5 Adc

@ TC = 125C 475
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228
BUH100
100 100
VCE = 1 V VCE = 3 V
TJ = 125C TJ = 125C

TJ = -20C TJ = -20C
10 TJ = 25C 10 TJ = 25C
1 1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
100 10
VCE = 5 V IC/IB = 5
TJ = 125C
1
TJ = -20C
10 TJ = 25C TJ = -20C
TJ = 25C
0.1
TJ = 125C
1 0.01
0.01 0.1 1 10 100 0.001 0.01 0.1 1 10
Figure 21. DC Current Gain @ 5 Volt Figure 22. CollectorEmitter Saturation

Voltage
10 1.5
1 1
TJ = 25C TJ = -20C TJ = -20C
TJ = 25C
0.1 TJ = 125C 0.5
TJ = 125C
0.01 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Figure 23. CollectorEmitter Saturation Figure 24. BaseEmitter Saturation Region

Voltage
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BUH100
1.5 2
IC/IB = 10 TJ = 25C 15 A
10 A
1.5

1 8A
TJ = -20C 5A
1
3A
TJ = 25C
0.5 2A
TJ = 125C 0.5
VCE(sat)
(IC = 1 A)
0 0
0.001 0.01 0.1 1 10 0.01 0.1 1 10
IC, COLLECTOR CURRENT (AMPS) IB, BASE CURRENT (A)
Figure 25. BaseEmitter Saturation Region Figure 26. Collector Saturation Region
10000 900
TJ = 25C TJ = 25C
f(test) = 1 MHz 800 BVCER @ 10 mA
Cib
C, CAPACITANCE (pF)
1000
BVCER (VOLTS)
700
600
100
Cob
500
BVCER(sus) @ 500 mA, 25 mH
10 400
1 10 100 10 100 1000 10000 100000
VR, REVERSE VOLTAGE (VOLTS) RBE ()
Figure 27. Capacitance Figure 28. Resistive Breakdown
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230
BUH100
2500 10
IB1 = IB2 TJ = 125C IB1 = IB2
VCC = 300 V TJ = 25C VCC = 300 V
2000 8
PW = 40 s PW = 20 s
TJ = 125C IC/IB = 10
t, TIME (s)
1500 6
t, TIME (ns)
IC/IB = 5

TJ = 25C
1000 4
125C
500 2
IC/IB = 10
25C IC/IB = 5
0 0
0 2 4 6 8 10 0 2 4 6 8 10
Figure 29. Resistive Switching Time, ton Figure 30. Resistive Switch Time, toff
7 6
IB1 = IB2 IB1 = IB2

IC/IB = 5 5 IC/IB = 10
VCC = 15 V VCC = 15 V
VZ = 300 V VZ = 300 V
5 LC = 200 H 4 LC = 200 H
t, TIME (s)
t, TIME (s)

3 2
TJ = 125C 1 TJ = 125C
TJ = 25C TJ = 25C
1 0
1 4 7 10 1 4 7 10
Figure 31. Inductive Storage Time, tsi Figure 13 Bis. Inductive Storage Time, tsi
600 800
IB1 = IB2 TJ = 125C TJ = 125C IB1 = IB2
VCC = 15 V TJ = 25C TJ = 25C VCC = 15 V
VZ = 300 V VZ = 300 V
LC = 200 H 600
tc LC = 200 H
400 tc
t, TIME (ns)
t, TIME (ns)
400
tfi
200 tfi
200
0 0
1 4 7 10 1 4 7 10
Figure 32. Inductive Storage Time, Figure 33. Inductive Storage Time,
tc & tfi @ IC/IB = 5 tc & tfi @ IC/IB = 10
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BUH100
4 200
IC = 7.5 A
3 IC = 5 A 150
tsi , STORAGE TIME (s)

2 100
IC = 7.5 A
IB1 = IB2 IBoff = IB2 IC = 5 A
1 50 VCC = 15 V
VCC = 15 V
TJ = 125C VZ = 300 V VZ = 300 V TJ = 125C
TJ = 25C LC = 200 H LC = 200 H TJ = 25C
0 0
2 4 6 8 10 3 4 5 6 7 8 9 10
Figure 34. Inductive Storage Time Figure 35. Inductive Fall Time
800
IB1 = IB2
700 VCC = 15 V
VZ = 300 V
600 LC = 200 H
IC = 7.5 A
500
400
300
200 TJ = 125C IC = 5 A
TJ = 25C
100
3 4 5 6 7 8 9 10
hFE, FORCED GAIN
Figure 36. Inductive Crossover Time, tc
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BUH100
10
VCE 9 IC 90% IC
8 tfi
dyn 1 s tsi
7
dyn 3 s 6
10% Vclamp 10% IC
0V 5 Vclamp
tc
4
90% IB 90% IB1
3 IB
1 s 2
IB 1
3 s
0
TIME 0 1 2 3 4 5 6 7 8
TIME
Figure 37. Dynamic Saturation Voltage Figure 38. Inductive Switching Measurements
Measurements
+15 V
IC PEAK
1 F 100 MTP8P10 100 F
150
3W 3W VCE PEAK
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
COMMON MTP12N10
150
3W V(BR)CEO(sus) Inductive Switching RBSOA
500 F L = 10 mH L = 200 H L = 500 H
RB2 = RB2 = 0 RB2 = 0
1 F VCC = 20 Volts VCC = 15 Volts VCC = 15 Volts
-Voff IC(pk) = 100 mA RB1 selected for RB1 selected for
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BUH100
TYPICAL THERMAL RESPONSE
1
SECOND BREAKDOWN
DERATING
0.8
POWER DERATING FACTOR

0.6
THERMAL DERATING
0.4
0.2
0
20 40 60 80 100 120 140 160
Figure 39. Forward Bias Power Derating
There are two limitations on the power handling ability of TJ(pk) may be calculated from the data in Figure 24. At any
a transistor: average junction temperature and second case temperatures, thermal limitations will reduce the power
breakdown. Safe operating area curves indicate ICVCE that can be handled to values less than the limitations
limits of the transistor that must be observed for reliable imposed by second breakdown. For inductive loads, high
operation; i.e., the transistor must not be subjected to greater voltage and current must be sustained simultaneously during
dissipation than the curves indicate. The data of Figure 22 is turnoff with the base to emitter junction reverse biased. The
based on TC = 25C; TJ(pk) is variable depending on power safe level is specified as a reverse biased safe operating area
level. Second breakdown pulse limits are valid for duty (Figure 23). This rating is verified under clamped conditions
cycles to 10% but must be derated when TC > 25C. Second so that the device is never subjected to an avalanche mode.
limitations. Allowable current at the voltages shown on
Figure 22 may be found at any case temperature by using the
100 12
GAIN 5 TC 125C
10 LC = 2 mH
10 1 ms 10 s 1 s
5 ms 8
EXTENDED
1 DC SOA 6
4
0.1 -5 V
2
0V -1.5 V
0.01 0
10 100 1000 200 300 400 500 600 700 800
Figure 40. Forward Bias Safe Operating Area Figure 41. Reverse Bias Safe Operating Area
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234
BUH100
1
0.5
0.2
(NORMALIZED)
0.1 P(pk)
0.05 RJC = 1.25C/W MAX
0.02 t2 READ TIME AT t1
SINGLE PULSE
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
Figure 42. Typical Thermal Response (ZJC(t)) for BUH100
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235
ON Semiconductor
BUH150
15 AMPERES
The BUH150 has an application specific stateofart die designed 700 VOLTS
for use in 150 Watts Halogen electronic transformers. 150 WATTS
features:
Fast Switching
this Device
Reproducible Parametric Distributions
MAXIMUM RATINGS

Rating
Symbol
VCEO
Value
400
Unit
Vdc


VCBO
VCES
700
700
Vdc
Vdc
CASE 221A09
TO220AB

EmitterBase Voltage

VEBO
IC
10
15
Vdc
Adc

Peak (1) ICM 25


IB
IBM
6
12
Adc


Operating and Storage Temperature
TJ, Tstg 65 to 150 C

C/W

Thermal Resistance


Maximum Lead Temperature for Soldering Purposes: TL 260 C

BUH150


OFF CHARACTERISTICS


(IC = 100 mA, L = 25 mH)


(ICBO = 1 mA)

(IEBO = 1 mA)



ICEO 100 Adc





(VEB = 9 Vdc, IC = 0)

IEBO 100 Adc
ON CHARACTERISTICS

BaseEmitter Saturation Voltage VBE(sat) 1 1.25 Vdc


(IC = 2 Adc, IB = 0.4 Adc) @ TC = 125C 0.15 0.4



@ TC = 25C
@ TC = 25C
0.45
2
1
5
Vdc
Vdc


@ TC = 25C
@ TC = 125C
hFE 4
2.5
7
4.5


@ TC = 25C
@ TC = 125C
8
6
12
10


@ TC = 25C
@ TC = 125C
12
14
20
22

DC Current Gain (IC = 100 mAdc, VCE = 5 Vdc)

@ TC = 25C 10 20
V lt

Voltage:
Dynamic Saturation


IC = 5 Adc, IB1 = 1 Adc

VCC = 300 V
@ TC = 25C
@ TC = 125C
VCE(dsat)
( ) 1.5
2.8
V

rising IB1 reaches

90% of final IB1
(see Figure 19)

IC = 10 Adc, IB1 = 2 Adc
VCC = 300 V
@ TC = 25C
@ TC = 125C
2.4
5
V



fT 23 MHz



(VCB = 10 Vdc, IE = 0, f = 1 MHz)

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237
BUH150



Turnon Time


@ TC = 25C ton 200 300 ns

Storage Time

Fall Time


IB2 = 0.2
0 2 Adc
VCC = 300 Vdc
@ TC = 25C
@ TC = 25C
ts
tf
5.3
240
6.5
350
s
ns

Turnoff Time

Turnon Time

@ TC = 25C
@ TC = 25C
toff
ton
5.6
100
7
200
s
ns

Storage Time

Fall Time


IB2 = 0.4
0 4 Adc
VCC = 300 Vdc
@ TC = 25C
@ TC = 25C
ts
tf
6.1
320
7.5
500
s
ns

Turnoff Time

Turnon Time

@ TC = 25C
@ TC = 25C
toff
ton
6.5
450
8
650
s
ns

IC = 5 Adc, IB1 = 0.5 Adc @ TC = 125C 800
IB2 = 0.5
0 5 Adc


@ TC = 125C 3.9

IC = 10 Adc, IB1 = 2 Adc @ TC = 125C 900

IB2 = 2 Adc

@ TC = 125C 2.75

Fall Time


@ TC = 25C tfi 110 250 ns

@ TC = 125C 160
IC = 2 Adc s

Storage Time @ TC = 25C tsi 6.5 8
IB1 = 0.2 Adc @ TC = 125C 8

IB2 = 0.2 Adc

@ TC = 125C 240


@ TC = 125C 170
IC = 2 Adc

Storage Time @ TC = 25C tsi 6 7.5 s
IB1 = 0.4 Adc @ TC = 125C 7.8

IB2 = 0.4 Adc

@ TC = 125C 270

Fall Time

IC = 5 Adc
@ TC = 25C
@ TC = 125C
tfi 110
140
150 ns

Storage Time @ TC = 25C tsi 3.25 3.75 s
IB1 = 0.5 Adc @ TC = 125C 4.6

IB2 = 0.5 Adc
Fall Time

@ TC = 125C
@ TC = 25C tfi
450
110 175 ns

@ TC = 125C 160

Storage Time IC = 10 Adc @ TC = 25C tsi 2.3 2.75 s
IB1 = 2 Adc @ TC = 125C 2.8

IB2 = 2 Adc

@ TC = 125C 475
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238
BUH150
100 100
VCE = 1 V VCE = 3 V
TJ = 125C TJ = 125C

TJ = -20C TJ = -20C
10 TJ = 25C 10 TJ = 25C
1 1
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100
100 10
VCE = 5 V IC/IB = 5
TJ = 125C TJ = 125C
1
TJ = -20C
10 TJ = 25C TJ = 25C
0.1 TJ = -20C
1 0.01
0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100

Voltage
10 1.5
1 1
TJ = -20C
TJ = 125C
TJ = 25C
0.1 0.5
TJ = 125C
TJ = 25C
0.01 0
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100

Voltage
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239
BUH150

1.5 2
TJ = 25C
IC/IB = 10
1.5

1
TJ = -20C
1
TJ = 25C 20 A
0.5
TJ = 125C 0.5 VCE(sat) 15 A
(IC = 1 A) 10 A
8A
5A
0 0
0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100
10000 900
TJ = 25C TJ = 25C
Cib (pF)
C, CAPACITANCE (pF)
1000
BVCER (VOLTS)
700
BVCER(sus) @ 200 mA
600
100 Cob (pF)
500
10 400
1 10 100 10 100 1000
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240
BUH150
2000 12
1800 IB1 = IB2 TJ = 25C IB1 = IB2
VCC = 300 V IC/IB = 10 10 TJ = 125C VCC = 300 V
1600
PW = 40 s PW = 20 s
1400 25C 8
125C
t, TIME (s)
1200
t, TIME (ns)

1000 6 IC/IB = 5
125C
800
4
600
400
25C 2 IC/IB = 10
200 IC/IB = 5
0 0
0 3 6 9 12 15 0 5 10 15
Figure 53. Resistive Switching, ton Figure 54. Resistive Switch Time, toff
8 8
7 IC/IB = 5 IB1 = IB2 7 IC/IB = 10 IB1 = IB2

VCC = 15 V VCC = 15 V
6 VZ = 300 V 6 VZ = 300 V
LC = 200 H LC = 200 H
t, TIME (s)
t, TIME (s)
5 5

4 4
3 3
2 2
TJ = 125C TJ = 125C
1 TJ = 25C 1 TJ = 25C
0 0
1 3 5 7 9 11 13 15 1 4 7 10
550 800
IB1 = IB2 TJ = 125C IB1 = IB2 TC = 125C
VCC = 15 V TJ = 25C 700
VCC = 15 V TC = 25C
450 VZ = 300 V
600 VZ = 300 V
LC = 200 H LC = 200 H
tc 500
350
t, TIME (ns)
t, TIME (ns)
tc
400
250 300
tfi
tfi
200
150
100
50 0
1 3 5 7 9 11 13 15 0 2 4 6 8 10
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241
BUH150
5 200
TJ = 125C
TJ = 25C
4 IC = 5 A
150

3
100
2
IC = 5 A
IB1 = IB2 IBoff = IB2
50 IC = 10 A
1 VCC = 15 V VCC = 15 V
VZ = 300 V IC = 10 A TJ = 125C VZ = 300 V
LC = 200 H TJ = 25C LC = 200 H
0 0
2 4 6 8 10 3 4 5 6 7 8 9 10
800
IB1 = IB2 TJ = 125C
700 VCC = 15 V TJ = 25C
VZ = 300 V
600 LC = 200 H
IC = 10 A
500
400
IC = 5 A
300
200
100
3 4 5 6 7 8 9 10
hFE, FORCED GAIN
Figure 60. Inductive Crossover Time
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242
BUH150
10
VCE 9 IC 90% IC
dyn 1 s 8 tfi
tsi
dyn 3 s 7
6
0V 5 Vclamp 10% Vclamp 10% IC
tc
4
90% IB 3 IB 90% IB1
1 s 2
IB 1
3 s
0
0 1 2 3 4 5 6 7 8
TIME TIME
Measurements
+15 V
IC PEAK
1 F 100 MTP8P10 100 F
150
3W 3W VCE PEAK
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
COMMON MTP12N10
150 V(BR)CEO(sus) Inductive Switching RBSOA
500 F 3W L = 10 mH L = 200 H L = 500 H
RB2 = RB2 = 0 RB2 = 0
IC(pk) = 100 mA RB1 selected for RB1 selected for
-Voff desired IB1 desired IB1
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243
BUH150
SECOND BREAKDOWN
0.8 DERATING

0.6
THERMAL DERATING
0.4
0.2
0
20 40 60 80 100 120 140 160
100 16
14 GAIN 5 TC 125C
1 s
LC = 4 mH
10 10 s 12
5 ms
1 ms 10
EXTENDED SOA
DC
1 8
6 -5 V
0.1 4
0V -1.5 V
2
0.01 0
1 10 100 1000 300 400 500 600 700 800
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244
BUH150
1
0.5
(NORMALIZED)
0.2
0.1 P(pk) RJC(t) = r(t) RJC
0.1
RJC = 0.83C/W MAX
t2
SINGLE PULSE
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
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245
ON Semiconductor
BUH50
4 AMPERES
The BUH50 has an application specific stateofart die designed for 800 VOLTS
use in 50 Watts HALOGEN electronic transformers and 50 WATTS
SWITCHMODE applications.
This high voltage/high speed transistor exhibits the following main
feature:
Improved Efficiency Due to Low Base Drive Requirements:
Fast Switching
Reproductible Parametric Distributions
Specified Dynamic Saturation Data
Full Characterization at 125C
MAXIMUM RATINGS




CASE 221A09

EmitterBase Voltage VEBO 9 Vdc TO220AB


Peak (1) ICM 8


*Total Device Dissipation @ TC = 25C

*Derate above 25C
PD 50
0.4
Watt
W/C


Thermal Resistance C/W



TL 260 C

BUH50


OFF CHARACTERISTICS


(IC = 100 mA, L = 25 mH)

Collector Cutoff Current ICEO 100 Adc

Adc

Collector Cutoff Current @ TC = 25C ICES 100


(VEB = 9 Vdc, IC = 0)

IEBO 100 Adc
ON CHARACTERISTICS


(IC = 1 Adc, IB = 0.33 Adc) 0.86 1.2
(IC = 2 Adc, IB = 0.66 Adc) 25C 0.94 1.6

(IC = 2 Adc, IB = 0.66 Adc) 100C 0.85 1.5

(IC = 1 Adc, IB = 0.33 Adc) @ TC = 25C 0.2 0.5

(IC = 2 Adc, IB = 0.66 Adc) @ TC = 25C
@ TC = 125C
0.32
0.29
0.6
0.7


@ TC = 25C 0.5 1

DC Current Gain (IC = 1 Adc, VCE = 5 Vdc) @ TC = 25C hFE 7 13


@ TC = 25C 5 10


fT 4 MHz

Output Capacitance


Cob 50 100 pF

(VCB = 10 Vdc, IE = 0, f = 1 MHz)

(VEB = 8 Vdc)

@ 1 s @ TC = 25C VCE(dsat) 1.75 V

IC = 1 A @ TC = 125C 5
Dynamic Saturation

IB1 = 0
0.33
33 A
Voltage:
VCC = 300 V @ 3 s @ TC = 25C 0.3 V
Determined 1 s and

@ TC = 125C 0.5
3 s respectively

after rising IB1 @ 1 s @ TC = 25C 6 V
IC = 2 A @ TC = 125C 14

reaches 90% of final
IB1 IB1 = 0
0.66
66 A
@ 3 s @ TC = 25C 0.75 V

VCC = 300 V
@ TC = 125C 4
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247
BUH50



Turnon Time

IC = 2 Adc, IB1 = 0.4 Adc @ TC = 25C ton 95 250 ns

IB2 = 0.4
0 4 Adc
Turnoff Time @ TC = 25C toff 2.5 3.5 s

VCC = 125 Vdc
Turnon Time IC = 2 Adc, IB1 = 0.4 Adc @ TC = 25C ton 110 250 ns

Turnoff Time

IB2 = 1 Adc
VCC = 125 Vdc @ TC = 25C toff 0.95 2 s

Turnon Time IC = 1 Adc, IB1 = 0.3 Adc @ TC = 25C ton 100 200 ns
IB2 = 0.3
0 3 Adc


Fall Time


@ TC = 25C tf 80 150 ns

@ TC = 125C 95
IC = 2 Adc s

Storage Time @ TC = 25C ts 1.2 2.5
IB1 = 0.4 Adc @ TC = 125C 1.7

IB2 = 1 Adc

@ TC = 125C 180

Fall Time @ TC = 25C tf 90 150 ns

@ TC = 125C 100
IC = 2 Adc

Storage Time @ TC = 25C ts 1.7 2.75 s
IB1 = 0.66 Adc @ TC = 125C 2.5

IB2 = 1 Adc

@ TC = 125C 220
100 100
VCE = 1 V VCE = 5 V
TJ = 125C TJ = 125C
TJ = 25C TJ = 25C
10 10
TJ = -40C TJ = -40C
1 1
0.01 0.1 1 10 0.01 0.1 1 10
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248
BUH50
10 10
TJ = 25C IC/IB = 3

4A
3A 1
1
2A
TJ = -40C
1A 0.1 TJ = 125C
IC = 500 mA TJ = 25C
0.1 0.01
0.01 0.1 1 10 0.01 0.1 1 10

Voltage
10 10
IC/IB = 5 IC/IB = 3
TJ = -40C
1 TJ = 125C
0.1 TJ = -40C
TJ = 25C TJ = 25C
TJ = 125C
0.01 0.1
0.01 0.1 1 10 0.01 0.1 1 10

Voltage
10 10000
IC/IB = 5 TJ = 25C
f(test) = 1 MHz
Cib (pF)
1000
C, CAPACITANCE (pF)
1 TJ = 125C 100
Cob (pF)
TJ = -40C
TJ = 25C 10
0.1 1
0.01 0.1 1 10 1 10 100
IC, COLLECTOR CURRENT (AMPS) VR, REVERSE VOLTAGE (VOLTS)
Figure 73. BaseEmitter Saturation Region Figure 74. Capacitance
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249
BUH50
3000 4000
TJ = 125C IBoff = IC/2 TJ = 125C
VCC = 125 V IBoff = IC/2
2500 TJ = 25C TJ = 25C VCC = 125 V
PW = 20 s
3000 PW = 20 s
2000
t, TIME (ns)
t, TIME (ns)
IC/IB = 5
1500 2000
IC/IB = 3
1000
1000
500
IC/IB = 3 IC/IB = 5
0 0
1 2 3 4 5 1 2 3 4 5
4000 300
IBoff = IC/2 IBoff = IC/2
VCC = 15 V VCC = 15 V
IC/IB = 3 VZ = 300 V VZ = 300 V
3000 LC = 200 H LC = 200 H
200
t, TIME (ns)
t, TIME (ns)
tc
2000
100
1000
TJ = 125C tfi TJ = 125C
TJ = 25C IC/IB = 5 TJ = 25C
0 0
1 2 3 4 1 2 3 4
Figure 77. Inductive Storage Time, tsi Figure 78. Inductive Storage Time,
tc & tfi @ IC/IB = 3
TYPICAL CHARACTERISTICS
250 4000
TJ = 125C TJ = 125C IBoff = IC/2
tc
TJ = 25C TJ = 25C VCC = 15 V
200 VZ = 300 V
3000
LC = 200 H
IC = 1 A
150
t, TIME (ns)
2000
100
IBoff = IC/2 1000

50 VCC = 15 V
IC = 2 A
VZ = 300 V tfi
LC = 200 H
0 0
1 2 3 4 3 4 5 6 7 8 9 10
Figure 79. Inductive Switching, tc & tfi @ IC/IB = 5 Figure 80. Inductive Storage Time
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250
BUH50
150 350
IBoff = IC/2 IBoff = IC/2
140
VCC = 15 V VCC = 15 V
130 IC = 1 A VZ = 300 V VZ = 300 V

120 LC = 200 H IC = 1 A LC = 200 H
250
110
100
90
150 IC = 2 A
80
70
TJ = 125C IC = 2 A TJ = 125C
60 TJ = 25C
TJ = 25C
50 50
2 4 6 8 10 3 5 7 9 11
SECOND BREAKDOWN
0.8
DERATING
0.6
THERMAL DERATING
0.4
0.2
0
20 40 60 80 100 120 140 160
Figure 83. Forward Power Derating
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251
BUH50
10
VCE
9 IC 90% IC
dyn 1 s 8
tsi tfi
dyn 3 s 7
6 10% IC
0V 10% Vclamp
5 Vclamp tc
4
90% IB 3 IB 90% IB1
1 s 2
3 s 1
IB
0
TIME 0 1 2 3 4 5 6 7 8
TIME
10 5
1 s TC 125C
10 s GAIN 3
LC = 500 H
1 ms
4
5 ms
1
EXTENDED 3
SOA
DC
2
0.1
1 -5 V
0V -1.5 V
0.01 0
10 100 1000 300 600 900
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252
BUH50
+15 V
IC PEAK
1 F 100 MTP8P10 100 F
150
3W 3W VCE PEAK
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
COMMON MTP12N10
500 F 3W L = 10 mH L = 200 H L = 500 H
RB2 = RB2 = 0 RB2 = 0
1 F
1
0.5
0.2
(NORMALIZED)

0.1 RJC = 2.5C/W MAX
0.05
t2
SINGLE PULSE DUTY CYCLE, D = t1/t2 TJ(pk) - TC = P(pk) RJC(t)
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
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253
ON Semiconductor
BUH51
3 AMPERES
The BUH51 has an application specific stateofart die designed for 800 VOLTS
use in 50 Watts Halogen electronic transformers. 50 WATTS
features:
Fast Switching
this Device
ON Semiconductor Six Sigma Philosophy Providing Tight and
Reproducible
Parametric Distributions

MAXIMUM RATINGS


CASE 7709

TO225AA TYPE


EmitterBase Voltage
VCES
VEBO
800
10
Vdc
Vdc


Peak (1)
IC
ICM
3
8
Adc


IB
IBM
2
4
Adc



C/W

Thermal Resistance

Junction to Ambient RJA 100


BUH51


OFF CHARACTERISTICS


(IC = 100 mA, L = 25 mH)
(ICBO = 1 mA)

(IEBO = 1 mA)



ICEO 100 Adc




(VEB = 9 Vdc, IC = 0)

IEBO 100 Adc

ON CHARACTERISTICS


@ TC = 25C VBE(sat) 0.92 1.1 Vdc

(IC = 1 Adc, IB = 0.2 Adc) @ TC = 125C 0.8

(IC = 1 Adc, IB = 0.2 Adc) @ TC = 125C 0.32 0.6


@ TC = 25C
@ TC = 125C
hFE 8
6
10
8


@ TC = 25C
@ TC = 125C
5
4
7.5
6.2

DC Current Gain (IC = 0.8 Adc, VCE = 5 Vdc)

@ TC = 25C
@ TC = 125C
10
8
14
13

DC Current Gain (IC = 10 mAdc, VCE = 5 Vdc)

@ TC = 25C
@ TC = 125C
14
18
20
25


Dynamic Saturation IC = 1 Adc, IB1 = 0.2 Adc @ TC = 25C VCE(dsat)
( ) 1.7 V

Voltage: VCC = 300 V @ TC = 125C 6 V

rising IB1 reaches IC = 2 Adc, IB1 = 0.4 Adc @ TC = 25C 5.1 V

90% of final IB1 VCC = 300 V @ TC = 125C 15 V

Current Gain Bandwidth fT 23 MHz
Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 1 MHz)
Cob 34 100 pF

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255
BUH51



Turnon Time

@ TC = 25C ton 110 150 ns

IC = 1 Adc, IB1 = 0.2 Adc @ TC = 125C 125
IB2 = 0.2
0 2 Adc


@ TC = 125C 4.1

IC = 2 Adc, IB1 = 0.4 Adc @ TC = 125C 1250

IB2 = 0.4
0 4 Adc

@ TC = 125C 2.1

Fall Time


@ TC = 25C tfi 200 300 ns

@ TC = 125C 320
IC = 1 Adc s

Storage Time @ TC = 25C tsi 3.4 3.75
IB1 = 0.2 Adc @ TC = 125C 4

IB2 = 0.2 Adc

@ TC = 125C 640


@ TC = 125C 300
IC = 2 Adc

Storage Time @ TC = 25C tsi 2.3 2.75 s
IB1 = 0.4 Adc @ TC = 125C 2.8

IB2 = 0.4 Adc

@ TC = 125C 725
100 100
VCE = 1 V VCE = 3 V
TJ = 125C TJ = 125C
10 TJ = -20C 10 TJ = -20C TJ = 25C

TJ = 25C
1 1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
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256
BUH51
100 10
VCE = 5 V
IC/IB = 5
TJ = 125C

TJ = 125C
1
TJ = 25C
10 TJ = -20C TJ = 25C
TJ = -20C
0.1
1 0.01
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10

Voltage
10 1.5
1
TJ = -20C
1
TJ = 25C
TJ = 25C
0.5 TJ = 125C
TJ = -20C
TJ = 125C
0.1 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10

Voltage
1.5 2
IC/IB = 10 TJ = 25C
4A
1.5 3A
1 2A
TJ = -20C 1A
1
TJ = 25C
0.5
TJ = 125C 0.5
VCE(sat)
(IC = 500 mA)
0 0
0.001 0.01 0.1 1 10 0.01 0.1 1 10
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257
BUH51
1000 1000
TJ = 25C TJ = 25C
f(test) = 1 MHz 900
Cib
C, CAPACITANCE (pF)
800
BVCER (VOLTS)
100 700
600 BVCER @ 10 mA
Cob 500 BVCER(sus) @ 200 mA, 25 mH
10 400
1 10 100 10 100 1000 10000 100000
2500 10
IB1 = IB2 IB1 = IB2
VCC = 300 V VCC = 300 V
2000 PW = 40 s IC/IB = 5 8 IC/IB = 5 PW = 40 s
t, TIME (s)
1500 6
t, TIME (ns)
1000 4
500 2 TJ = 125C
TJ = 125C
TJ = 25C
TJ = 25C
0 0
0 1 2 3 0 1 2 3
7 4
IB1 = IB2 IC/IB = 10 IB1 = IB2
VCC = 15 V VCC = 15 V
IC/IB = 5
VZ = 300 V VZ = 300 V
LC = 200 H 3 LC = 200 H
5
t, TIME (s)
t, TIME (s)

3
1
TJ = 125C TJ = 125C
TJ = 25C TJ = 25C
1 0
0 1 2 3 0.5 1 1.5 2
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258
BUH51
800 1000
IB1 = IB2 IB1 = IB2
VCC = 15 V VCC = 15 V
VZ = 300 V tc 800 VZ = 300 V
600 LC = 200 H LC = 200 H
tc
tc 600
t, TIME (ns)
t, TIME (ns)
400
400
tfi
ttfifi
200
200
TJ = 125C tfi TJ = 125C
TJ = 25C TJ = 25C
0 0
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5
4 450
IBoff = IB2
400 VCC = 15 V
350 VZ = 300 V
LC = 200 H
3 300
IC = 0.8 A
250
200
2 150
IC = 2 A IB1 = IB2
VCC = 15 V 100
TJ = 125C IC = 0.8 A
VZ = 300 V IC = 2 A TJ = 125C
TJ = 25C 50
LC = 200 H TJ = 25C
1 0
2 4 6 8 10 3 4 5 6 7 8 9 10
800
TJ = 125C
IC = 2 A
700 TJ = 25C
600
IB1 = IB2
500 VCC = 15 V
VZ = 300 V
400 LC = 200 H
300
200 IC = 0.8 A
100
3 4 5 6 7 8 9 10
hFE, FORCED GAIN
Figure 106. Inductive Crossover Time
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BUH51
10
VCE
9 IC 90% IC
dyn 1 s 8
tsi tfi
dyn 3 s 7
6 10% IC
0V 10% Vclamp
5 Vclamp tc
4
90% IB 3 IB 90% IB1
1 s 2
3 s 1
IB
0
TIME 0 1 2 3 4 5 6 7 8
TIME
Figure 107. Dynamic Saturation Voltage Figure 108. Inductive Switching

Measurements Measurements
+15 V
IC PEAK
1 F 100 MTP8P10 100 F
150
3W 3W VCE PEAK
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
COMMON V(BR)CEO(sus) Inductive Switching RBSOA
150 MTP12N10
L = 10 mH L = 200 H L = 500 H
500 F 3W RB2 = RB2 = 0 RB2 = 0
1 F IC(pk) = 100 mA RB1 selected for RB1 selected for
-Voff
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BUH51

1
SECOND BREAKDOWN
0.8 DERATING

0.6
THERMAL DERATING
0.4
0.2
0
20 40 60 80 100 120 140 160
There are two limitations on the power handling ability of TJ(pk) may be calculated from the data in Figure 112. At
a transistor: average junction temperature and second any case temperatures, thermal limitations will reduce the
breakdown. Safe operating area curves indicate ICVCE power that can be handled to values less than the limitations
dissipation than the curves indicate. The data of Figure 110 turnoff with the base to emitter junction reverse biased. The
is based on TC = 25C; TJ(pk) is variable depending on power safe level is specified as a reverse biased safe operating area
level. Second breakdown pulse limits are valid for duty (Figure 111). This rating is verified under clamped
cycles to 10% but must be derated when TC > 25C. Second conditions so that the device is never subjected to an
breakdown limitations do not derate the same as thermal avalanche mode.
Figure 110 may be found at any case temperature by using
the appropriate curve on Figure 109.
100 4
TC 125C
GAIN 4
LC = 500 H
10 1 s 3
1 ms 10 s
1 5 ms 2
DC
EXTENDED
SOA
0.1 1 -5 V
0V -1.5 V
0.01 0
10 100 1000 200 300 400 500 600 700 800 900
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BUH51
1
0.5
0.2
(NORMALIZED)
0.1
P(pk) RJC(t) = r(t) RJC
0.1 0.05 RJC = 2.5C/W MAX
t1
t2 READ TIME AT t1
SINGLE PULSE TJ(pk) - TC = P(pk) RJC(t)
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
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ON Semiconductor
SWITCHMODE BUL146
NPN Bipolar Power Transistor BUL146F
For Switching Power Supply Applications
The BUL146/BUL146F have an applications specific
POWER TRANSISTOR
stateoftheart die designed for use in fluorescent electric lamp
6.0 AMPERES
ballasts to 130 Watts and in Switchmode Power supplies for all types 700 VOLTS
of electronic equipment. These high voltage/high speed transistors 40 and 100 WATTS
offer the following:
High and Flat DC Current Gain
Fast Switching
No Coil Required in Base Circuit for TurnOff (No Current Tail)
Two Packages Choices: Standard TO220 or Isolated TO220
Parametric Distributions are Tight and Consistent LottoLot
BUL146F, Case 221D, is UL Recognized to 3500 VRMS: File #
E69369
BUL146
MAXIMUM RATINGS CASE 221A09
Rating Sym- BUL146 BUL146F Unit TO220AB
bol
Peak(1) ICM 15
Peak(1) IBM 8.0
RMS Isolation Voltage: (2) VISOL1 4500 Volts
(for 1 sec, R.H. 30%, VISOL2 3500
TC = 25 C) VISOL3 1500
Total Device Dissipation (TC = 25C) PD 100 40 Watts CASE 221D02
Derate above 25C 0.8 0.32 W/C ISOLATED TO220 TYPE
Operating and Storage Temperature TJ, Tstg 65 to 150 C BUL146F
Rating Sym- BUL146 BUL146F Unit
bol
Thermal Resistance Junction to Case RJC 1.25 3.125 C/W
Junction to Ambient RJA 62.5 62.5
Purposes: 1/8 from Case for 5 Seconds

June, 2001 Rev. 5 BUL146/D
BUL146 BUL146F

OFF CHARACTERISTICS
CollectorEmitter Sustaining Voltage (IC = 100 mA, L = 25 mH) VCEO(sus) 400 Vdc
Collector Cutoff Current (VCE = Rated VCEO, IB = 0) ICEO 100 Adc
Collector Cutoff Current (VCE = Rated VCES, VEB = 0) ICES 100 Adc
(TC = 125C) 500
Collector Cutoff Current (VCE = 500 V, VEB = 0) (TC = 125C) 100
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle 10%.
ON CHARACTERISTICS
BaseEmitter Saturation Voltage (IC = 1.3 Adc, IB = 0.13 Adc) VBE(sat) 0.82 1.1 Vdc
BaseEmitter Saturation Voltage (IC = 3.0 Adc, IB = 0.6 Adc) 0.93 1.25
CollectorEmitter Saturation Voltage (IC = 1.3 Adc, IB = 0.13 Adc) VCE(sat) 0.22 0.5 Vdc
(TC = 125C) 0.20 0.5
CollectorEmitter Saturation Voltage (IC = 3.0 Adc, IB = 0.6 Adc) 0.30 0.7
(TC = 125C) 0.30 0.7
DC Current Gain (IC = 0.5 Adc, VCE = 5.0 Vdc) hFE 14 34
(TC = 125C) 30
DC Current Gain (IC = 1.3 Adc, VCE = 1.0 Vdc) 12 20
(TC = 125C) 12 20
DC Current Gain (IC = 3.0 Adc, VCE = 1.0 Vdc) 8.0 13
(TC = 125C) 7.0 12
DC Current Gain (IC = 10 mAdc, VCE = 5.0 Vdc) 10 20
Current Gain Bandwidth (IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 MHz) fT 14 MHz
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz) COB 95 150 pF
Input Capacitance (VEB = 8.0 V) CIB 1000 1500 pF
1.0 2.5
Dynamic
y a c Saturation
Sa u a o Volt-
o (IC = 1.3 Adc s (TC = 125C) 6.5
age: IB1 = 300 mAdc
VCC = 300 V) 3.0 0.6
Determined 1.0 s and s (TC = 125C) 2.5
3 0 s respectively after
3.0 VCE(dsat) V
rising IB1 reaches 90% of 1.0 3.0
final IB1
(IC = 3.0 Adc s (TC = 125C) 7.0
IB1 = 0.6
0 6 Adc
(see Figure 18) VCC = 300 V) 3.0 0.75
s (TC = 125C) 1.4
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BUL146 BUL146F

TurnOn Time (IC = 1.3 Adc, IB1 = 0.13 Adc ton 100 200 ns
IB2 = 0.65 Adc, VCC = 300 V) (TC = 125C) 90
TurnOff Time toff 1.35 2.5 s
(TC = 125C) 1.90
IB1 = 1.5 Adc, VCC = 300 V) (TC = 125C) 100
(TC = 125C) 2.1
Fall Time (IC = 1.3 Adc, IB1 = 0.13 Adc tfi 115 200 ns
IB2 = 0.65 Adc) (TC = 125C) 120
Storage Time tsi 1.35 2.5 s
(TC = 125C) 1.75
Crossover Time tc 200 350 ns
(TC = 125C) 210
IB2 = 1.5 Adc) (TC = 125C) 100
(TC = 125C) 2.25
(TC = 125C) 200
IB2 = 0.6 Adc) (TC = 125C) 210
(TC = 125C) 4.5
(TC = 125C) 400
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BUL146 BUL146F
100 100
VCE = 5 V
TJ = 125C VCE = 1 V TJ = 125C
TJ = 25C
h FE , DC CURRENT GAIN
TJ = 25C
TJ = -20C
10 TJ = -20C 10
1 1
0.01 0.1 1 10 0.01 0.1 1 10
Figure 1. DC Current Gain @ 1 Volt Figure 2. DC Current Gain @ 5 Volts
2 10
TJ = 25C
V CE , VOLTAGE (V)
1
V CE , VOLTAGE (V)
IC = 1 A 2A 3A 5A 6A
1
0.1 IC/IB = 10
IC/IB = 5 TJ = 25C
TJ = 125C
0 0.01
0.01 0.1 1 10 0.01 0.1 1 10
IB, BASE CURRENT (mA) IC COLLECTOR CURRENT (AMPS)
1.2 10000
1.1 TJ = 25C
Cib f = 1 MHz
1 1000
V BE , VOLTAGE (V)
C, CAPACITANCE (pF)
0.9
0.8 100
TJ = 25C Cob
0.7
0.6 10
TJ = 125C IC/IB = 5
0.5
IC/IB = 10
0.4 1
0.01 0.1 1 10 1 10 100 1000
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BUL146 BUL146F

(IB2 = IC/2 for all switching)
1000 4000
IB(off) = IC/2 IB(off) = IC/2
IC/IB = 5 TJ = 25C
VCC = 300 V 3500 VCC = 300 V
IC/IB = 10 TJ = 125C
800 PW = 20 s PW = 20 s
3000 IC/IB = 5
2500
t, TIME (ns)
600
t, TIME (ns)
TJ = 125C IC/IB = 10
2000
400 1500
1000
200
TJ = 25C
500
0 0
0 2 4 6 8 0 2 4 6 8
Figure 7. Resistive Switching, ton Figure 8. Resistive Switching, toff
2500 4000
IB(off) = IC/2 TJ = 25C IB(off) = IC/2
VCC = 15 V 3500 TJ = 125C VCC = 15 V
IC/IB = 5
2000 VZ = 300 V VZ = 300 V
LC = 200 H 3000 IC = 3 A LC = 200 H
t si , STORAGE TIME (ns)
1500 2500
t, TIME (ns)
2000
1000 1500
1000
500
TJ = 25C 500 IC = 1.3 A
TJ = 125C IC/IB = 10
0 0
0 1 2 3 4 5 6 7 8 3 4 5 6 7
IC COLLECTOR CURRENT (AMPS) hFE, FORCED GAIN
Figure 9. Inductive Storage Time, tsi Figure 10. Inductive Storage Time, tsi(hFE)
250 250
tc IB(off) = IC/2
VCC = 15 V
200 VZ = 300 V
200 tc LC = 200 H
150 tfi
t, TIME (ns)
t, TIME (ns)
150 tfi
100
IB(off) = IC/2 100

50 VCC = 15 V
VZ = 300 V TJ = 25C TJ = 25C
LC = 200 H TJ = 125C TJ = 125C
0 50
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Figure 11. Inductive Switching, tc and tfi Figure 12. Inductive Switching, tc and tfi
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BUL146 BUL146F

130 250
IC = 1.3 A
IC = 1.3 A
120
TC , CROSS-OVER TIME (ns)

IC = 3 A 200
110
Tfi , FALL TIME (ns)
100
150
IB(off) = IC/2
90 VCC = 15 V
VZ = 300 V IC = 3 A
80 LC = 200 H 100 IB(off) = IC/2
VCC = 15 V
70 TJ = 25C TJ = 25C VZ = 300 V
TJ = 125C TJ = 125C LC = 200 H
60 50
3 4 5 6 7 8 9 10 11 12 13 14 15 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 13. Inductive Fall Time Figure 14. Inductive CrossOver Time
GUARANTEED SAFE OPERATING AREA INFORMATION

100 7
DC (BUL146) TC 125C
6 IC/IB 4
I C , COLLECTOR CURRENT (AMPS)
5 ms 1 ms 10 s 1 s LC = 500 H
10
5
EXTENDED 4
1 SOA
3
VBE(off)
2
0.1 -5 V
1
0V
0 -1, 5 V
0.01
10 100 1000 0 200 400 600 800
Figure 15. Forward Bias Safe Operating Area Figure 16. Reverse Bias Switching Safe Operating Area
There are two limitations on the power handling ability of a tran-

sistor: average junction temperature and second breakdown. Safe
operating area curves indicate IC VCE limits of the transistor that
1,0
must be observed for reliable operation; i.e., the transistor must not
be subjected to greater dissipation than the curves indicate. The data
SECOND BREAKDOWN of Figure 15 is based on TC = 25C; TJ(pk) is variable depending on
0,8
DERATING power level. Second breakdown pulse limits are valid for duty
cycles to 10% but must be derated when TC > 25C. Second break-
0,6 down limitations do not derate the same as thermal limitations. Al-
lowable current at the voltages shown in Figure 15 may be found at
any case temperature by using the appropriate curve on Figure 17.
0,4
TJ(pk) may be calculated from the data in Figure 20. At any case tem-
peratures, thermal limitations will reduce the power that can be han-
THERMAL DERATING
0,2 dled to values less than the limitations imposed by second break-
down. For inductive loads, high voltage and current must be sus-
tained simultaneously during turnoff with the basetoemitter
0,0
20 40 60 80 100 120 140 160 junction reversebiased. The safe level is specified as a reverse
TC, CASE TEMPERATURE (C) biased safe operating area (Figure 16). This rating is verified under
clamped conditions so that the device is never subjected to an ava-
Figure 17. Forward Bias Power Derating lanche mode.
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BUL146 BUL146F
5 10
VCE
4 9 IC 90% IC
tfi
3 dyn 1 s 8
tsi
2 7
dyn 3 s
1 6
tc 10% IC
VOLTS
0 5 VCLAMP 10% VCLAMP

-1 4
90% IB IB 90% IB1
-2 3
-3 1 s 2
-4 3 s 1
IB
-5 0
0 1 2 3 4 5 6 7 8
0 1 2 3 4
TIME 5 6 7 8
TIME
Figure 18. Dynamic Saturation Voltage Measurements Figure 19. Inductive Switching Measurements
+15 V
IC PEAK
1 F MTP8P10 100 F
100
150
3W VCE PEAK
3W
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
COMMON V(BR)CEO(sus) INDUCTIVE SWITCHING RBSOA
MTP12N10
150 L = 10 mH L = 200 H L = 500 H
500 F 3W RB2 = RB2 = 0 RB2 = 0
VCC = 20 VOLTS VCC = 15 VOLTS VCC = 15 VOLTS
1 F IC(pk) = 100 mA RB1 SELECTED FOR RB1 SELECTED
DESIRED IB1 FOR DESIRED IB1
-Voff

1
D = 0.5
0.2
(NORMALIZED)
0.1 P(pk)
PULSE TRAIN SHOWN
0.02
t1 READ TIME AT t1
t2 TJ(pk) - TC = P(pk) RJC(t)
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
Figure 20. Typical Thermal Response (ZJC(t)) for BUL146
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BUL146 BUL146F

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.00
D = 0.5
0.2
0.10 0.1 RJC = 3.125C/W MAX
D CURVES APPLY FOR
0.05
POWER PULSE TRAIN
t1 SHOWN READ TIME AT t1
0.02 t2
0.01
0.01 0.10 1.00 10.00 100.00 1000
t, TIME (ms)
Figure 21. Typical Thermal Response for BUL146F
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270
BUL146 BUL146F
TEST CONDITIONS FOR ISOLATION TESTS*

MOUNTED MOUNTED MOUNTED
FULLY ISOLATED FULLY ISOLATED FULLY ISOLATED
CLIP PACKAGE CLIP PACKAGE PACKAGE
0.107 MIN 0.107 MIN
LEADS LEADS LEADS
HEATSINK HEATSINK HEATSINK

0.110 MIN
Figure 22a. Screw or Clip Mounting Figure 22b. Clip Mounting Position Figure 22c. Screw Mounting Position
Position for Isolation Test Number 1 for Isolation Test Number 2 for Isolation Test Number 3
*Measurement made between leads and heatsink with all leads shorted together
MOUNTING INFORMATION**
4-40 SCREW CLIP
PLAIN WASHER
HEATSINK
COMPRESSION WASHER
NUT HEATSINK
Figure 23a. ScrewMounted Figure 23b. ClipMounted
Figure 23. Typical Mounting Techniques

for Isolated Package
Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a
screw torque of 6 to 8 in . lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain
a constant pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 440 screw, without washers, and applying a torque in excess of 20 in . lbs will
cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
Additional tests on slotted 440 screws indicate that the screw slot fails between 15 to 20 in . lbs without adversely affecting the
package. However, in order to positively ensure the package integrity of the fully isolated device, ON Semiconductor does not recom-
mend exceeding 10 in . lbs of mounting torque under any mounting conditions.
** For more information about mounting power semiconductors see Application Note AN1040.
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271
ON Semiconductor
SWITCHMODE BUL147
NPN Bipolar Power Transistor
POWER TRANSISTOR
The BUL147 have an applications specific stateoftheart die 8.0 AMPERES
designed for use in electric fluorescent lamp ballasts to 180 Watts and 700 VOLTS
in Switchmode Power supplies for all types of electronic equipment. 45 and 125 WATTS
These highvoltage/highspeed transistors offer the following:
High and Flat DC Current Gain
Fast Switching
Parametric Distributions are Tight and Consistent LottoLot
Two Package Choices: Standard TO220 or Isolated TO220
MAXIMUM RATINGS
Rating Symbol BUL147 Unit
CollectorEmitter Sustaining Voltage VCEO 400 Vdc BUL147
CollectorEmitter Breakdown Voltage VCES 700 Vdc CASE 221A09
TO220AB
Peak(1) ICM 16
Peak(1) IBM 8.0
Total Device Dissipation (TC = 25C) PD 125 Watts
Rating Symbol BUL44 Unit
Thermal Resistance Junction to Case RJC 1.0 C/W

May, 2001 Rev. 4 BUL147/D
BUL147

OFF CHARACTERISTICS
(TC = 125C) 500
ON CHARACTERISTICS
BaseEmitter Saturation Voltage (IC = 4.5 Adc, IB = 0.9 Adc) 0.92 1.25
(IC = 2.0 Adc, IB = 0.2 Adc) 0.25 0.5
(TC = 125C) 0.3 0.5
(IC = 4.5 Adc, IB = 0.9 Adc) 0.35 0.7
(TC = 125C) 0.35 0.8
(TC = 125C) 30
(TC = 125C) 7.0 11
DC Current Gain (IC = 2.0 Adc, VCE = 1.0 Vdc) (TC = 25C to 125C) 10 18
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cob 100 175 pF
Input Capacitance (VEB = 8.0 V) Cib 1750 2500 pF
1.0 3.0
Dynamic Saturation Volt-
Volt (IC = 2.0 Adc s (TC = 125C) 5.5
age: IB1 = 200 mAdc
VCC = 300 V) 3.0 0.8
3 0 s respectively after
3.0 VCE(dsat) Volts
rising IB1 reaches 90% of 1.0 3.3
(IC = 5.0 Adc s (TC = 125C) 8.5
final IB1
IB1 = 0.9
0 9 Adc
(see Figure 18) 3.0 0.4
VCC = 300 V)
s (TC = 125C) 1.0
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BUL147

IB2 = 1.0 Adc, VCC = 300 V) (TC = 125C) 190
(TC = 125C) 1.6
IB1 = 2.25 Adc, VCC = 300 V) (TC = 125C) 100
(TC = 125C) 2.0
IB2 = 1.0 Adc) (TC = 125C) 120
(TC = 125C) 1.9
(TC = 125C) 230
IB2 = 2.25 Adc) (TC = 125C) 100
(TC = 125C) 2.1
(TC = 125C) 200
IB2 = 0.9 Adc) (TC = 125C) 150
(TC = 125C) 4.3
(TC = 125C) 330
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BUL147
100 100
TJ = 125C VCE = 1 V TJ = 125C VCE = 5 V

TJ = 25C TJ = 25C
10 TJ = -20C 10 TJ = -20C
1 1
0.01 0.1 1 10 0.01 0.1 1 10
Figure 1. DC Current Gain @ 1 Volt Figure 2. DC Current Gain @ 5 Volts
2 10
TJ = 25C
1.5
V CE , VOLTAGE (VOLTS)
V CE , VOLTAGE (VOLTS)
1
IC = 1 A 3A 5A 8A 10 A
1
IC/IB = 10
0.1
0.5
IC/IB = 5
TJ = 25C
TJ = 125C
0 0.01
0.01 0.1 1 10 0.01 0.1 1 10
IB, BASE CURRENT (AMPS) IC COLLECTOR CURRENT (AMPS)
1.3 10000
Cib TJ = 25C
1.2
f = 1 MHz
1.1 1000
V BE , VOLTAGE (VOLTS)
1
C, CAPACITANCE (pF)
Cob
0.9
100
0.8
0.7 TJ = 25C
10
0.6
IC/IB = 5
0.5 TJ = 125C IC/IB = 10
0.4 1
0.01 0.1 1 10 1 10 100
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BUL147

600 4000
IB(off) = IC/2 IC/IB = 5 TJ = 25C IB(off) = IC/2
VCC = 300 V 3500 TJ = 125C VCC = 300 V
500 IC/IB = 10
PW = 20 s PW = 20 s
3000 I /I = 5
C B
400 TJ = 125C 2500
t, TIME (ns)
t, TIME (ns)
TJ = 25C
300 2000
1500
200
1000
100 IC/IB = 10
500
0 0
0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
3500 4000
3000 VCC = 15 V 3500 TJ = 125C VCC = 15 V
VZ = 300 V VZ = 300 V
IC/IB = 5 3000
LC = 200 H LC = 200 H
2500
2500 IC = 2 A
2000
t, TIME (ns)
2000
1500
1500
1000
1000
500 TJ = 25C 500
TJ = 125C IC/IB = 10 IC = 4.5 A
0 0
1 2 3 4 5 6 7 8 3 4 5 6 7 8 9 10 11 12 13 14 15
IC COLLECTOR CURRENT (AMPS) hFE, FORCED GAIN
300 250
TJ = 25C IB(off) = IC/2
tc TJ = 125C VCC = 15 V
250
200 VZ = 300 V
tc LC = 200 H
200
tfi 150
t, TIME (ns)
t, TIME (ns)
150
100
100
IB(off) = IC/2
VCC = 15 V 50
50 tfi
VZ = 300 V TJ = 25C
LC = 200 H TJ = 125C
0 0
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8
Figure 11. Inductive Switching, tc and tfi Figure 12. Inductive Switching, tc and tfi
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276
BUL147

180 300
TJ = 25C IB(off) = IC/2 IC = 2 A IB(off) = IC/2
TJ = 125C VCC = 15 V VCC = 15 V
160
VZ = 300 V 250 VZ = 300 V
TC , CROSSOVER TIME (ns)

IC = 2 A LC = 200 H LC = 200 H
140
200
120
150
100
IC = 4.5 A
100
80
TJ = 25C
IC = 4.5 A TJ = 125C
60 50
3 4 5 6 7 8 9 10 11 12 13 14 15 3 4 5 6 7 8 9 10 11 12 13 14 15

100 9
DC (BUL147) TC 125C
8
IC/IB 4
5 ms 1 ms 10 s 1 s
7 LC = 500 H
10
6
EXTENDED 5
1 SOA
4
3
0.1 -5 V
2
1
VBE(off) = 0 V -1, 5 V
0.01 0
10 100 1000 0 100 200 300 400 500 600 700 800

1.0 operating area curves indicate IC VCE limits of the transistor that
SECOND BREAKDOWN be subjected to greater dissipation than the curves indicate. The data
0.8
DERATING of Figure 15 is based on TC = 25C; TJ(pk) is variable depending on

power level. Second breakdown pulse limits are valid for duty cycles
0.6 to 10% but must be derated when TC > 25C. Second breakdown li-
mitations do not derate the same as thermal limitations. Allowable
current at the voltages shown in Figure 15 may be found at any case
0.4
temperature by using the appropriate curve on Figure 17. TJ(pk) may
be calculated from the data in Figure 20 and NO TAG. At any case
THERMAL DERATING
0.2 temperatures, thermal limitations will reduce the power that can be
handled to values less than the limitations imposed by second break-
down. For inductive loads, high voltage and current must be sus-
0.0
20 40 60 80 100 120 140 160 tained simultaneously during turnoff with the basetoemitter
TC, CASE TEMPERATURE (C) junction reversebiased. The safe level is specified as a reverse
biased safe operating area (Figure 16). This rating is verified under
Figure 17. Forward Bias Power Derating clamped conditions so that the device is never subjected to an ava-
lanche mode.
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277
BUL147
5 10
VCE
4 9 IC 90% IC
tfi
3 dyn 1 s 8
tsi
2 7
dyn 3 s
1 6
tc 10% IC
VOLTS

-1 4
90% IB IB 90% IB1
-2 3
-3 1 s 2
-4 3 s 1
IB
-5 0
0 1 2 3 4 5 6 7 8
0 1 2 3 4
TIME 5 6 7 8
TIME
+15 V
IC PEAK
1 F MTP8P10 100 F
100
150
3W VCE PEAK
3W
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
V(BR)CEO(sus) INDUCTIVE SWITCHING RBSOA
MTP12N10
150 L = 10 mH L = 200 H L = 500 H
500 F 3W RB2 = RB2 = 0 RB2 = 0
-Voff
COMMON

1
D = 0.5
0.2
(NORMALIZED)

0.1 RJC = 1.0C/W MAX
t1 READ TIME AT t1
t2
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
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ON Semiconductor
SWITCHMODE BUL44
NPN Bipolar Power Transistor
POWER TRANSISTOR
The BUL44 have an applications specific stateoftheart die 2.0 AMPERES
designed for use in 220 V line operated Switchmode Power supplies 700 VOLTS
and electronic light ballasts. These high voltage/high speed transistors 40 and 100 WATTS
offer the following:
Fast Switching
Tight Parametric Distributions are Consistent LottoLot
MAXIMUM RATINGS
BUL44
CASE 221A06
EmitterBase Voltage VEBO 9.0 Vdc TO220AB
Peak(1) ICM 5.0
Peak(1) IBM 2.0

BUL44

OFF CHARACTERISTICS
(TC = 125C) 500
ON CHARACTERISTICS
BaseEmitter Saturation Voltage (IC = 0.4 Adc, IB = 40 mAdc) VBE(sat) 0.85 1.1 Vdc
(IC = 1.0 Adc, IB = 0.2 Adc) 0.92 1.25
(IC = 0.4 Adc, IB = 40 mAdc) 0.20 0.5
(TC = 125C) 0.20 0.5
(IC = 1.0 Adc, IB = 0.2 Adc) 0.25 0.6
(TC = 125C) 0.25 0.6
DC Current Gain hFE
(IC = 0.2 Adc, VCE = 5.0 Vdc) 14 34
(TC = 125C) 32
(IC = 0.4 Adc, VCE = 1.0 Vdc) 12 20
(TC = 125C) 12 20
(IC = 1.0 Adc, VCE = 1.0 Vdc) 8.0 14
(TC = 125C) 7.0 13
(IC = 10 mAdc, VCE = 5.0 Vdc) 10 22
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz) COB 38 60 pF
Input Capacitance (VEB = 8.0 V) CIB 380 600 pF
1.0 2.5
(IC = 0.4 Adc s (TC = 125C) 2.7
Dynamic Saturation Volt-
Volt IB1 = 40 mAdc
age: VCC = 300 V) 3.0 1.3
VCE(dsat) Vdc
3.0 s respectively after 1.0 3.2
rising IB1 reaches 90% of (IC = 1.0 Adc s (TC = 125C) 7.5
final IB1 IB1 = 0.2
0 2 Adc
VCC = 300 V) 3.0 1.25
s (TC = 125C) 1.6
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle 10%. (continued)
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280
BUL44

TurnOn Time (IC = 0.4 Adc, IB1 = 40 mAdc ton 40 100 ns
IB2 = 0.2 Adc, VCC = 300 V) (TC = 125C) 40
TurnOff Time (IC = 0.4 Adc, IB1 = 40 mAdc toff 1.5 2.5 s
IB2 = 0.2 Adc, VCC = 300 V) (TC = 125C) 2.0
IB1 = 0.5 Adc, VCC = 300 V) (TC = 125C) 85
TurnOff Time (IC = 1.0 Adc, IB1 = 0.2 Adc toff 1.75 2.5 s
IB2 = 0.5 Adc, VCC = 300 V) (TC = 125C) 2.10
Fall Time (IC = 0.4 Adc, IB1 = 40 mAdc tfi 125 200 ns
IB2 = 0.2 Adc) (TC = 125C) 120
(TC = 125C) 0.8
(TC = 125C) 110
IB2 = 0.5 Adc) (TC = 125C) 120
(TC = 125C) 2.25
(TC = 125C) 210
IB2 = 160 mAdc) (TC = 125C) 180
(TC = 125C) 4.2
(TC = 125C) 350
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BUL44
100 100
VCE = 1 V VCE = 5 V
TJ = 125C TJ = 125C

TJ = 25C
TJ = 25C
TJ = -20C
10 10
1.0 1.0
0.01 0.1 1.0 10 0.01 0.1 1.0 10
Figure 21. DC Current Gain at 1 Volt Figure 22. DC Current Gain at 5 Volts
2.0 10
TJ = 25C
IC/IB = 10
1.0
IC/IB = 5
1.0
2A 0.1
1.5 A
1A
0.4 A TJ = 25C
IC = 0.2 A TJ = 125C
0 0.01
1.0 10 100 1000 0.01 0.1 1.0 10
Voltage
1.2 1000
1.1 CIB TJ = 25C

f = 1 MHz
1.0
C, CAPACITANCE (pF)
100
0.9
0.8
COB
TJ = 25C
0.7
10
0.6
TJ = 125C
0.5 IC/IB = 5
IC/IB = 10
0.4 1.0
0.01 0.1 1.0 10 1.0 10 100
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282
BUL44

300 6.0
250 VCC = 300 V 5.0 IC/IB = 5 VCC = 300 V
PW = 20 s PW = 20 s
200 4.0
IC/IB = 10
t, TIME (s)
t, TIME (ns)

150 3.0 TJ = 25C
IC/IB = 5 TJ = 125C
100 2.0
50 TJ = 25C 1.0
TJ = 125C IC/IB = 10
0 0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
2500 2.0
IC/IB = 5 IB(off) = IC/2 TJ = 25C IB(off) = IC/2
VCC = 15 V TJ = 125C VCC = 15 V
2000 VZ = 300 V VZ = 300 V
1.5
LC = 200 H LC = 200 H
IC = 1 A
1500
t, TIME (ns)
1000 1.0
500
TJ = 25C IC = 0.4 A
TJ = 125C IC/IB = 10
0 0.5
0.4 0.8 1.2 1.6 2.0 2.4 5.0 6.0 7.0 8.0 9.0 10 11 12 13 14 15
Figure 29. Inductive Storage Time, tsi Figure 30. Inductive Storage Time
250 200
IB(off) = IC/2
VCC = 15 V
200 VZ = 300 V
tc LC = 200 H
150 tc
150
t, TIME (ns)
t, TIME (ns)
tfi
100
100 tfi
IB(off) = IC/2
50 VCC = 15 V
VZ = 300 V TJ = 25C TJ = 25C
LC = 200 H TJ = 125C TJ = 125C
0 50
0.4 0.8 1.2 1.6 2.0 2.4 0.4 0.8 1.2 1.6 2.0 2.4
Figure 31. Inductive Switching, Figure 32. Inductive Switching,

tc and tfi IC/IB = 5 tc and tfi IC/IB = 10
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283
BUL44

170 190
160 IC = 1 A
VCC = 15 V 170 VCC = 15 V
150 VZ = 300 V VZ = 300 V

LC = 200 H 150 LC = 200 H
140
IC = 0.4 A
130 130
IC = 0.4 A
120 110
110
90
IC = 1 A
100
70 TJ = 25C
TJ = 25C
90 TJ = 125C
TJ = 125C
80 50
5.0 6.0 7.0 8.0 9.0 10 11 12 13 14 15 5.0 6.0 7.0 8.0 9.0 10 11 12 13 14 15

10 2.5
10s
1s
TC 125C
DC (BUL44) 5ms 1ms
2.0 GAIN 4
50s LC = 500 H
Extended
1.0
SOA
1.5
1.0
0.1 -5 V
0.5
-1.5 V
0V
0.01 0
10 100 1000 0 100 200 300 400 500 600 700
1.0 limits of the transistor that must be observed for reliable

SECOND BREAK- dissipation than the curves indicate. The data of figure 35 is
0.8
DOWN DERATING based on TC = 25C; TJ(PK) is variable depending on power

level. Second breakdown pulse limits are valid for duty cycles
0.6 to 10% but must be derated when TC > 25C. Second
THERMAL DERATING limitations. Allowable current at the voltages shown on figure
0.4
35 may be found at any case temperature by using the
appropriate curve on figure 37. TJ(PK) may be calculated from
0.2
the data in figure 40. At any case temperatures, thermal
limitations will reduce the power than can be handled to
0 values less than the limitations imposed by second
20 40 60 80 100 120 140 16
breakdown. For inductive loads, high voltage and current
must be sustained simultaneously during turnoff with the
Figure 37. Forward Bias Power Derating basetoemitter junction reversebiased. The safe level is
specified as a reversebiased safe operating area (Figure 36).
There are two limitations on the power handling ability of This rating is verified under clamped conditions so that the
a transistor: average junction temperature and second device is never subjected to an avalanche mode.
breakdown. Safe operating area curves indicate ICVCE
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284
BUL44
5 10
VCE
4 9 IC 90% IC
tfi
3 dyn 1 s 8
tsi
2 7
dyn 3 s
1 6
tc 10% IC
VOLTS

-1 4
90% IB IB 90% IB1
-2 3
-3 1 s 2
-4 3 s 1
IB
-5 0
0 1 2 3 4 5 6 7 8
0 1 2 3 4
TIME 5 6 7 8
TIME
+15 V
IC PEAK
1 F MTP8P10 100 F
100
150
3W VCE PEAK
3W
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
MTP12N10
150 L = 10 mH L = 200 H L = 500 H
500 F 3W RB2 = RB2 = 0 RB2 = 0
-Voff
1.0
0.5
r(t) TRANSIENT THERMAL
0.2
0.01
0.1
0.05
P(pk)
0.02 D CURVES APPLY FOR
t1 POWER PULSE TRAIN
SHOWN READ TIME AT t1
SINGLE PULSE t2 TJ(pk) - TC = P(pk) RJC1(t)
0.01
0.01 0.1 1.0 10 100 1000
t, TIME (ms)
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285
ON Semiconductor
BUL45D2
High Speed, High Gain Bipolar
NPN Power Transistor with POWER TRANSISTORS
Integrated Collector-Emitter 5 AMPERES

700 VOLTS
Diode and Built-in Efficient 75 WATTS
Antisaturation Network
The BUL45D2 is stateofart High Speed High gain BIPolar
transistor (H2BIP). High dynamic characteristics and lot to lot
minimum spread (150 ns on storage time) make it ideally suitable for
light ballast applications. Therefore, there is no need to guarantee an
hFE window.
Main features:
Low Base Drive Requirement
High Peak DC Current Gain (55 Typical) @ IC = 100 mA
Extremely Low Storage Time Min/Max Guarantees Due to the
H2BIP Structure which Minimizes the Spread
Integrated CollectorEmitter Free Wheeling Diode
Fully Characterized and Guaranteed Dynamic VCE(sat)
6 Sigma Process Providing Tight and Reproductible Parameter
Spreads
Its characteristics make it also suitable for PFC application. CASE 221A09
TO220AB
MAXIMUM RATINGS

Rating
Symbol
VCEO
Value
400
Unit
Vdc


VCBO
VCES
700
700
Vdc
Vdc

EmitterBase Voltage

VEBO
IC
12
5
Vdc
Adc

Peak (1) ICM 10





Thermal Resistance

Junction to Case

RJC 1.65
C/W



March, 2001 Rev. 2 BUL45D2/D
BUL45D2


OFF CHARACTERISTICS


(IC = 100 mA, L = 25 mH)


(ICBO = 1 mA)

(IEBO = 1 mA)



ICEO 100 Adc

Collector Cutoff Current (VCE = Rated VCES, VEB = 0) @ TC = 25C ICES 100 Adc

@ TC = 125C 500
Collector Cutoff Current (VCE = 500 V, VEB = 0) @ TC = 125C 100


(VEB = 10 Vdc, IC = 0)

IEBO 100 Adc
ON CHARACTERISTICS


(IC = 0.8 Adc, IB = 80 mAdc) @ TC = 25C 0.8 1
@ TC = 125C 0.7 0.9

(IC = 2 Adc, IB = 0.4 Adc)

@ TC = 25C
@ TC = 125C
0.89
0.79
1
0.9


(IC = 0.8 Adc, IB = 80 mAdc) @ TC = 25C 0.28 0.4
@ TC = 125C 0.32 0.5

(IC = 2 Adc, IB = 0.4 Adc)

@ TC = 25C
@ TC = 125C
0.32
0.38
0.5
0.6

(IC = 0.8 Adc, IB = 40 mAdc) @ TC = 25C 0.46 0.75

@ TC = 125C 0.62 1

DC Current Gain hFE

(IC = 0.8 Adc, VCE = 1 Vdc) @ TC = 25C 22 34


@ TC = 125C
@ TC = 25C
20
10
29
14

@ TC = 125C 7 9.5

DIODE CHARACTERISTICS

Forward Diode Voltage VEC V
(IEC = 1 Adc) @ TC = 25C 1.04 1.5

@ TC = 125C 0.7

(IEC = 2 Adc) @ TC = 25C 1.2 1.6

@ TC = 125C

(IEC = 0.4 Adc) @ TC = 25C 0.85 1.2
@ TC = 125C 0.62

Forward Recovery Time (see Figure 27)

(IF = 1 Adc, di/dt = 10 A/s) @ TC = 25C
Tfr 330 ns

(IF = 2 Adc, di/dt = 10 A/s) @ TC = 25C 360

(IF = 0.4 Adc, di/dt = 10 A/s) @ TC = 25C 320
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BUL45D2





fT 13 MHz



(VCB = 10 Vdc, IE = 0, f = 1 MHz)

(VEB = 8 Vdc)

Dynamic Saturation

IC = 1 A
IB1 = 100 mA
@ 1 s @ TC = 25C
@ TC = 125C
VCE(dsat) 3.7
9.4
V

Voltage:
VCC = 300 V @ 3 s @ TC = 25C 0.35 V
Determined 1 s and

@ TC = 125C 2.7
3 s respectively
@ 1 s

after rising IB1 @ TC = 25C 3.9 V
reaches 90% of final IC = 2 A @ TC = 125C 12

IB1 IB1 = 0
0.8
8A
VCC = 300 V @ 3 s @ TC = 25C 0.4 V

@ TC = 125C 1.5


@ TC = 125C 105
IB2 = 1 Adc
s

Turnoff Time VCC = 300 Vdc @ TC = 25C toff 1.15 1.3
@ TC = 125C 1.5

Turnon Time

IB2 = 0.4
0 4 Adc
@ TC = 25C
@ TC = 125C
ton 90
110
150 ns

@ TC = 125C 3.1


@ TC = 125C 93

Storage Time IC = 1 Adc @ TC = 25C ts 0.72 0.9 s

IB1 = 100 mAdc @ TC = 125C 1.05
IB2 = 500 mAdc


@ TC = 125C 95

@ TC = 125C 105

Storage Time

IC = 2 Adc
IB1 = 0.4 Adc
IB2 = 0.4 Adc
@ TC = 25C
@ TC = 125C
ts 1.95
2.9
2.25 s


@ TC = 125C 450
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BUL45D2
100 100
VCE = 1 V VCE = 5 V
80 TJ = 125C 80 TJ = 125C

TJ = 25C TJ = 25C
60 60
40 TJ = -20C 40 TJ = -20C
20 20
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
4 10
TJ = 25C
IC/IB = 5
TJ = 25C
3
2 1
TJ = 125C
5A
1 3A
2A 4A
1A TJ = -20C
IC = 500 mA
0 0.1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
IB, BASE CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS)

Voltage
10 10
IC/IB = 10 IC/IB = 20
1 1
TJ = 25C TJ = 125C
TJ = -20C TJ = -20C
TJ = 125C
TJ = 25C
0.1 0.1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Figure 45. CollectorEmitter Saturation Figure 46. CollectorEmitter Saturation

Voltage Voltage
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289
BUL45D2
10 10

TJ = 25C
1 TJ = -20C 1 TJ = -20C
TJ = 125C
TJ = 125C
TJ = 25C
0.1 0.1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Figure 47. BaseEmitter Saturation Region Figure 48. BaseEmitter Saturation Region
10 10
IC/IB = 20
FORWARD DIODE VOLTAGE (VOLTS)
1 25C
1 TJ = -20C
125C
TJ = 125C
TJ = 25C
0.1 0.1
0.001 0.01 0.1 1 10 0.01 0.1 1 10
IC, COLLECTOR CURRENT (AMPS) REVERSE EMITTER-COLLECTOR CURRENT (AMPS)
Figure 49. BaseEmitter Saturation Region Figure 50. Forward Diode Voltage
1000 1000
Cib (pF) TJ = 25C TJ = 25C
C, CAPACITANCE (pF)
100 800
BVCER (VOLTS)
Cob (pF)
700
10 600
BVCER(sus) @ 200 mA
500
1 400
1 10 100 10 100 1000
Figure 51. Capacitance Figure 52. BVCER = f(ICER)
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BUL45D2
1000 5
IBon = IBoff TJ = 125C IBon = IBoff
VCC = 300 V TJ = 25C IC/IB = 10 VCC = 300 V
800 4
PW = 20 s PW = 20 s
t, TIME (s)
600
t, TIME (ns)

IC/IB = 10
400 2
IC/IB = 5
IC/IB = 5
200 1 TJ = 125C
TJ = 25C
0 0
0.5 1 1.5 2 2.5 3 3.5 4 0.5 1 1.5 2 2.5 3 3.5 4
Figure 53. Resistive Switch Time, ton Figure 54. Resistive Switch Time, toff
4 5
IBon = IBoff IBon = IBoff
IC/IB = 5 VCC = 15 V
VCC = 15 V
4 VZ = 300 V
VZ = 300 V
3 LC = 200 H
LC = 200 H
3
t, TIME (s)
t, TIME (s)
2
2
1 1
TJ = 125C TJ = 125C
TJ = 25C TJ = 25C
0 0
0 1 2 3 4 0 1 2 3 4
tsi @ IC/IB = 5 tsi @ IC/IB = 10
600 400
IBon = IBoff TJ = 125C IBoff = IBon
500 VCC = 15 V TJ = 25C VCC = 15 V
VZ = 300 V VZ = 300 V
LC = 200 H tc 300
400 LC = 200 H
t, TIME (ns)
t, TIME (ns)
300 200
200
100
100 TJ = 125C
tfi TJ = 25C
0 0
0 1 2 3 4 0 1 2 3
IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 4
Figure 57. Inductive Switching, Figure 58. Inductive Switching,

tc & tfi @ IC/IB = 5 tfi @ IC/IB = 10
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291
BUL45D2
1500 5
TJ = 125C IBon = IBoff
IBoff = IBon TJ = 125C
TJ = 25C VCC = 15 V
VCC = 15 V TJ = 25C
VZ = 300 V
VZ = 300 V IC = 1 A

LC = 200 H
1000 LC = 200 H 4
t, TIME (ns)
500 3
IC = 2 A
0 2
0 1 2 3 4 0 5 10 15 20
Figure 59. Inductive Switching, Figure 60. Inductive Storage Time

tc @ IC/IB = 10
450 1400
IBoff = IBon TJ = 125C IBon = IBoff TJ = 125C
VCC = 15 V 1200
TJ = 25C VCC = 15 V TJ = 25C
VZ = 300 V
350 IC = 1 A VZ = 300 V
LC = 200 H 1000 LC = 200 H
IC = 2 A
800
250
600
400
150
IC = 2 A 200
IC = 1 A
50 0
2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20
3000 360
IB1 = IB2 IBon = IBoff
t fr , FORWARD RECOVERY TIME (ns)
VCC = 15 V dI/dt = 10 A/s

VZ = 300 V TC = 25C
LC = 200 H
2000 340
t, TIME (ns)
IB = 50 mA
IB = 100 mA
1000 320
IB = 200 mA
IB = 500 mA
IB = 1 A
0 300
0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2
IC, COLLECTOR CURRENT (AMPS) IF, FORWARD CURRENT (AMP)
Figure 63. Inductive Storage Time, tsi Figure 64. Forward Recovery Time tfr
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292
BUL45D2
10
VCE 9 IC 90% IC
dyn 1 s
8 tfi
tsi
dyn 3 s 7
6
0V 10% IC
5 Vclamp 10% Vclamp
tc
4
90% IB 3 IB 90% IB1
1 s 2
IB 1
3 s
0
0 1 2 3 4 5 6 7 8
TIME TIME
Figure 65. Dynamic Saturation Figure 66. Inductive Switching Measurements

Voltage Measurements
VFRM VFR (1.1 VF unless

otherwise specified)
VF VF
tfr
0.1 VF
0
IF
10% IF
0 2 4 6 8 10
Figure 67. tfr Measurements
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293
BUL45D2
+15 V
IC PEAK
1 F 100 MTP8P10 100 F
150
3W 3W VCE PEAK
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
COMMON MTP12N10
500 F 3W L = 10 mH L = 200 H L = 500 H
RB2 = RB2 = 0 RB2 = 0
100 6
TC 125C
5 GAIN 5
10 1 s LC = 2 mH
10 s 4
EXTENDED SOA
5 ms 1 ms
1 3
DC
2
-5 V
0.1
1 0V -1.5 V
0.01 0
10 100 1000 200 300 400 500 600 700 800
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BUL45D2
SECOND BREAKDOWN
0.8 DERATING

0.6
THERMAL DERATING
0.4
0.2
0
20 40 60 80 100 120 140 160
1
0.5
0.2
(NORMALIZED)
0.1
0.1 0.05 RJC = 2.5C/W MAX
0.02 t1 PULSE TRAIN SHOWN
t2 READ TIME AT t1
0.01
0.01 0.1 1 10 100 1000
t, TIME (ms)
Figure 71. Typical Thermal Response (ZJC(t)) for BUL45D2
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295
ON Semiconductor
NPN Silicon Power Transistor BUL45

High Voltage SWITCHMODE Series
Designed for use in electronic ballast (light ballast) and in POWER TRANSISTOR
Switchmode Power supplies up to 50 Watts. Main features include: 5.0 AMPERES
700 VOLTS
Improved Efficiency Due to: 35 and 75 WATTS
Low Base Drive Requirements (High and Flat DC Current Gain hFE)
Low Power Losses (OnState and Switching Operations)
Fast Switching: tfi = 100 ns (typ) and tsi = 3.2 s (typ)
@ IC = 2.0 A, IB1 = IB2 = 0.4 A
Tight Parametric Distributions Consistent LottoLot
MAXIMUM RATINGS
BUL45
EmitterBase Voltage VEBO 9.0 Vdc CASE 221A06
TO220AB
Peak(1) ICM 10

OFF CHARACTERISTICS
(TC = 125C) 100

BUL45
ELECTRICAL CHARACTERISTICS continued (TC = 25C unless otherwise noted)

ON CHARACTERISTICS
(IC = 2.0 Adc, IB = 0.4 Adc) 0.89 1.25
(IC = 1.0 Adc, IB = 0.2 Adc) 0.175 0.25
(TC = 125C) 0.150
(IC = 2.0 Adc, IB = 0.4 Adc) 0.25 0.4
(TC = 125C) 0.275
(TC = 125C) 32
(TC = 125C) 5.0 12
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cob 50 75 pF
Input Capacitance (VEB = 8.0 Vdc) Cib 920 1200 pF
Dynamic Saturation Volt- 1.0 1.75
age: (IC = 1.0 Adc s (TC = 125C) 4.4
IB1 = 100 mAdc
Determined 1.0 s and VCC = 300 V) 3.0 0.5
3.0 s respectively
res ectively after s (TC = 125C) VCE 1.0
Vdc
rising IB1 reaches 90% 1.0 (Dyn sat) 1.85
of final IB1 (IC = 2.0 Adc s (TC = 125C) 6.0
(see Figure 18) IB1 = 400 mAdc
VCC = 300 V) 3.0 0.5
s (TC = 125C) 1.0
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297
BUL45
SWITCHING CHARACTERISTICS: Resistive Load

TurnOn Time (IC = 2.0 Adc, IB1 = IB2 = 0.4 Adc ton 75 110 ns
Pulse Width = 20 s, (TC = 125C) 120
Duty Cycle < 20%
TurnOff Time VCC = 300 V) toff 2.8 3.5 s
(TC = 125C) 3.5
SWITCHING CHARACTERISTICS: Inductive Load (VCC = 15 Vdc, LC = 200 H, Vclamp = 300 Vdc)
IB2 = 0.4 Adc) (TC = 125C) 200
(TC = 125C) 4.2
(TC = 125C) 400
IB2 = 0.5 Adc) (TC = 125C) 100
(TC = 125C) 1.5
(TC = 125C) 170
IB2 = 2.0 Adc) (TC = 125C)
(TC = 125C)
(TC = 125C)
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298
BUL45
100 100
TJ = 25C VCE = 1 V TJ = 25C VCE = 5 V
TJ = 125C TJ = 125C

TJ = -20C TJ = -20C
10 10
1 1
0.01 0.10 1.00 10.00 0.01 0.10 1.00 10.00
Figure 1. DC Current Gain @ 1 Volt Figure 2. DC Current Gain at @ 5 Volts
2.0 10
TJ = 25C
1.5
1.0
1 A 1.5 2A 3A 4A 5A 6A
1.0 A
0.1 IC/IB = 10
0.5
IC/IB = 5 TJ = 25C
TJ = 125C
IC = 0.5 A
0 0.01
0.01 0.10 1.00 10.00 0.01 0.10 1.00 10.00
IB, BASE CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS)
Figure 3. CollectorEmitter Saturation Region Figure 4. CollectorEmitter Saturation Voltage
1.1 10000
TJ = 25C
1.0 f = 1 MHz
Cib
1000
0.9
C, CAPACITANCE (pF)
0.8
Cob
TJ = 25C 100
0.7
0.6
TJ = 125C 10
0.5 IC/IB = 10
IC/IB = 5
0.4 1
0.01 0.10 1.00 10.00 1 10 100 1000
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BUL45

1200 3000
VCC = 300 V TJ = 25C
1000 TJ = 125C 2500 IC/IB = 5 VCC = 300 V
PW = 20 s TJ = 125C
PW = 20 s
800 2000
t, TIME (ns)
t, TIME (ns)
IC/IB = 10
IC/IB = 10
600 1500
400 1000
200 500
IC/IB = 5
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
3500 3500
VZ = 300 V
3000 TJ = 125C LC = 200 H
VCC = 15 V 3000 VZ = 300 V
IC/IB = 5 IB(off) = IC/2
VCC = 15 V
2500 LC = 200 H
2500
IC = 1 A
2000
t, TIME (ns)
2000
1500
1500
1000
TJ = 25C 1000
500
TJ = 125C
IC/IB = 10 IC = 2 A
0 500
0 1 2 3 4 5 3 4 5 6 7 8 9 10 11 12 13 14 15
300 200
250 tc tc
150
200
t, TIME (ns)
t, TIME (ns)
150 100
100
VCC = 15 V IB(off) = IC/2
50
IB(off) = IC/2 VCC = 15 V tfi
50 tfi VZ = 300 V
LC = 200 H TJ = 25C TJ = 25C
VZ = 300 V TJ = 125C LC = 200 H TJ = 125C
0 0
0 1 2 3 4 5 0 1 2 3 4 5
Figure 11. Inductive Switching, tc & tfi, IC/IB = 5 Figure 12. Inductive Switching, tc & tfi, IC/IB = 10
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300
BUL45

150 300
VCC = 15 V
140 VZ = 300 V
TJ = 125C VCC = 15 V
250 IB(off) = IC/2
VZ = 300 V

130 LC = 200 H
IC = 1 A LC = 200 H IC = 1 A
120
200
110
100 150
90
100
80 IC = 2 A TJ = 25C
TJ = 125C IC = 2 A
70 50
3 4 5 6 7 8 9 10 11 12 13 14 15 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 13. Inductive Fall Time, tfi(hFE) Figure 14. Crossover Time

100 6
DC (BUL45) TC 125C
IC/IB 4

5
5ms 1ms 50s 10s 1s LC = 500 H
10
4
1.0 EXTENDED 3
SOA
2
0.1
-5 V
1
VBE(off) = 0 V -1.5 V
0.01 0
10 100 1000 300 400 500 600 700 800
1.0 operating area curves indicate IC VCE limits of the transistor that
SECOND BREAKDOWN be subjected to greater dissipation than the curves indicate. The
0.8
DERATING data of Figure 15 is based on TC = 25C; TJ(pk) is variable depend-

ing on power level. Second breakdown pulse limits are valid for
0.6 duty cycles to 10% but must be derated when TC 25C. Second
breakdown limitations do not derate the same as thermal limita-
tions. Allowable current at the voltages shown in Figure 15 may
0.4 be found at any case temperature by using the appropriate curve on
Figure 17. TJ(pk) may be calculated from the data in Figures 20. At
THERMAL DERATING any case temperatures, thermal limitations will reduce the power
0.2
that can be handled to values less than the limitations imposed by
second breakdown. For inductive loads, high voltage and current
0 must be sustained simultaneously during turnoff with the base
20 40 60 80 100 120 140 160
toemitter junction reversebiased. The safe level is specified as
TC, CASE TEMPERATURE (C) a reversebiased safe operating area (Figure 16). This rating is ver-
ified under clamped conditions so that the device is never sub-
jected to an avalanche mode.
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301
BUL45
5 10
VCE
4 9 IC 90% IC
tfi
3 dyn 1 s 8
tsi
2 7
dyn 3 s
1 6
tc 10% IC
VOLTS

-1 4
90% IB IB 90% IB1
-2 3
-3 1 s 2
-4 3 s 1
IB
-5 0
0 1 2 3 4 5 6 7 8
0 1 2 3 4
TIME 5 6 7 8
TIME
+15 V
IC PEAK
1 F MTP8P10 100 F
100
150
3W VCE PEAK
3W
MTP8P10 VCE
MPF930 RB1
MUR105 IB1
A
IB2
50 RB2
MJE210
MTP12N10
150 L = 10 mH L = 200 H L = 500 H
500 F 3W RB2 = RB2 = 0 RB2 = 0
-Voff

r(t) TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.00
D = 0.5
0.2
0.10 0.1 P(pk) RJC(t) = r(t) RJC

RJC = 2.5C/W MAX
0.05 D CURVES APPLY FOR
t1
POWER PULSE TRAIN
0.02 t2 SHOWN READ TIME AT t1
0.01
0.01 0.10 1.00 10.00 100.00 1000.00
t, TIME (ms)
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302
BUL45
The BUL45 Bipolar Power Transistors were specially demonstrate how well these devices operate. The circuit and
designed for use in electronic lamp ballasts. A circuit detailed component list are provided below.
designed by ON Semiconductor applications was built to
Q1 C5 400 V
D5
IC 0.1 F
MUR150
22 F 385 V 1000 V
47
D3
C1
470 k 1 T1A 15 F
D10 D9 TUBE
C4
T1B
D1 1N4007
D8 D7 D6
FUSE IC
Q2 C3 1000 V 400 V
MUR150 47
C2 10 nF C6 0.1 F
L
CTN 0.1 F 100 V D4
D2 1N5761 5.5 mH
AC LINE
1
220 V
Components Lists
Q1 = Q2 = BUL45 Transistor All resistors are 1/4 Watt, 5%

D1 = 1N4007 Rectifier R1 = 470 k
D2 = 1N5761 Rectifier R2 = R3 = 47
D3 = D4 = MUR150 R4 = R5 = 1 (these resistors are optional, and
D5 = D6 = MUR105 might be replaced by a short circuit)
D7 = D8 = D9 = D10 = 1N400 C1 = 22 F/385 V
CTN = 47 @ 25C C2 = 0.1 F
L = RM10 core, A1 = 400, B51 (LCC) 75 turns, C3 = 10 nF/1000 V
wire = 0.6 mm C4 = 15 nF/1000 V
T1 = FT10 toroid, T4A (LCC) C5 = C6 = 0.1 F/400 V
Primary: 4 turns
Secondaries: T1A: 4 turns
Secondaries: T1B: 4 turns
NOTES:
1. Since this design does not include the line input filter, it cannot be used asis in a practical industrial circuit.
2. The windings are given for a 55 Watt load. For proper operation they must be recalculated with any other loads.
Figure 21. Application Example
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303
ON Semiconductor
BUV20
SWITCHMODE Series BUV60
NPN Silicon Power Transistor
. . . designed for high speed, high current, high power applications. 50 AMPERES
High DC current gain: NPN SILICON
hFE min = 20 at IC = 25 A POWER
= 10 at IC = 50 A METAL TRANSISTOR
125 VOLTS
Low VCE(sat): 250 WATTS
VCE(sat) max. = 0.6 V at IC = 25 A
= 0.9 V at IC = 50 A
Very fast switching times:
TF = 0.25 s at IC = 50 A

MAXIMUM RATINGS

Rating Symbol BUV20 BUV60 Unit

CollectorEmititer Voltage VCEO(sus) 125 Vdc
CASE 197A05

CollectorBase Voltage VCBO 160 260 Vdc TO204AE
(TO3)

CollectorEmitter Voltage (VBE = VCEX 160 260 Vdc

1.5 V)
100 )

CollectorEmitter voltage (RBE = VCER 150 260 Vdc

CollectorCurrent Continuous
Peak (PW
IC
ICM
50
60
Adc
Apk

10 ms)

BaseCurrent continuous IB 10 Adc

Total Power Dissipation @ TC = PD 250 Watts
25C


Temperature Range

Characteristic Symbol BUV20 BUV60 Unit

Thermal Resistance, Junction to JC 0.7 C/W
Case
1.0
0.8
DERATING FACTOR
0.6
0.4
0.2
0 40 80 120 160 200

TC, TEMPERATURE (C)

May, 2001 Rev. 10 BUV20/D
BUV20 BUV60


OFF CHARACTERISTICS1


(IC = 200 mA, IB = 0, L = 25 mH) BUV20, BUV60

Collector Cutoff Current at Reverse Bias ICEX mAdc

(VCE = 140 V, VBE = 1.5 V) BUV20 3.0
(VCE = 140 V, VBE = 1.5 V, TC = 125C) BUV20 12

(VCE = 260 V, VBE = 1.5 V) BUV60

CollectorEmitter Cutoff Current ICEO 3.0 mAdc
(VCE = 100 V) BUV20
(IE = 50 mA)

EmitterBase Reverse Voltage

BUV20, BUV60
VEBO 7 V


(VEB = 5 V)

BUV20, BUV60
IEBO 1.0 mAdc
SECOND BREAKDOWN

Second Breakdown Collector Current with base forward biased IS/b Adc
(VCE = 20 V, t = 1 s)

12
(VCE = 40 V, t = 1 s) 1.5
DC Current Gain

ON CHARACTERISTICS1

hFE

(IC = 25 A, VCE = 2 V) BUV20 20 60
(IC = 50 A, VCE = 4 V) BUV20 10


(IC = 25 A, IB = 2.5 A) BUV20
VCE(sat)
0.6
Vdc

(IC = 50 A, IB = 5 A) BUV20 1.2


(IC = 50 A, IB = 5 A)0 BUV20 2.0

(IC = 25 A, IB = 1.25 A) BUV60 0.9

(IC = 50 A, IB = 5 A) BUV60 0.9

(IC = 60 A, IB = 7.5 A) BUV60 1.2

(IC = 50 A, IB = 5 A) BUV60 1.6

(IC = 60 A, IB = 7.5 A) BUV60 1.8

Current Gain Bandwidth Product fT 8.0 MHz
(VCE = 15 V, IC = 2 A, f = 4 MHz)

Turnon Time

SWITCHING CHARACTERISTICS (Resistive Load)

ton 1.5 s

Storage Time

Fall Time

(IC = 50 A
A, IB1 = IB2 = 5 A,
VCC = 30 V, RC = 0.6 )
A
ts
tf
1.2
0.25
1 Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
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305
BUV20 BUV60


10 operation i.e., the transistor must not be subjected to greater
The data of Figure 2 is based on TC = 25C. TJ(pk) is
1 limitations do not derate the same as thermal limitations.
At high case temperatures, thermal limitations will reduce
1 10 100 125
2.0 100
IC/IB = 10 VCE = 4 V
1.6 80
V, VOLTAGE (V)
1.2 VBE(sat) 60
0.8 40
VCE(sat)
0.4 20
0 0
1 10 100 1 10
Figure 3. On Voltages Figure 4. DC Current Gain
VCC = 30 V
IC/IB1 = 10 VCC
IB1 = IB2
3.0
104 F
2.0 RC
t, TIME (s)

1.0 tS IB2
IB1 VCC = 30 V
0.4 ton RC = 0.6
0.3
0.2 tF
RC Non inductive resistance
0 10 20 30 40 50
Figure 6. Switching Times Test Circuit
Figure 5. Resistive Switching Performance
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306
ON Semiconductor
SWITCHMODE Series BUV21

NPN Silicon Power Transistor
. . . designed for high speed, high current, high power applications. 40 AMPERES
NPN SILICON
High DC current gain: POWER
hFE min. = 20 at IC = 12 A METAL TRANSISTOR
Low VCE(sat), VCE(sat) 200 VOLTS
max. = 0.6 V at IC = 8 A 250 WATTS
TF max. = 0.4 s at IC = 25 A
MAXIMUM RATINGS

Rating
Symbol
VCEO(sus)
Value
200
Unit
Vdc

CollectorBase Voltage VCBO 250 Vdc CASE 197A05
TO204AE

EmitterBase Voltage VEBO 7 Vdc (TO3)

CollectorEmitter Voltage (VBE = 1.5 V) VCEX 250 Vdc
CollectorEmitter Voltage (RBE = 100 )

VCER 240 Vdc
CollectorCurrent Continuous IC 40 Adc

Peak (PW 10 ms)

BaseCurrent continuous
ICM
IB
50
8
Apk
Adc


Operating and Storage Junction TJ, Tstg 65 to 200 C
Temperature Range


1.0
0.8
DERATING FACTOR
0.6
0.4
0.2
0 40 80 120 160 200

TC, TEMPERATURE (C)

May, 2001 Rev. 9 BUV21/D
BUV21




(IC = 200 mA, IB = 0, L = 25 mH)

Collector Cutoff Current at Reverse Bias: ICEX mAdc

(VCE = 250 V, VBE = 1.5 V) 3.0
(VCE = 250 V, VBE = 1.5 V, TC = 125C) 12.0
(VCE = 160 V)

CollectorEmitter Cutoff Current

ICEO 3.0 mAdc

EmitterBase Reverse Voltage VEBO 7 V

(IE = 50 mA)

EmitterCutoff Current IEBO 1.0 mAdc
(VEB = 5 V)
SECOND BREAKDOWN


(VCE = 20 V, t = 1 s) 12

(VCE = 140 V, t = 1 s) 0.15

ON CHARACTERISTICS1

DC Current Gain hFE
(IC = 12 A, VCE = 2 V) 20 60

(IC = 25 A, VCE = 4 V) 10

(IC = 12 A, IB = 1.2 A)
(IC = 25 A, IB = 3 A)


VCE(sat)
0.6
Vdc

1.5

(IC = 25 A, IB = 3 A)

Current Gain Bandwidth Product

(VCE = 15 V, IC = 2 A, f = 4 MHz)
fT 8.0 MHz
SWITCHING CHARACTERISTICS (Resistive Load)

Turn-on Time ton 1.0 s
(IC = 25 A
A, IB1 = IB2 = 3 A,
A

Storage Time ts 1.8
VCC = 100 V, RC = 4 )

Fall Time tf 0.4
1 Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
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308
BUV21

10
operation i.e., the transistor must not be subjected to greater
1
The data of Figure 2 is based on TC = 25C, TJ(pk) is
limitations do not derate the same as thermal limitations.
0.1
At high case temperatures, thermal limitations will reduce
1 10 100 200
2.0
50
IC/IB = 8 VCE = 5 V
1.6
40
V, VOLTAGE (V)
1.2
30
0.8 VBE
20
0.4
10
VCE
0
1 10 0
100 1 10
VCE = 100 V
IC/IB1 = 8
IB1 = IB2 VCC
3.0
2.0 10,000 F
t, TIME (s)
RC

1.0
tS IB2
0.4 IB1 RB VCC = 100 V

0.3 ton RC = 4
0.2 RB = 2.2
tF
RC RB: Non inductive resistances

0 5 10 15 20 25
Figure 5. Resistive Switching Performance Figure 6. Switching Times Test Circuit
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309
ON Semiconductor
BUV22
SWITCHMODE Series
NPN Silicon Power Transistor 40 AMPERES
NPN SILICON
. . . designed for high current, high speed, high power applications. POWER
High DC current gain: METAL TRANSISTOR
HFE min. = 20 at IC = 10 A 250 VOLTS
250 WATTS
Low VCE(sat): VCE(sat)
max. = 1.0 V at IC = 10 A
TF max. = 0.35 s at IC = 20 A
MAXIMUM RATINGS

Rating
Symbol
VCEO(sus)
Value
250
Unit
Vdc

CASE 197A05
CollectorBase Voltage VCBO 300 Vdc TO204AE

(TO3)

CollectorEmitter Voltage (VBE = 1.5 V) VCEX 300 Vdc

CollectorEmitter Voltage (RBE = 100 ) VCER 290 Vdc

CollectorCurrent Continuous IC 40 Adc
Peak (pw 10 ms) ICM 50 Apk

BaseCurrent continuous

IB
PD
8
250
Adc
Watts


Temperature Range

1.0
0.8
DERATING FACTOR
0.6
0.4
0.2
0 40 80 120 160 200

TC, TEMPERATURE (C)

March, 2001 Rev. 9 BUV22/D
BUV22




(IC = 200 mA, IB = 0, L = 25 mH)

Collector Cutoff Current at Reverse Bias ICEX mAdc

(VCE = 300 V, VBE = 1.5 V) 3.0
(VCE = 300 V, VBE = 1.5 V, TC = 125C) 12.0
(VCE = 200 V)

CollectorEmitter Cutoff Current

ICEO 3.0 mAdc

EmitterBase Reverse Voltage VEBO 7 V

(IE = 50 mA)

EmitterCutoff Current IEBO 1.0 mAdc
(VEB = 5 V)
SECOND BREAKDOWN


(VCE = 20 V, t = 1 s) 12

(VCE = 140 V, t = 1 s) 0.15

ON CHARACTERISTICS1

DC Current Gain hFE
(IC = 10 A, VCE = 4 V) 20 60

(IC = 20 A, VCE = 4 V) 10

(IC = 10 A, IB = 1 A)
(IC = 20 A, IB = 2.5 A)


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CMOS Logic Data

CMOS Logic Data

PUBLICATION ORDERING INFORMATION

PUBLICATION ORDERING INFORMATION

Chapter 2 Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 4 B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 5 CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 6 CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 7 CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Chapter 8 Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Chapter 9 Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Device Function Page

Pull 500* piece sample from lot following Group A

ADD 500 CYCLES

SCRAP SCRAP SCRAP

3.0 TEST CONDITIONS AND COMMENTS

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C

VIL = 1.5 V Vout = 0.5 V Vout

FIRST STAGE VIL = 1.5 V SECOND STAGE

Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specifications

PROPAGATION DELAY AND RISE TIME

Figure 2. Networks for Minimizing ESD and Reducing

POWER SUPPLIES the possibility of latchup related failures. This system

Figure 4. Secondary Breakdown Characteristics

Figure 5. Battery Backup Interface

INPUTS VDD = 5.0 Vdc

All inputs, while in the recommended operating range

Vout , OUTPUT VOLTAGE (V)

R2 7.5 pF For these reasons, all unused inputs should be connected

VDD VDD PCHANNEL NCHANNEL VSS

Figure 11. CMOS Wafer Cross Section

Figure 12. Latch Up Circuit Schematic

B-Suffix Series CMOS Gates

MC14081B Quad 2Input AND Gate

MC14082B Dual 4Input AND Gate

Semiconductor Components Industries, LLC, 2000 32 Publication Order Number:

MC14001B MC14011B MC14071B MC14081B

MC14025B MC14023B MC14073B MC14082B

IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

MC14071B MC14073B MC14081B MC14082B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

BSERIES GATE SWITCHING TIMES

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B, MC14071B MC14025B

MC14023B, MC14073B MC14011B, MC14081B

TYPICAL BSERIES GATE CHARACTERISTICS

NCHANNEL DRAIN CURRENT (SINK) PCHANNEL DRAIN CURRENT (SOURCE)

ID , DRAIN CURRENT (mA)

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = 5.0 Vdc

ID , DRAIN CURRENT (mA)

Figure 4. VGS = 10 Vdc Figure 5. VGS = 10 Vdc

ID , DRAIN CURRENT (mA)

Figure 6. VGS = 15 Vdc Figure 7. VGS = 15 Vdc

TYPICAL BSERIES GATE CHARACTERISTICS (contd)

VOLTAGE TRANSFER CHARACTERISTICS