Digital system Modeling-

Digital design methodologies

Design Domains

Levels of modeling

Department of Electrical & Electronics Engineering 2/16/2016

 Design Methodology
Most real designs are combinations of both
Top Down Approach Bottom up Approach
Concept:- Concept:-
Define top level block Identify available building blocks
Identify sub blocks Build bigger blocks(called
Divide sub block until leaf cell as Macrocells) using this till top
Leaf cell further cant be divided
level block
eg: 4 bit adder
Designer partitions the system
Designer partitions the system
based on sub module availability
based on objective criteria
-speed, power, area etc.
May not meet objective criteria
Design not by what is available

May produce non standard modules

May be more economical
Allows team work
Design Reuse possible
May increase cost Department of Electrical & Electronics Engineering 2/16/2016
 Design Methodologies
Verilog
HDL

3 2005
Design Domains

Specifies how a chip is manufactured

Specifies abstraction levels

Behavioral
Structural
Physical/Geometrical

Department of Electrical & Electronics Engineering 2/16/2016

Behavioral

What the system does?

Information on how it is achieved is hidden
i/ps, o/ps and its relation - defined
How the system respond to set of i/ps
Boolean equation, truth table, state diagram, algorithm,waveform etc.

Department of Electrical & Electronics Engineering 2/16/2016

Structural

What are the components?

Information on how the components are interconnected to
perform certain function
Schematic,Netlist,
What the design is?
No information on what the system does
Module level, gate level, switch level, circuit level

Department of Electrical & Electronics Engineering 2/16/2016

Physical

How the design is made

Placement & routing or manufacturing information
No information on which components, how they behave
PCB manufacture etching tracks
IC layout- mask layout, metal, diffusion
PLDs- define internal connections
Define how particular part has to be constructed

Department of Electrical & Electronics Engineering 2/16/2016

 Domains and Levels of Modeling
Gajskis Y chart Behavioral/Functional
Algorithm
Structural
Register-Transfer
Processor-
Language
Memory
Boolean Equation
Register-Transfer
Differential Equation
Gate Polygons

Transistor Sticks

Standard Cells

Floor Plan
Geometric Y-chart due to
Gajski & Kahn
VHDL Quick Start 1998, Peter J. Ashenden
 Behavioral Structural Geometrical
Algorithm:- Processor:- Chip floor plan:-
Set of operations to be Architecture of Mapping into chip surface
performed processor depends
Behavior of target chips on target chip
behavior

FSM/Register Transfer language:- Register/ALUs:- Standard cells/Module

How data will be moved and Structural placement:-
stored implementation Modules placed on to chip
surface using CAD tools Routing
optimization

Boolean equation:- Leaf cells/Gates:- Sticks /Cell placement:-

How individual signals are Structural Placed &interconnected
manipulated description
Individual modules

Differential equation:- Transistor :- Polygons:-

Boolean description Transistor level Mask generation
How currents and voltages in the implementation
transistors behave Department of Electrical & Electronics Engineering 2/16/2016
 DSDCA2016/ course material /EEE dept

HARDWARE DESCRIPTION
LANGUAGE
(HDL)
VHDL

Verilog HDL

Comparison

System C

Introduction to Verilog HDL

 HDL
Similar to computer program Advantages
Describes underlying
hardware Widely supported
Enables portability
Two main HDLs:- Text based
VHDL Modular Implementation possible
Sharing & Reuse
Verilog HDL

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HDL-origin
1980s: VHSIC program
Emergence of HDLs
The need to standardized language for hardware
description
Design at RTL

Dramatic change in digital design

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What is HDL
Textual description of the circuit
Easier to understand
Functional verification
Describe a system
Human & machine readable
System can be described from many different form
Behavior
Structure
Physical properties
Used to describe hardware for the purpose of specification ,
synthesis, verification & documentation
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Trends in HDLs
Design at behavioral level
Formal verification techniques
Very high speed & time critical circuits
mixed - gate level & RTL design

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HDL Language constructs
Must be able to design component types
Model may be behavioral/structural
Must be able to define data types
Wire may carry enumerated value
Must be able to define modules

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Verilog HDL
1983
Gateway design automation company
Simulation environment
Comprising various levels of abstraction
Switch(transistors),gate, register transfer & higher levels
Extend& customize simulation environment
General Purpose
Easy to learn, easy to use, fast simulation similar to syntax C
Allows different levels of abstraction & mixing them supported by most
popular logic synthesis tools

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VHDL
More general language
1980-USA department of defense
Used for describing digital electronic systems
Used for specifying , simulating, & implementing digital designs
Primarily describing parallel structure
Harder to learn &use

DSDCA2016/ course material /EEE dept

 Comparison b/n VHDL & Verilog
HDL
VHDL Verilog HDL
Modeling Considered at the system level Better when describing a system at the
capability gate level/transistor level
Compilation Multiple design units may be Order of compilation crucial
separately compiled
Data types User defined data types No user defined data types, simple data
types provided by language
Strongly typed language
cannot mix datatype
Design packages/ libraries present No concept of package
Reusability
High level More in VHDL Better suited for low level modeling
constructs
Harder to learn & use Easy to learn & use
Case insensitive Case sensitive
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(Verilog keywords- lower case)
Verilog HDL/VHDL

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Verilog HDL/VHDL

Market divided b/n VHDL & Verilog

Concurrent hardware description Language

Design Reusability

DSDCA2016/ course material /EEE dept

System C
C++ library
Used for supporting system level modeling
Modeling concurrent systems
Can be considered as HDL
Supports various abstraction level
Used for fast efficient design & verification
Defines data types like bit ,vectors
Enables hardware- software co-design environment
Provide timing & event driven simulation

DSDCA2016/ course material /EEE dept