Us03-101 840 01 02 02

Antares
US
Troubleshooting Tools
System
System Troubleshooting
10032747
10032746
08653771
05936518
Siemens AG 2003
The reproduction, transmission or use
of this document or its contents is not
permitted without express written
Siemens Medical
Ultrasound
ejt DivisionSolutions
authority. Offenders will be liable for
damages. All rights, including rights
created by patent grant or registration
of a utility model or design, are
reserved.
Print No.: US03-101.840.01.02.02 English

Replaces: US03-101.840.01.01.02 Doc. Gen. Date: 10.05
n.a.
Part No.:
sd
2 Revision / Disclaimer
1Revision / Disclaimer
Copyright
Copyright 2004 by Siemens Corporation. All rights reserved. No part of this publication
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to this manual.Although Siemens Corporation has attempted to ensure accuracy through-
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Trademarks
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Adara, Antares, G20, G40, G50, G60S, Omnia and KinetDx are trademarks of Siemens
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Disclaimer
The service of equipment described herein is to be performed by qualified personnel who
are employed by Siemens or one of its affiliates or who are otherwise authorized by Sie-
mens or one of its affiliates to provide such services.
Assemblers and other persons who are not employed by or otherwise directly affiliated
with or authorized by Siemens or one of its affiliates are directed to contact one of the
local offices of Siemens or one of its affiliates before attempting installation or service pro-
cedures.
License Agreement
All computer programs copyright 1990-2004 by Siemens Corporation or its suppliers. Pro-
grams are licensed under the following agreement:
Siemens or its suppliers retain(s) ownership of and title to any computer program supplied
with the equipment and to the trade secrets embodied in such computer programs. Sub-
ject to the Buyers acceptance and fulfillment of the obligations in this paragraph, Siemens
grants the Buyer a personal, non-transferable, perpetual, non-exclusive license to use any
computer program supplied with the Equipment that is necessary to operate the Equip-
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Antares US03-101.840.01.02.02 Page 2 of 106 Siemens

10.05 sd Medical Solutions USA, Inc.
Revision / Disclaimer 3
of this license, the license granted by this paragraph shall terminate. Further, because
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Siemens US03-101.840.01.02.02 Page 3 of 106 Antares

Medical Solutions USA, Inc. 10.05 sd
4 Table of Contents
1- 0Table of Contents
1 _______ Troubleshooting Guide ___________________________________________ 6
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Acronyms and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Basic Troubleshooting steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Rules for Interchanging Boards/Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Troubleshooting Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Using the Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC/DC Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Tray LED Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Tray LED Fault Indication tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Troubleshooting the E Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
E Module Troubleshooting Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Troubleshooting Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Troubleshooting basic imaging problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Appendix A: Test Results and Test Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Appendix B: How to Access ImagingBE and Firmware Logs . . . . . . . . . . . . . . . . . . . . . 55
What to look for in a ImagingBElog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix C: Examples of ImagingBE and Firmware Logs . . . . . . . . . . . . . . . . . . . . . . . 56
Imaging Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Firmware (FW) Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendix D: How to Boot in Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendix E: Test Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Front-end Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Control Dac Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Back-end Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Video Interface Segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Control Panel Tests - CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
System Level Tests - RC, BE, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix F: Board Tests and Related Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Diagnostic Test Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Transmit test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Receive Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Zm System B-Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Zm System BC-Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
RTC Sequence Test (RC sequence, TR0 sequence, TR1 sequence, TR2 sequence)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
FE memory (includes RC memory, TR0 memory, TR1 memory, TR2 memory). . . 101
DC cal/DC cal check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Probe Relay test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
BE memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table of Contents 5
VI memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Control DAC test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A2D Diag Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6 Troubleshooting Guide
2-
Purpose
1Troubleshooting Guide
The purpose of this section is to identify the root cause of the error with the Antares sys-
tem.
Begin with the (Troubleshooting Flowchart / p. 11). It guides the user through a series of
functional tests and diagnostic suggestions.
If the answer is Troubleshoot E Module, refer to the (E Module Troubleshooting
Process / p. 36). Use this section and the service manual to further troubleshoot other
system faults.
NOTICE When an E Module board is replaced, an E Module test must be

performed.
When the troubleshooting is finished, the system will
prompt the user to execute a module test on every reboot
until the E Module test has been executed.
Acronyms and Terms 0
Acronym/Term Definition
AC AC tray; also referred to as PSAC Tray
aperture number of active transducer elements, or transducer width, dur-
ing transmit or receive
apodization amplitude weighting function applied across the active trans-
ducer aperture
beamformer electronics responsible for combining signals (receive or trans-
mit) from each transducer element into a single acoustic vector
axial direction along the acoustic vector
B-mode two dimensional brightness mode display
BC-mode B-mode with a color flow ROI
BE backend or Backend Board
BP Backplane
BP-mode B-mode with power mode ROI
CB CW Beamformer Board
CLA transducer curved linear array transducer
CP Control Panel

Troubleshooting Guide 7
CW or CW Doppler continuous wave Doppler
DGC depth gain compensation (same as TGC)
ECG electrocardiogram
EM E Module
ensemble set of color flow vectors from a single direction used to estimate
flow
FE frontend
FOV field-of-view
FP Front Panel
HDD Hard Disk Drive
HW hardware
HW/HW IDD specifies signal characteristics of hardware-to-hardware inter-
faces
IO Input/Output Board
IP Image Processor Board
LA transducer linear array transducer
M-mode Motion Mode
PA transducer phased array transducer: element spacing is no greater than
half-wavelength
PY Physio Module
PS power supply
PSAC Power Supply AC tray; also referred to as AC Tray
PW or PW Doppler pulsed wave Doppler
RC Receive Beamformer and Controller Board
RM CPU Real-time Manager
ROI region-of-interest
TEE transesophageal transducer
TGC time gain compensation
THI Tissue harmonic Imaging
TI transducer interface, Transducer Interface Board

TR Transmit/Receive Board
RTC Real Time Controller
VI Video Input/Output

Basic Troubleshooting steps 0
1. Power up the system and ensure that the system boots to imaging mode with a func-
tional ultrasound image.
2. If the system does not boot to imaging, refer to the (Boot Sequence / p. 38) to deter-
mine possible defective EM boards.
3. If the service test tools are available, execute EM, PS and TI diagnostics.
4. If diagnostics fail, refer to (Appendix E: Test Descriptions / p. 61) and (Tab. 16 / p. 44) to
identify probable E Module board failures.
- If the diagnostic failure and the probable E Module board failure are related, then de-
termine which board needs to be replaced.
- If the two are not related, two boards may need to replaced; one to fix the diagnostic
problem and the other to fix the boot problem. Refer to the (Tab. 17 / p. 47) to resolve
the failure.
Rules for Interchanging Boards/Modules 0
NOTICE The system license information will be corrupted if multiple

boards/modules are replaced/interchanged at the same time.
A corrupt license file will result in the loss of optional features and
system imaging functionality.
To minimize this risk, only replace one board or module
at a time and perform a system reboot each time.
To prevent the loss of system license information, replace only one board or one FRU at a
time and reboot after each task.
The applications license.dat file is maintained in four locations in the system:
RM board
TI board
Control Panel
Hard Drive
On each reboot, the license.dat file is pulled from each location and the stored licenses
are compared.
If there is any disagreement within the individual license file locations, the software will
use the license.dat information that receives the most matches from within these loca-
tions. If no two license.dat files match, the license.dat file becomes corrupted and must be
reloaded.

NOTE Interchanging two TR boards in the E Module for image testing or

other purposes will not corrupt the license.dat file or the system
serial number.
System Serial Number

The system serial number of the Antares system is stored and maintained on a series of
boards within the E Module.
TR0
TR1
TR2
RC
BE
VI
RM
CB (for future use)
The system serial number is determined by comparing the files stored on each reboot. A
serial number will be assigned if a majority of the compared files match.
If there is no majority from the files contained on the E Module boards, a secondary com-
parison will be performed from files stored on the TI Module, the Control Panel and the
Hard Drive.
If there is still no majority, the system will force the serial number to 99999 and will create
a license file for each board using the 99999 number.
If the system serial number is forced to 99999, escalate the problem to the Headquarters
Support Center (HSC) as soon as possible.

Troubleshooting Flowchart 0
The system troubleshooting flowchart is designed as a closed loop. The main flowchart
branches to secondary flowcharts, each of which returns to the main flowchart for contin-
ued troubleshooting. With this method, fault conditions involving more than one error may
be resolved. The flowchart is not intended to resolve all possible fault conditions; it is
designed to resolve 80 percent of typical field situations.
Using the Flowchart 0
Always start at the top and check each item in the CHECK column, which provides details
for each CHECK item. Any place on the flowchart which has an active link will be noted
with bold green text.As an example, a system does not boot correctly.Do not go directly to
the BOOTUP flowchart. First confirm power by checking the LEDs on the PSAC and I/O
modules. If these are all OK, and the monitor LED is on, proceed to the BOOTUP flow-
chart by clicking on the E, which will link to the section of the flowchart which deals spe-
cifically with BOOTUP troubleshooting. Follow the BOOTUP flowchart, then clicking the
F, which will follow the flowchart pattern back to the main flowchart. Confirm the remain-
ing items in the flowchart to complete use of the troubleshooting flowchart.

Fig. 1:

Fig. 2:
Fig. 3:

Fig. 4:

Fig. 5:

Fig. 6: P10 Connector into J10 Connection

Fig. 7:

Fig. 8:

Fig. 9:

Fig. 10:

Fig. 11:

Fig. 12:
Fig. 13:

Power Test Points 0
Tab. 1 PSAC Power Test Points
FRU TP Description Comment

PSAC 1 48V output Tolerance: 47V +/- 1V
See 6 Fan voltage (TP6 is only on PSAC units before M/N Tolerance: 45V +/- 1V
(Fig. 14 74 78 212.)
/ p. 23)
2 48V return
3 Signal ground
5 ACRMVRS (Power for LAN and start-up circuitry.) Tolerance: 5.0V +/- 0.2V
4 ACRMMSV (Standby power to keep DRAM alive.) Tolerance: 5.0V +/- 0.2V
Fig. 14: AC Tray (PSAC) Test Points and Transformer Fuses

Pos. 1 Test Point 1
Pos. 2 Test Point 2
Pos. 3 Test Point 3
Pos. 4 Test Point 4
Pos. 5 Test Point 5
Pos. 6 Transformeer Fuse F1
Pos. 7 Transformer Fuse F2

Tab. 2 PSA Power Test Points

PSA1 1 VTX0 (TP at top) 0 - 18.5V (C-, P-, D-mode)
See 2 P14AQ +14.2V +/- 5%
(Fig. 15
/ p. 25) 3 P5AQ +5.0V +/- 5%
4 EBN -3V +/- 5%
5 M9.6A -9.6V +/- 5%
6 M2.0AQ -2.2V +/- 5%
7 M100HV +7.5V +/- 5%
8 M14AQ -14.2V +/- 5%
9 VTX1 0 - 18.5V (B-, M-mode)
10 P7A 7.0V +/- 5%
11 P3.3A +3.3V +/- 5%
12 P5A +5.0V +/- 5%
13 P3.3AQ +3.45V +/- 5%
14 P100HV +3.87V +/- 5%
15 Ground (TP at bottom)
1. PSA test points are not labeled. Test point Number 1 is at the top.
Tab. 3 PSD Power Test Points

PSD1 1 Ground (TP at top)
See 2 M12D -12V +/-5%
(Fig. 15
/ p. 25) 3 P12D +12V +/-5%
4 P5D +5.1 +/-5%
5 P3.3D +3.4V +/-5%
6 P2.5D (TP at bottom) +2.575 +/-5%
1. PSD test points are not labeled. Test point Number 1 is at the top.

Fig. 15: PSA and PSD test points

Pos. PSD 1 PSD Test Point 1 (top)
Pos. PSD 6 PSD TEst Point 6 (bottom)
Pos. PSA 1 PSA Test Point 1 (top)
Pos. PSA 14PSA Test Point 14
Pos. PSA 15PSA Test Point 15 - ground (bottom)

Tab. 4 I/O Board Test Points

I/O 1 Ground
Module
2 +3.3VF (Control Panel) I/O LED 7
See
(Fig. 16 3 +5VF (Control Panel & Front Connector Panel) I/O LED 8
/ p. 26)
4 +12VF (Control Panel) I/O LED 9
5 +12V DP (HDD) I/O LED 4
6 +5V DP (HDD) I/O LED 3
7 +5V RDD I/O LED 5
8 +12V RDD I/O LED 6
9 +5V MIC
12 P2-5D Not used
16 -12V I/O Module only
Fig. 16: I/O Board Test Points
NOTE The I/O Board test points are located behind the hard disk drive as-
sembly.

Tab. 5 I/O Module LEDs
FRU LEDs Description

I/O Module 1 RM boot status
LEDs
2 HDD disk access
See
(Fig. 17 / p. 27) 3 +5V HDD
4 +12V HDD
5 +5V RDD
6 +12V RDD
7 +3.3VF Control Panel
8 +5VF Control Panel & Front Connector Panel
9 +12VF Control Panel
When attempting to use the I/O Module LEDs to diagnose a problem, note that LED 1 will
be yellow during BIOS load and initialization of the system. It will change to solid green
when Windows starts loading.
LED 2 will flash yellow when any activity occurs on the hard drive.
LEDs 3-9 should be solid green, indicating voltages are present in the associated test
points.
Fig. 17: I/O Module LEDs

Tab. 6 Control Panel LEDs
FRU LED Description

Control Panel 1 Keyboard USB connection
See 2 Control Panel USB connection
(Fig. 18 / p. 28)
3 Not Used
4 Not Used
LEDs 1 and 2 will be flashing under normal operation.
Fig. 18: Control Panel LEDs
AC/DC Power Connections 0
Tab. 7 AC/DC Power Connections
FRU Connector Pin Signal

AC transformer J50/P50 2 115/230 VAC
primary
3 100 VAC
4 0 VAC
6 115/230 VAC
7 0 VAC
8 0 VAC
AC transformer J49/P49 1 48V PS AC MAIN N

secondary
2 48V PS AC MAIN H

Isolation trans- J41 Monitor AC fused at F1 1 216 VAC, not switched

former
2 216 VAC, not switched
3 Safety ground to monitor and system chas-
sis
4 Shelled drain to chassis
J35 OEM AC fused at F2 115/230V selectable AC outlet
PSA Power J36/P36 A1 48V_PSA

A2 48V_PSA_RET
PSD Power J37/P37 A1 48V_PSD

A2 48V_PSD_RET
PS Fans J32/P32, J92/P92 1 PFANS1

2 PFANS1 TACH
3 PFANS1 RET
5 PFANS2
6 PFANS2 TACH
7 PFANS2 RET


Main Fans J31/P31, J91/P91 1 FANS1
2 FANS1 TACH
3 FANS1 RET
4 FANS2
5 FANS2 TACH
6 FANS3 RET
7 FANS3
8 FANS2 TACH
9 FANS3 RET
Battery P39 2 +4.8V (Red)

3 +4.8V RET (Black)
Monitor AC J41/P41, J63/P63 1 Hot (Brown)

2 Neutral (Blue)
3 Safety ground (Grn/Yel)
4 Shield ground
CP J52/P52 1 +5V
2 +5V RET
7 +12V
8 +12V RET
Front Connector J11A/P11A, J67/P67 1-5 +12V RDD

Panel
6-10 +5V RDD
13-15 +5V Fused
33, 34 Mic Power
35-39 +12V RDD RET
40-44 +5V RDD RET

HDD J13/P13, J130/P130 1 +12V

2 +12V RET
3 +5V RET
4 +5V
RDD P72 1 +12V

2 +5V
3 +12V RET
4 +5V RET
J133/P133, J135/P135 1 +12V
2 +12V RET
3 +5V RET
4 +5V
Physio module J12A/P12A, J76/P76 2 +12V RET

8 +12V DC

AC Tray LED Faults 0
Many system faults can be detected by viewing the AC Tray LED array located near the
circuit breaker on the rear of the Antares system. See (Fig. 19 / p. 32). The group of tables
located in (AC Tray LED Fault Indication tables / p. 32)will explain the AC Tray LED array
and what each fault indication pattern means.
Fig. 19: LED Fault indication panel
AC Tray LED Fault Indication tables 0
Tab. 8 AC Tray LED Description
LED Array LED Meaning LED Legend

1. PSA status
2. PSD status
3. 48V status
4. Main fans status
5. Power Supply fans status
6. AC Tray fans status
Battery Status
AC power status
In each of the next four sections, the Dont Care LED indicator means that the LED is not
relevant for the condition being described. The relevant error section should be used to
determine the meaning of the other LEDs. LED 1, 2 and 3 are described in the (Power
Supply Status / p. 34) section. LED 4, 5, and 6 are described in the (AC Tray Fan LED

Status / p. 35) section. The (Battery Status / p. 33) and (AC LED Status / p. 33) are
described in individual sections. Any condition that causes a yellow LED to illuminate will
cause the system to shutdown.
AC LED Status
Tab. 9 AC LED Status
LED Pattern Condition Description

No AC Power AC Power is not available. This could be
caused by the absence of wall power, the
cord, the AC tray circuit breaker being open,
the AC tray or the isolation transformer.
AC power available AC Power is available. This is a normal con-
dition
Battery Status
Tab. 10 Battery Status

No Battery, or battery If the battery is present and correctly con-
malfunction nected, this condition indicates that a fault
has been detected in the battery pack by the
charger. Otherwise this a normal condition.
The battery is charging This condition indicates the battery is in a
discharge/charge cycle.
The battery is charged A full or partially charged battery is installed

in the system.

Power Supply Status

Tab. 11 Power Supply Status

Standby The power supply is in standby mode, wait-
ing for a power up command.
48V supply started This condition lasts for 1.2 seconds during
power up. It indicates the 48V power supply
successfully started. If this condition is not
exited in 5 seconds a fault condition will be
displayed
PSD started This condition lasts for less than 1 second
during power up. It follows It indicates the
48V power supply successfully started. If
this condition is not exited in 5 seconds a
fault condition will be displayed
AC Tray running This is the normal state of the AC Tray when
the system is running
48V Internal Fault The AC Tray 48V power supply has

reported an error. This includes undervolt-
age, overvoltage or over temperature. If
condition continues replace the AC Tray
PSD Internal Fault The PSD has reported an internal error.
This includes undervoltage, overvoltage or
over temperature. If condition continues
replace the PSD
PSA Internal Fault The PSA has reported an internal error. This
includes undervoltage, overvoltage or over
temperature. If condition continues replace
the PSA
PSD 48V Overload The PSD is overloading the 48V power sup-
ply. If condition continues, replace the PSD
PSA 48V Overload The PSA is overloading the 48V power sup-
ply. If condition continues, replace the PSA
PSD Overload One of the PSD outputs is overloaded. This

can be caused by the EM, IO, TI, CP, UFP,
RMM, or HDD.


PSA Overload One of the PSA outputs is overloaded. This
can be caused by the EM, IO, TI, CP, UFP,
RMM, or HDD.
BE board not installed An EM overheat sensor has not been imple-
in EM (Formerly System mented. The Active high line is currently
Overheat) grounded on the BE board. If the BE board
is removed from the EM card cage, the AC
tray will not allow the system to power on
and will display this LED pattern.
AC Tray Fan LED Status

Tab. 12 Fan LED Status

Fans Running All fans are running normally
AC Tray Fans Stopped The fan in the AC Tray has stopped. If this
condition continues replace the AC Tray
Power Supply fans One or more of the power supply fans is

stopped slow or stopped. If this condition continues
replace the power supply fan assembly
Main fans stopped One or more of the main fans is slow or
stopped. If this condition continues replace
the main fan assembly

Troubleshooting the E Module 0
Using this section assumes that troubleshooting has already been completed at the mod-
ule level and the problem has been isolated to the E Module.
E Module Troubleshooting Process 0
Troubleshooting the Antares Ultrasound E Module consists of observing symptoms and

test data, identifying the likely cause, replacing potentially defective boards, and verifying
that the module and system have been repaired.
Tab. 13 Stages of E Module Troubleshooting
Stage Description
1 The CSE collects and analyzes imaging and other performance symptoms. These
will generally be reported by the customer, and later verified by the CSE at the site.
2 The E Module service test tools are used to provide additional information about E
Module performance. Using the combination of performance symptoms and test
data, the CSE assesses board defect possibilities, and determines a cost effective
strategy for ordering replacement boards.
3 The CSE accesses the E Module and makes one or more board replacements. Per-
formance symptoms and diagnostic tests are rechecked to confirm effectiveness of
the changes.
4 The CSE conducts a comprehensive set of imaging tests to verify that the system is
operating correctly.
Troubleshooting Flowcharts 0
NOTE Always disconnect the quickstart backup battery, if installed, be-

fore troubleshooting.

Fig. 20: Troubleshooting Process Flowchart
Boot Sequence 0
(Tab. 14 / p. 38) shows the boot sequence for the Antares system software Rev 2.1 and
3.0 and potential problems that may occur during the sequence.
The table has four columns. The first column, Boot sequence progress, indicates the
approximate stage of the boot sequence.
The second column, Corresponding Expected Behavior/Indications, indicates what
should be happening in each stage of the sequence.
In the event that a condition described in the second column does not happen, refer to the
third column, Possible Causes of Unexpected Behavior, to determine a potential expla-
nation for why the behavior did not occur.
The fourth column, Further evaluation, provides suggestions to follow which may help
identify the defective E Module board.
Tab. 14 Boot Sequence troubleshooting chart
Boot Corresponding Possible Causes of Unex- Further evaluation

sequence Expected Behav- pected Behavior
progress ior/Indications
Standby Mode LEDs on UFP and AC PS supply (see
monitor turn amber (Tab. 9 / p. 33))
AC PS cooling fan
turns on (Note: Only
for ACPS without
Handles around the
breaker)
Powering Up LEDs on AC PS Fault condition detected by
(user initiated) turn on AC PS (see (Tab. 9 / p. 33))
LED on UFP turns BE board in EM is discon-
green nected from backplane
EM cooling fans System stops after 2 to 3 To distinguish between BE
turn on seconds. and VI; disconnect VI from
RM in reset condition (BIOS backplane and power on sys-
err LED on RM on; all others tem; if RM reset condition
off. See (Fig. 21 / p. 39)) due goes away VI is likely cause.
to BE, VI or RM board prob- Note: The BE cannot be dis-
lem connected in a similar man-
ner, since removing the BE
will indicate to the AC PS that
a overtemp fault occurred
Control Panel Control Panel emits Control Panel fault
Executing Self beep
test


Video initializ- LED on monitor Incorrect video signal or If it is the VI, the RM may
ing turns green missing sync continue with the boot pro-
cess as indicated by RM
POST LED #1 on IO and
accesses to Hard Drive LED
#2 on IO
RM BIOS starts Antares splash RM or VI if screen is blank
executing screen is displayed
POST
RM BIOS fin- System emits RM if splash screen remains Reseat RM
ished execut- beep on screen and LEDs do not
ing POST RM Boot OK change appropriately
LED is on
LED #1 on IO
changes from
amber to green
Fig. 21: RM Board LEDs

Pos. 1 Power LED
Pos. 2 Boot OK LED
Pos. 3 BIOS ERR LED
Pos. 4 IDE ACT LED
Pos. 5 SCSI ACT LED


Windows load- For 2.1.032 stan- RM or HDD
ing dard windows
screen sequence
prior to Syngo count
For 3.0.094A splash
screen remains on
screen after RM
POST is completed
until Syngo count
starts
Antares Syngo System emits three The three clicks indicate a Check error messages and
test tools avail- clicks system reset initiated by the ImagingBE.log, Imag-
able system after the RM was ingBE.1.log and Imag-
able to communicate with all ingBE.2.log in C:/Syngo/log
EM boards and the TI mod- directory. See (Appendix B:
ule. The absence of three How to Access ImagingBE
clicks could be indicative of and Firmware Logs / p. 55)
problem with any of these and (Appendix C: Examples
boards: of ImagingBE and Firmware
RM, VI, BE, RC, TR0, TR1, Logs / p. 56) for help on how
TR2, TI to access the logs. Use
Escape to OS and
Explorer.exe; Windows safe
mode; or log extract utility to
access these log files


Syngo loading, Syngo count and Defective: Check error messages and
Hardware and imaging screens RM, VI, BE, RC, TR0, TR1, ImagingBE.log, Imag-
Firmware con- appear. TR2, TI ingBE.1.log and Imag-
figuration check ingBE.2.log in C:/Syngo/log
and Imaging directory and call UPTIME
application service center (USC). Use
loading. If a Escape to OS and
firmware mis- Explorer.exe; Windows safe
match is mode; or log extract utility to
detected, then access these log files
a firmware load
will occur fol- Firmware load problems. If LED on RC board is off,
lowed by a Firmware load failures usu- then RTC device has firm-
shutdown. ally can be traced to the ware problems.
board where the firmware Check error messages and
load is failing. (Refer to fwlog.txt C:/Syngo/log direc-
(Tab. 18 / p. 50)) tory to identify failing compo-
The circuit that controls data nent and board location. See
transfer for firmware loading (Appendix C: Examples of
is on the BE board, so the ImagingBE and Firmware
BE board is capable of caus- Logs / p. 56) and (Appendix
ing firmware load problems D: How to Boot in Safe
on other boards. Mode / p. 59)
Run a board test to identify
defective boards if the tests
are available.
Fig. 22: RC Board LED


System Ready
for Imaging
(Tab. 15 / p. 42) will show many of the common problems that occur during boot up and
the potential causes.
Tab. 15 Boot Problems
Symptom Cause
Press Power On and system exhibits no response AC tray is responding to a fault by not allow-
ing system to boot
Press Power On and system starts to respond but RM is in reset
stops after 2 to 3 seconds; RM BIOS error indicator is
on; monitor led is green VI is keeping RM in reset by not releasing
ACRM-PSS line
BE is keeping RM in reset by not releasing
ACRM-PSS line
Blank screen, monitor led is amber, RM proceeds VI board problem
through the standard POST process
System proceeds through boot up process, syngo BE PCI bridge is not functional
counts from 1 through 99, standard overlay informa-
tion from RM is present on the screen; but no ultra-
sound information is displayed. ImagingBE.log file
indicates BE driver install failure. Only shutdown or
cancel options are displayed when turning off sys-
tem, instead of the normal standby, shutdown, or
cancel
blank screen RM problem
LED #1 on I/O Board does not change from amber to
green
Hangs on a Windows Bar (Rev 2.1.032)
Hangs after I/O Board LED #1 transition to green but
before Syngo count starts (Rev 3.0)
Monitor LED does not change to green
Video problem early in the boot or with the overlay
information

Symptom Cause
Error message on screen or ImagingBE.log indicates RM is cause of error message
error
BE is cause of error message
See (Appendix C: Examples of ImagingBE and Firm-
ware Logs / p. 56)and (Appendix D: How to Boot in TR is cause of error message
Safe Mode / p. 59) for more details.
RC is cause of error message
TI is cause of error message
System shuts down during boot up PSA or PSD Fault is detected by AC tray.
See (Tab. 9 / p. 33)
No operating system found error message IO module/EM connection problem
HDD problem
Troubleshooting basic imaging problems 0
The following troubleshooting table will show a number of potential problems and the test
that may help determine the problem. Always use the test tools for further troubleshooting.

Tab. 16 Board vs. Image problem
Board Image Problem Test Troubleshooting Suggestion

TR In general TR board image Refer to Antares (Channel
problems will be related to a Map / p. 51)and then interchange TR
single channel, a group of 8 boards. A TR-related imaging fault will
channels, or a group of 64 move with the associated TR as indicated
channels. Refer to the by the channel map.
(Channel Map / p. 51) for how
TR channels map to the
image.
A single channel or multiple Transmit Test Moving the focal point closer to the skin-
channel transmit failure will line will make transmit failures easier to
create a dead/dark area identify. This reduces the number of
associated with the channels. transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.
A THI transmit failure can cre- Transmit Test Moving the focal point closer to the skin-
ate lighter or dark lines in the line will make transmit failures easier to
image identify. This reduces the number of
transmit channels fired at the same time.
boards.
A single channel receive fail- Moving the focal point closer to the skin-
ure typically creates an arti- line will make transmit failures easier to
fact that is shaped like an arc identify. This reduces the number of
in normal or THI imaging transmit channels fired at the same time.
mode Using Cine playback can make a bad
boards.


RC Large dropouts in image RC memory Interchange TR boards. If the drop-
associated with an defective Receive test out/artifact stays in the same position, the
RXBF (16-channel grouping) RC board is most likely the problem.
B mode
If the dropout/artifact changes position,
BC mode the TR board is most likely the problem.
Large areas of color noise in RC memory
image associated with an Receive test
defective RXBF (16 channel
grouping) B mode
BC mode
Vertical lines in image RC memory
Receive test
B mode
BC mode
Color/Power outside vessels Check top marking on U78 and U79 (near
or on bright areas of B image, connector P508- See (Fig. 23 / p. 47)), if
can be intermittent due signif- marked with KLT23 then this failure mode
icant tendency on tempera- is possible and RC board should be
ture replaced, if marked with XEL23 then this
failure mode is not possible. Note: Not all
KLT23 parts are defective, so only
replace RC boards that have these parts
and a history of the problem.
Poor image resolution due to
defective main clock oscillator
Bands in image
Color noise on skinline A2D Diag RCFEREF voltage bad
Grid artifact in far field


BE Entire image has problems B mode
BC mode
Image problems that seem to BE memory
be digital - hard horizontal or B mode
vertical boundaries; blocks of
colors; etc. BC mode
Radial line color noise B mode

BC mode
Doppler problems BE memory
M-mode problems BE memory
Cine problems BE memory
BE/VI Audio problem UFP can also cause no audio
VI no image
Color noise
Incorrect color (I.e, red
image)
Vertical lines in image
Doppler Auto stats overlay
problem
RM Image overlay problems
System locks up
Image break up- Large sec-
tions of image shifted or out
of place
3D problems
4D problems Run the TI test and all 4D transducer
tests to ensure the TI board and all the
transducers are OK.
VI/BE/R Error Message Refer to log files in C:/Syngo/log direc-
C/TR tory. Files such as ImagingBE.log and
ImagingCrashDataWdyMthDDHHMMSS
Year0.txt

Fig. 23: Drawing of RC Board Area

Pos. 1 U78
Pos. 2 U79
Tab. 17 Image Problems and associated board fault
Image Problem Test Board Troubleshooting Suggestion

Problems in 8-channel TR Refer to Antares (Channel
segments Map / p. 51)and then interchange TR
boards. A TR-related imaging fault will
move with the associated TR as indi-
cated by the channel map.
3D problems RM
4D problems RM This assumes the transducer and TI
module are functioning properly


Problems in 64-channel TR Refer to Antares (Channel
segments Map / p. 51)and then interchange TR
Arc-shaped artifact in TR Refer to Antares (Channel
normal or THI imaging Map / p. 51)and then interchange TR
mode boards. A TR-related imaging fault will
Audio problem BE, VI UFP can also cause no audio
Bands in image RC
Cine problems BE memory BE
Color noise VI
Color noise on skinline A2D Diag RC RCFEREF voltage bad
Color/Power outside RC Check top marking on U78 and U79
vessels or on bright (near connector P508), if marked with
areas of B image, can KLT23 then this failure mode is possible
be intermittent due sig- and RC board should be replaced, if
nificant tendency on marked with XEL23 then this failure
temperature mode is not possible. Note: Not all
KLT23 parts are defective, so only
replace RC board that have these parts
and a history of the problem.
Dead/dark area associ- Transmit test TR Moving the focal point closer to the skin-
ated with the channels line will make transmit failures easier to
identify. This reduces the number of
channel easier to identify. Refer to
Antares (Channel Map / p. 51)and then
interchange TR boards. A TR-related
imaging fault will move with the associ-
ated TR as indicated by the channel
map.
Doppler Auto stats over- VI
lay problem
Doppler problems BE memory BE


Entire image has prob- B mode, BC mode BE
lems tests
Error message TR, RC, Refer to log files in C:/Syngo/log direc-
BE, VI tory. Files such as ImagingBE.log and
ImagingCrashDataWdyMthDDHHMMSS
Year0.txt.
Grid artifact in far field RC
Image break up RM
Image overlay problems RM
Incorrect color VI
Large areas of color RC memory, RC
noise in image (16 receive test, B
channel grouping) mode, BC mode
Large dropouts in image RC memory, RC
(16 channel grouping) receive test, B
mode, BC mode
Light or dark lines in the TR Moving the focal point closer to the skin-
image line will make transmit failures easier to
identify. This reduces the number of
channel easier to identify. Refer to
Antares (Channel Map / p. 51)and then
interchange TR boards. A TR-related
imaging fault will move with the associ-
ated TR as indicated by the channel
map.
M-mode problems BE memory BE
No image VI
Poor image resolution RC
Problems with digital BE memory, b BE
imaging mode, BC mode
tests
Radial line color noise B mode, BC mode BE
tests


Single channel prob- TR Refer to Antares (Channel
lems Map / p. 51)and then interchange TR
System locks up RM
Vertical lines in image RC memory, RC, VI
receive test, B
mode, BC mode
Firmware failures
Firmware failures are logged in the fwlog.txt file located in the C:/syngo/log directory.
Always start at the end of the file to review the most current firmware information.
For firmware failures, the board where the failing device is located is the probable cause.
The board controlling the programming operation is the next probable - but less likely -
cause.
A firmware load/upgrade normally takes place if a new board, module or 4D transducer is
recognized. Firmware may also be upgraded as part of a software patch or combine code
load. For details on how to access a FW log, see (Appendix C: Examples of ImagingBE
and Firmware Logs / p. 56) and (Appendix D: How to Boot in Safe Mode / p. 59).
Tab. 18 Firmware Failures
Board Device Board which controls

programming
BE SIP DSP RM and BE
SIP BE
FPA BE
FPB BE
PCI BE
VI DEC BE
ENC
ACLK
VCLK
RC RTC BE
TR TR BE

Board Device Board which controls

programming
TI TI BE
RM Program BIOS RM
Channel Map 0
The following figures show the Antares Channel map, from left to right. The map is broken
down into segments for ease of use.
Image channels from left to right refers to the channels displayed on the system moni-
tor, from left to right. Channel 0 is the left-most channel while channel 191 is the
right-most for a 192-element transducer. Channel 32 is the left-most and channel 159 is
the right-most channel for a 128-element transducer.
Diagnostic channel references refers to the numbering system used in diagnostic test
results.
Transmit receive PWA (TR) identifies which TR board - TR0, TR1 or TR2 - corresponds
to a particular channel or set of channels.
TXPG ASIC identifies which TXPG ASIC corresponds to a particular channel or set of
channels.
Receive Beanformer (RXBF) ASIC identifies which RXBF ASIC corresponds to a partic-
ular channel or set of channels.
Fig. 24: Channels 0-31



Appendix A: Test Results and Test Summary 0
An example of a test results and a test summary can be found in: (US03-101.840.71 /
System Logs.exe).

Appendix B: How to Access ImagingBE and Firmware Logs 0
If the Local Service Page is available:

1. Select Presets
2. Select Service in the left plane
3. Select Local Service
4. Type in the service key - Level 7 or higher is required
5. Select Utilities
6. Select Escape to OS from the dropdown menu.
7. Type EXPLORER in the parameter field and select Go in the lower right corner.
8. Select the C Drive under My Computer.
9. Select the Syngo Directory
10. Select Log.
11. Identify the ImagingBE.log, ImagingBE.1.log, ImagingBE.2.log and the fwlog.txt
files.
12. Double click the file to open. The log should open in Notepad.
If the Local Service Page is NOT available:

1. Boot the system in safe mode. See (Appendix D: How to Boot in Safe Mode / p. 59)
The system is booted up in safe mode with a prompt.
2. Type EXPLORER at the command line and select Enter.
3. From Explorer, select the C Drive under My Computer.
4. Select Syngo.
5. Select Log.
6. Identify the ImagingBE.log, ImagingBE.1.log, ImagingBE.2.log and the fwlog.txt
files.
7. Double click the file to open. The log should open in Notepad.
What to look for in a ImagingBElog 0
The ImagingBE log will display test results. Any problems or faults will be noted in the log
and will be preceded by the word ERROR!

Appendix C: Examples of ImagingBE and Firmware Logs 0
Imaging Log 0
At each reboot, a new BE log is generated. ImagingBE.log is the log from last reboot. The
system saves up to 3 BE logs at a time. Scroll through the log and look for error indica-
tions.
An example of a BE log can be found in: (US03-101.840.71 / System Logs.exe).
Firmware (FW) Log 0
The FW log gets updated every time a firmware load is executed. Typically, a firmware
load takes place if a new module or board is installed. The system checks the firmware
revision and loads new firmware if necessary.
A firmware load can take place if a 4D transducer is connected or a software patch or
combine code is installed.
If firmware is loaded or if an attempt is made to load firmware, information will be
appended to the fw log. The most recent information will be at the end of the log.
What to look for in a FW log

Firmware tests check to see if the correct firmware has been/is installed on the system. If
the test discovers that the fw is not current, it will search for the proper fw revision and
attempt to load the correct version. It will then attempt to verify that the correct firmware
was properly loaded. The firmware log will alert the CSE to the status of the firmware.
Firmware Log Example

The following information is an example of a firmware log pulled from an Antares system.
The log itself can also be found in: (US03-101.840.71 / System Logs.exe).
Firmware log
Mon Oct 04 15:33:57 2004
Zm System : Software Installed
Mon Oct 04 15:57:18 2004
Back End : Configuration mismatch Back End PCI FW rev expected 29.29, actual 29.22
Mon Oct 04 15:57:19 2004
Video Interface : Configuration mismatch Video Interface VCLK FW rev expected 5.0,
actual 4.0
Mon Oct 04 15:57:19 2004
Back End : Loading c:\zdt\program_PCI_29.29_0.sbs to Back End
Mon Oct 04 15:58:33 2004


Mon Oct 04 15:59:46 2004
Back End : Verify c:\zdt\verify_PCI_29.29_0.sbs on Back End
Mon Oct 04 15:59:49 2004
Mon Oct 04 15:59:53 2004
Video Interface : Loading c:\zdt\program_VCLK_5.0_0.sbs to Video Interface
Wed Oct 06 10:30:54 2004
Receive Control : Configuration mismatch Receive Control RTC FW rev expected 07.15,
actual 07.02
Wed Oct 06 10:30:54 2004
Back End : Configuration mismatch Back End DSP FW rev expected 1.75, actual 1.70
Wed Oct 06 10:30:54 2004
Back End : Configuration mismatch Back End FPA FW rev expected 4.5, actual 3.5
Wed Oct 06 10:30:54 2004
Back End : Configuration mismatch Back End PCI FW rev expected 29.29, actual 29.14
Wed Oct 06 10:30:54 2004
Transducer Interface : Configuration mismatch Transducer Interface TI FW rev expected
5.53, actual 5.29
Wed Oct 06 10:30:54 2004
Realtime Manager : Configuration mismatch Realtime Manager BIOS FW rev expected
1.0.7, actual 1.0.6
Wed Oct 06 10:30:55 2004
Receive Control : Loading c:\zdt\program_RTC_07.15_0.sbs to Receive Control
Wed Oct 06 10:32:08 2004
Receive Control : Loading c:\zdt\program_RTC_07.15_1.sbs to Receive Control
Wed Oct 06 10:33:21 2004
Back End : Loading c:\zdt\program_dsp_1.75 to Back End
Wed Oct 06 10:34:42 2004
Back End : Verify c:\zdt\program_dsp_1.75 on Back End
Wed Oct 06 10:34:42 2004
Back End : Loading c:\zdt\program_FPA_4.5_0.sbs to Back End
Wed Oct 06 10:35:55 2004
Back End : Loading c:\zdt\program_FPA_4.5_1.sbs to Back End
Wed Oct 06 10:37:08 2004
Back End : Verify c:\zdt\verify_FPA_4.5_0.sbs on Back End

Wed Oct 06 10:37:12 2004

Back End : Verify c:\zdt\verify_FPA_4.5_1.sbs on Back End
Wed Oct 06 10:37:15 2004
Wed Oct 06 10:38:28 2004
Wed Oct 06 10:39:41 2004
Wed Oct 06 10:39:44 2004
Wed Oct 06 10:39:48 2004
Transducer Interface : Loading c:\zdt\program_TI_5.53_0.sbs to Transducer Interface
Wed Oct 06 10:41:01 2004
Transducer Interface : Verify c:\zdt\verify_TI_5.53_0.sbs on Transducer Interface
Wed Oct 06 10:41:04 2004
Realtime Manager : Loading c:\zdt\program_BIOS_1.0.7.bin to Realtime Manager
Wed Oct 06 10:41:27 2004
Realtime Manager : Verify c:\zdt\program_BIOS_1.0.7.bin on Realtime Manager

Appendix D: How to Boot in Safe Mode 0
To be able to access important information at times, it may be necessary to boot in safe

mode. Before the system will boot into safe mode, certain settings need to be temporarily
altered - USB legacy must be enabled and the system splash screen must be disabled.
NOTE Disconnect the QuickStart battery, if installed.
To enable USB Legacy:

1. Ensure the system is completely powered down and not in standby mode.
2. Turn on power using the green power switch, located near the CD-R.
3. Press and hold the Ctl and Browser keys on the keyboard.
NOTE If this does not work, power down system and retry. Instead of
holding down the Ctl and Browser keys, hold down the Ctl key and
then quickly and continuously tap the Browser key.
4. The system will boot to the BIOS setup menu.

5. Use the left-right arrow keys to navigate to the Advanced header.
6. Use the Up-Down arrow keys to navigate to Legacy Support.
7. Press Enter on the keyboard.
8. Select Enable from the drop down menu.
To be able to boot into safe mode, the splash screen must first be disabled. The following
steps are only necessary if the system has software rev 3.0 installed.
NOTE In the Windows BIOS, the screen is called a clean screen and is
the same thing as the splash screen. The term splash screen will
be used exclusively except when referencing text taken directly
from the Windows BIOS.
How to disable the splash screen:

1. From the main BIOS, select Keyboard Features.
2. Press Enter on the keyboard.
3. Navigate to the Clean Screen entry.
4. Select Disable from the drop down menu.
How to Boot in safe mode
1. Once the splash screen and the Legacy USB settings are changed, press the Text D
key on the keyboard. The system will start to reboot.
2. Press and hold the Text B key on the keyboard.

3. Continue holding the key until the system starts beeping, then release the key.
4. A screen will come up asking how the system should be booted. Select Safe Mode
with a Command Prompt.
5. Press Enter on the keyboard
6. The system will ask which OS should be loaded. Choose MS Windows Profession-
al and press Enter on the keyboard.
7. The system will boot to Safe Mode with a Command Prompt.
NOTE After leaving Safe Mode and rebooting the system, the Antares will
not restore the BIOS defaults. Please re-enter the BIOS and change
the Clean Screen setting to Enable and the USB Legacy setting to
Disable.

Appendix E: Test Descriptions 0
The main goals for the Antares system diagnostics are:
1. Accurate diagnosis of defective Field Replaceable Units (FRUs).

2. Local execution with no external test equipment.
3. Remote execution via Siemens SRS.
The test functions are individually executable address the following FRUs:
Field Replaceable Units
Back-end Board
Transmit Receive Board
Receive Control
Continuous Wave Beamformer (for future use)
Transducer Interface
Control panel
RealTime Manager
Video Input/Output
Input / Output Board
Physio Module
E Module
The individually executable test functions and the FRUs they address are described in the
following outline.
Unless otherwise specified these tests require no external test equipment.
Front-end Segment 0
Real Time Controller Memory Test

Standard memory test performed on all testable registers and memory spaces.
Test Coverage - Real Time Controller Memory Test
Coverage for this test includes the FEBus interface from the BE board, the RTC FEBus
interface the RTC internal and the external RTC SRAM

Fig. 29: Test Coverage, Real Time Controller Memory Test
Receive Control Sequencer Test

Functional test of the ability of the RC to program the TR cards and its own RXBF ASICs
at high speed. The target registers and tables are first cleared. Patterns are stored in the
RC index state machines tables. A sequence is loaded that is expected to move the pat-
terns out to the TXPG and RXBF ASICs. The sequence is executed and the results veri-
fied.
Test Coverage - Receive Control Sequencer Test
Coverage for this test include the local uP bus from the RTC to the RXBF asics, the
TCBus to the TR and TI boards. The local interfaces on the TR board, the Control EPLD
and the TXPGs, the local interface and the Control EPLD on the TI board.

Fig. 30: Test Coverage - Receive Control Sequencer Test
Receive Beamformer ASIC Memory Test

Test Coverage - Receive Beamformer ASIC Memory Test
This test covers the RXBF internal registers and SRAM plus the FEBus interface to the
RTC and the local uP bus.

Fig. 31: Test Coverage, Receive Beanformer ASIC Memory Test
Receive Beamformer ASIC Built-in Self-test

A file list of register values is loaded into each asic. The device is programed to initiate a
BIST function and the return signatures are compared with expected values. A self con-
tained RAM BIST is also executed and the results are displayed.
Test Coverage - Receive Beamformer ASIC Built-in Self-test
This test covers the RXBF internal registers and SRAM plus the FEBus interface to the
RTC and the local uP bus

Fig. 32: Test Coverage - Receive Beamformer ASIC Built-in Self-test
Transmit Pulse Generator ASIC Memory Test

Test Coverage - Transmit Pulse Generator ASIC Memory Test
This test covers the TXPG internal registers and SRAM plus the TCBus interface to the
TR and the local uP bus.

Fig. 33: Test Coverage, Transmit Pulse Generator ASIC Memory Test
Transmit Pulse Generator ASIC Built-in Self-test

The TXPG Built-in Self Test is composed of three sub-tests described in the following sec-
tions.
Txpg pass counter test
This test will exercise the TXPG by generating 255-4.5 mhz waveforms per channel from a
minimum length 8 nibble data pattern loaded into the Hout and Lout lower memories. The
memory will be loaded with a minimum ram length nibble pattern so that the number of
ram Pass Counters of each channel will be exercised extensively. All channels will be set
to 0 delay to speed up testing.
Txpg nibble counter test
The test will exercise the TXPG by generating 33-2.48 mhz waveforms from a maximum
ram length data pattern of 696 nibbles loaded into lower memory for even channel checks
and upper memory for odd channel checks.
Txpg delay counter test

This test will exercise the TXPG by generating only one 4.5 mhz pulse sequence per
channel after a maximum length channel delay.
Test Coverage - Transmit Pulse Generator ASIC Built-in Self-test
This test covers the TXPG internal logic and SRAM plus the TCBus interface to the TR
and the local uP bus.
Fig. 34: Test Coverage, Transmit Pulse Generator ASIC Built-in Self-test
Receive Test
A signal source on the RC is routed through the TI to all receive channels and sampled by
each RXBF ADC. Signal analysis on samples in each RXBF SRAM are used to verify
each receive channel.
Test Coverage - Receive Test
Coverage includes the RC boards FEBus interface, RTC, RXBFs, gain controls and
TCBus interface; the TR boards TCBus interface, receive amplifiers and signal paths and
gain controls; TI boards BIT test signal routing and internal power divider.

Fig. 35: Test Coverage - Receive Test
Transmit Tests
The test will be done by transmitting on each channel in turn or multiple channels delayed
with increasing delay per channel and examining the signal received in the RXBF SRAM
of channel 16. This TRRCS channel can be connected to the TIRCMSR inputs which per-
mit an independent signal path. The resistive power combiner on the TI board can be
directed to this measurement path. Signal analysis on these samples will verify that each
of the transmitters fire.
The transmit test must be executed twice, once for each of the 2 transmit voltage supplies.
Test Coverage - Transmit Tests
Coverage includes the RC boards FEBus interface, RTC, RXBF channel 16, and TCBus
interface; the TR boards TCBus interface, transmit pulsers and signal paths and transmit
voltage controls; TI boards BIT test signal routing and internal power combiner or the
external PCD.

Fig. 36: Test Coverage - Transmit Tests
Continuous Wave Transmit Test (SCW TX Pwr Calibration)

This test is in reality a test of the TR boards. It has been accomplished by designing and
implementing a SCW Transmit power calibration test. The test sets up the transmitters to
transmit in Infinite Pulse Mode, at 1.818 MHz. Using an External Power divider combiner
as a load the waveform of the CW signal produced by transmitting on 64 channels is cap-
tured in RXBF channel 16 via the TIRCMSR circuit. Analysis of the data provides a value
for the absolute power per channel. The test then increments the Transmit power control
code and repeats the data gathering and analysis process. The output of the test is a set
of calibration values that are used by OPSW to cause each system to behave the same in
regard to SCW transmit power requests.
The Data that is stored in the RC board ID prom is made available to OPSW via a text file.
The text file is generated by the test and any time Zdt starts up.
Test Coverage - Continuous Wave Transmit Test
Not applicable to the CB.

Continuous Wave IQ Phase and Gain Calibration Test

This test injects a signal from an external source into the CB boards Pencil Probe CW
input. The external source delivers a signal whos frequency is the current operating fre-
quency plus two kilo Hertz. The CB board is properly set up for this mode of operation.
The signal is processed as a PPCW signal and IQ data is gathered at the SIP. The Base-
band IQ data is analyzed for Phase difference and amplitude ratio. The phase difference
from exactly 90 deg of the Q data and the amplitude ratio of I/Q are saved and stored in
the CB boards IDProm. A calibration value for each operating frequency, each high pass
filter setting and each baseband gain setting is stored. The total number of values is 162
(9X2X9).
The Data that is stored in the CB board ID prom is made available to OPSW via a text file.
The text file is generated by the test and any time Zdt starts up and detects that the CB
Serial number has changed from the last time the file was generated. (The CB board
Serial number is imbedded in the file).
Test Coverage - Continuous Wave IQ Phase and Gain Calibration Test
The test covers the Pencil probe CW input amplifier, Frequency specific band pass filter
section, RF mixer section, base band gain section, the selectable high pass filter section,
the low pass anti-aliasing section and the Analog to Digital converter section.
Pencil Probe CW Receive Test

The Pencil probe CW receive test sets up the CB board from the test selectable operating
frequency, base band gain and high pass filter settings. The pseudo random signal gener-
ator resident on the RC board is used to inject a test signal into the Pencil Probe CW input
via the TI board diagnostic test circuit. IQ data is gathered at the SIP and Analyzed for sig-
nal level at a particular frequency. The raw time domain data is processed by a
Cooley-Tukey radix-2, DIF fft function. It provides a frequency resolution of 9.5367 Hz.
The pseudo random generated will provide frequency content that will span more than
one bin but will be consistent from machine to machine.
Steerable CW Receive Test

The Steerable CW receive test sets up the CB board from the test selectable operating
frequency, base band gain and high pass filter settings. The pseudo random signal gener-
ator resident on the RC board is used to inject a test signal into all of the TR RF signal
paths via the TI board diagnostic test circuit and power divider. IQ data is gathered at the
SIP and Analyzed for signal level at a particular frequency. The raw time domain data is
processed by a Cooley-Tukey radix-2, DIF fft function. It provides a frequency resolution of
9.5367 Hz. The pseudo random generated will provide frequency content that will span
more than one bin but will be consistent from machine to machine.
Pencil Probe CW Transmit Test

The Pencil Probe CW transmit test sets up the CB board from the test selectable operat-
ing frequency and transmits its CW signal to the TI board which as been configured to
direct the PPCW transmit to the TIRCMSR circuit. The data is gathered via TRRCS chan-
nel 16. The data is analyzed for power and compared to and expected absolute value.

Power supply and Reference Test

A 14 bit ADC on the RC board will be accessed to convert power supply and reference
signal voltages. These are all DC measurements and will have PASS/FAIL limits applied
to each signal individually. A measurement bus has be defined to allow each board
accessed to drive the input to the single A/D with the power supplies and references for
that board.
In addition to the Power supply and reference test there is a sub-set test that accesses
only the available power supplies. Most are available on the RC, the TI and CB are
accessed for the others. There are 5 Digital supplies (PSD) and 12 Analog supplies
(PSA). The diagnostic A/D can access 8 of the Analog supplies, 10 if there is a CB board
and ONE Digital supply. The 4 digital supplies will more than likely preclude the BE board
from working at all if they are non-functional.
Test Coverage - Power supply and Reference Test
Coverage includes the RC boards Diagnostic ADC, input muxes, local uP bus and the
RTC and its FEBus interface; the TR boards diagnostic analog mux; the TI boards diag-
nostic analog mux.
Fig. 37: Test Coverage - Power supply and Reference Test

Control Dac Test 0
The Control Dac test exercises the TGC, AAC, TXV0, TXV1, PSMON0 and PSMON1 con-
trol dacs. Each dac output, or a derivative of it is available at the mux of each TR board.
For general tests related to the RC board the mux on the first TR board is used. For TR
board specific tests the mux on the Board under test is used.
The mux output drives the Diagnostic A2D converter on the RC board. Each dac is incre-
mented over its entire range. The acquired values from the ADC are processed for Slope,
Offset and RMS deviation. Limits are applied to each of these values.
The PSMON0 and 1 dacs are not directly tested. These dacs are tested by setting the
PSMON dac then incrementing the TXV dac until the corresponding interrupt occurs. The
TXV value is acquired and when all PSMON values have been exercised then the same
Slope, Offset and RMS calculations and limits are applied. The Slope and Offset values
from the TXV test, which is always executed first, are used to minimize errors in this calcu-
lation.
Test Coverage - Control Dac Test

These tests exercise the RC board Dacs and ADC the TXV power supplies and Various
analog buffers on the RC and TR boards.

Fig. 38: Test Coverage - Control Dac Test
Transducer Interface Memory Test

Test Coverage - Transducer Interface Memory Test
Coverage includes the TI board register and memory.

Fig. 39: Test Coverage, Transducer Interface Memory Test
Transducer Interface Probe Relay Test

The Capacitive combiners on the TI board which can be directed to the TIRCMSR bus will
be used to verify that a transmitter can transmit across each relay tree for each of the
three positions of the probe connect relays. A version of the transmit test will be used to
do this verification test. The purpose of the test is to find broken relays so minimal signal
analysis will be done.
Test Coverage
Coverage includes the same hardware as plus the TI boards capacitive combiners.

Fig. 40: Test Coverage, Transducer Interface Probe Relay Test
Back-end Segment 0
PCI FPGA Memory Test - BE

Standard barberpole memory test performed on all testable registers and memory spaces
on the BE PCI FPGA.
Test Coverage - PCI FPGA Memory Test
The internal memory spaces in the BE PCI FPGA.

Fig. 41: PCI FPGA Memory Test Coverage
Digital Receiver ASIC Memory Test - BE

of each of the DR ASICS. Note that there are 4 separate tests, one for each ASIC.
Test Coverage -Digital Receiver ASIC Memory Test
The internal memory spaces in the DR ASICs and the BE local bus.
Digital Receiver ASIC Built-in Self-test - BE

Standard ASIC signature test. The resulting digital signature is compared to simulation
results. Note that there are 4 separate tests, one for each ASIC.
Test Coverage -Digital Receiver ASIC Built-in Self-test
The internal memory spaces in the DR ASICs and the BE local bus.

Fig. 42: DR Memory & BIST Test Coverage
Echo Processor ASIC Memory Test - BE

in the EP ASIC.
Test Coverage -Echo Processor ASIC Memory Test
The internal memory spaces in the EP ASIC and the BE local bus.
Echo Processor External Memory Test - BE

Standard barberpole memory test performed on the EP external Persistence SRAM.
Test Coverage -Echo Processor ASIC External Memory Test
The EP ASIC interface for external SRAM, the SRAM memory devices and the BE local
bus.
Echo Processor ASIC Built-in Self-test - BE

The BIST setup for the EP is imported directly from the ASIC design simulation. A CRC
signature is generated and compared to simulation results.
Test Coverage -Echo Processor ASIC Built-in Self-test
This test covers the EP internal registers and SRAM plus the local uP bus.

Fig. 43: EP Memory & BIST Test Coverage
Flow Processor ASIC Memory Test - BE

on the FP ASIC. Note that this test is skipped for all BE boards with P/N 7466746 or later.
These have an updated FP ASIC that does not support reading from the ASIC.
Test Coverage -Flow Processor ASIC Memory Test
The internal memory spaces in the FP ASIC and the BE local bus.

Fig. 44: Test Coverage -Flow Processor ASIC Memory Test
Flow Processor CTB Memory Test - BE

on the FP ASIC.
Test Coverage -Flow Processor ASIC Memory Test

The external Corner Turning Buffer (CTB) memory space and the BE local bus.

Fig. 45: Flow Processor Memory Test Coverage
Flow Processor FPGA Memory Test - BE

in the EP ASIC.
Test Coverage -Flow Processor FPGA Memory Test
The internal memory spaces in the FP FPGA and the BE local bus.
Flow Processor FPGA External Memory Test - BE

Standard barberpole memory test performed on the FP external Persistence SRAM.
Test Coverage -Flow Processor FPGA External Memory Test
The FP FPGA interface for external SRAM, the SRAM memory devices and the BE local
bus.

Fig. 46: FP FPGA Memory Test Coverage
Scan Converter ASIC Memory Test - BE

in the SC ASIC.
Test Coverage -Scan Converter ASIC Memory Test
The internal memory spaces in the SC ASIC and the BE local bus.
Scan Converter External Memory Test - BE

Standard barberpole memory test performed on the SC Cine and Raster buffer SDRAM.
Test Coverage -Scan Converter ASIC External Memory Test
The SC ASIC interface for external SDRAM, the SDRAM memory devices and the BE
local bus.

Fig. 47: SC Memory & Bist Test Coverage
SIP FPGA Memory Test - BE

from the host CPU.
Test Coverage -SIP FPGA Memory Test
All internal RAM accessible by the CPU via PCI.
Digital Signal Processor IPC Test - BE

Diagnostic DSP firmware is loaded into the DSP program RAM via the Host Port Interface
(HPI) and a set of Inter-Processor Command (IPs) packets are sent from the host CPU to
the DSP. The DSP performs a checksum of each packet and sends it back to the host.
Test Coverage -Digital Signal Processor Memory Test - BE
Test Coverage -Digital Signal Processor IPC Test

Control and interrupt interface between the SIP FPGA and the DSP.
Test Coverage -Digital Signal Processor Memory Test - BE

Diagnostic DSP firmware is loaded into the DSP program RAM via the Host Port Interface
(HPI) and a memory test performed on all DSP external memory spaces.

Fig. 48: DSP Test Coverage
Video Interface Segment 0
Decoder FPGA Memory Test - VI

Standard memory test performed on all testable registers and memory spaces in the VI
Decoder FPGA.
Test Coverage -Decoder FPGA Memory Test

A series of audio tones are generated by the BE DSP and are heard on the system speak-
ers. The operator is prompted to indicate pass or fail.
Encoder FPGA Memory Test - VI

Encoder FPGA.
Test Coverage -Encoder FPGA Memory Test

The internal memory spaces in the Encoder FPGA and the VI local bus.

VPDM ASIC Memory Test - VI

VPDM ASIC except for the external SDRAMs.
Test Coverage -VPDM ASIC Memory Test

The internal and external memory spaces in the VPDM ASIC and the VI local bus.
VPDM SDRAM Test - VI

Four memory tests are available for the external SDRAM associated with the VPDM. Two,
the Address Data Test and the Bank Address Test, are enabled by default but may be
optionally disabled for troubleshooting support. Two other tests, the Checkerboard Test 0
and Checkerboard Test 1, may be enabled for troubleshooting support.
Test Coverage -VPDM ASIC Memory Test

The Address Data Test accesses all memory locations the external SDRAM. The test
checks the operation of all address and data lines, and identifies row and column address-
ing errors. The test cannot identify bank addressing errors.
The Bank Address Test identifies bank addressing errors.
The two checkerboard tests may be used to write alternating ones and zeros to every bit
in SDRAM.
Each test returns up to 30 error messages identifying the SDRAM LUT index, the device,
bank, row, and column of the failing location, and the expected and actual data read from
the location.
Control Panel Tests - CP 0
Executes the CP power-on self test on the CP sub-processor and reads the result back.
The POST tests executed are:
CPU Check
RAM Check
Boot Block CkSum
App Code CkSum
Stuck Key
Control Panel Manual Test

A graphical layout of the control panel is presented on the system monitor showing all the
keys, knobs, sliders and toggle switches.
The controls on the display highlight when that control is used. The operator presses each
key, turns and presses each knob, slides the sliders and toggles the toggles.

Physio POST Test

Execute the built-in power-on self test on the external Physio Signal module and reports
the result. Possible errors include:
Physio POST: ROM Error

Physio POST: SRAM Error
Physio POST: I/O Error
Physio POST: Software Error
System Level Tests - RC, BE, VI 0
The approach for each of the mode functional tests is to load a static test pattern into the
RXBF delay SRAMs and to program the entire system (excepting transmit channels) to
beamform and image this data in each of the specified modalities.
After a fixed number of frames the sequencer is stopped. Register data and CRC values
for memory data are examined to verify system operation in the specified imaging mode.
For each mode of operation a meaningful visual pattern is displayed on the system.
Register data and CRC values isolate the section of the EM that is responsible for a test
failure.
Tests are defined for the imaging modes listed below.
B-Mode
The test emulates B-Mode imaging operation for a C5-2 transducer set for maximum
depth and 4 parallel beams.
The test stimulus is a 2.2 Mhz sine wave pattern loaded into all RXBF Delay SRAMs.
Imaging is enabled for a fixed number of frames then halted. Register values are tested for
the RC board, for the VPSC ASIC on the BE board, and for the VPDM ASIC on the VI
board. When register values indicate successful operation, CRC values are calculated
from the following: Synthetic Aperture memories associated with all 4 DR ASICs on the
BE board, RP Raster memory associated with the VPSC ASIC on the BE board, and ras-
ter memory associated with the VPDM ASIC on the VI board. If register values indicate
that data were not processed as expected at any point, subsequent CRC values are not
calculated.
B-Mode System Test Coverage

The entire digital B-Mode data path is tested, from the RXBF ASICs on the RC board
through to the raster video area of SDRAM and the VPDM ASIC on the VI board.

Fig. 49: B-Mode System test Coverage
BC-Mode
The test emulates BC-Mode imaging operation for a C5-2 transducer with a color ROI set
for minimum width and maximum height.
The test stimulus is a 2.2 Mhz sine wave pattern loaded into all RXBF Delay SRAMs.
Imaging is enabled for a fixed number of frames then halted. Register values are tested for
the RC board, for the VPSC ASIC on the BE board, and for the VPDM ASIC on the VI
board. When register values indicate successful operation, CRC values are calculated
from the following: Synthetic Aperture memories associated with two DR ASICs on the BE
board, RP Raster memory associated with the VPSC ASIC on the BE board, and raster
memory associated with the VPDM ASIC on the VI board. If register values indicate that
data were not processed as expected at any point, subsequent CRC values are not calcu-
lated.
BC-Mode System Test Coverage

The entire digital BC-Mode data path is tested from the RXBF ASICs on the RC board
through to the raster video area of SDRAM and the VPDM ASIC on the VI board. Both the
echo path through the DR and EP ASICs and the flow path through the FP ASIC and FP
FPGA are evaluated.

Fig. 50: BC Mode System Test Coverage

Appendix F: Board Tests and Related Failures 0
Diagnostic Test Tools 0
In this Stage, the higher level FRU diagnostic test suites can be run.
To access the diagnostic tests, a site-specific service access key Level 7 is needed. Ser-
vice access keys for the Antares are based on the system serial number. The CSE or user
who requires a Service key obtains it through Service.
1. Select Presets from the imaging toolbar or from the keyboard.

2. Select Service
Fig. 51:

3. Select Local Service.
Fig. 52:
4. The Service Authentication page appears. Enter the service access key and click OK.
The Service access key is a 20-digit alphanumeric password. The first 14 digits are
placed in the first field and the last six are placed in the second field. Clicking the Set as
Default box will save only the first 14 digits upon reboot. The final six must me entered
manually after each entrance to the local service page. if the Set as Default box is not
checked, the entire access key must be re-entered on reboot.
Fig. 53:

5. The Service Home page appears. Click TestTools to go to the TestTools screen. A
message will appear saying: Please insure [sic] that all probes are dis-
connected and REMOVED from the three connectors of the system.
This is REQUIRED for tests to operate properly. Ensure that all trans-
ducers are disconnected from the transducer interface, then click OK.
6. The TestTools screen allows access to all of the higher level FRU tests, including the E
Module test, E Module board level tests, transducer interface test, Power Supply test,
Physio Module test, transducer tests and CD-ROM tests.
Fig. 54:

7. Select Board Test, a sub-menu for E Module test. A new menu will appear which will
show all the available board tests.
Fig. 55: Board Tests

8. Select the appropriate test and click Start to run the tests. An Estimated Time counter
shows approximately how much time is needed to complete the diagnostic tests. The
counter will count down during the tests, which is indicated by the letters dn next to the
timer. When the estimated time has been exceeded, the counter will start counting up,
indicated by the letters up.
Fig. 56:
9. After the tests are completed, scroll to the bottom of the scroll box and check the status
of the tests. If the test fails, a detailed report of the failure can be found on the Reports
page.

Test target areas

The next section will show a series of tables which explain the tests performed in each
section of the system, which board is targeted in each section of the test and the primary
focus of that test. The tests will be executed as part of the board tests.
Tab. 19 Front End Test target areas
Test Front End TR Board RC Board E Module TI Module

Test Test Test Test
Real Time Controller Memory Test RC Memory FE Memory
Receive Control Sequencer Test TR Cntrl Seq RC Cntrl Seq RTC RTC
Receive Beamformer ASIC Memory RC Memory FE Memory
Test
Receive Beamformer ASIC Built-in RC Memory FE Memory
Self-test
Transmit Pulse Generator ASIC TR memory FE Memory
Memory Test
Transmit Pulse Generator ASIC TR memory FE Memory
Built-in Self-test
Receive Test TR receive Receiver Receiver
Receive Color Test
Transmit Tests TR transmit TR Transmit
Continuous Wave Transmit Test
(SCW TX Pwr Calibration)
Continuous Wave IQ Phase and
Gain Calibration Test
Pencil Probe CW Receive Test
Steerable CW Receive Test
Pencil Probe CW Transmit Test
Power supply and Reference Test TR Diags RC Diags Refs Refs
Transducer Interface Memory Test TI Memory
Transducer Interface Probe Relay Probe Relay
Test
Thermistor Measurement Test Thermistor
Overcurrent Test Overcurrent

Tab. 20 Backend Test Target Areas
Test Backend BE EM
PCI FPGA Memory Test - BE BE Memory BE Memory
Digital Receiver ASIC Memory Test - BE
Digital Receiver ASIC Built-in Self-test - BE BE Memory BE Memory
Echo Processor ASIC Memory Test - BE BE Memory BE Memory
Echo Processor External Memory Test - BE BE Memory BE Memory
Echo Processor ASIC Built-in Self-test - BE BE Memory BE Memory
Flow Processor ASIC Memory Test - BE BE Memory BE Memory
Flow Processor CTB Memory Test - BE BE Memory BE Memory
Flow Processor FPGA Memory Test - BE BE Memory BE Memory
Flow Processor FPGA External Memory Test - BE BE Memory BE Memory
Scan Converter ASIC Memory Test - BE BE Memory BE Memory
Scan Converter External Memory Test - BE BE Memory BE Memory
SIP FPGA Memory Test - BE BE Memory BE Memory
Digital Signal Processor IPC Test - BE BE Memory BE Memory
Digital Signal Processor Memory Test - BE BE Memory BE Memory
Digital Signal Processor Program Verify- BE BE Memory BE Memory
Tab. 21 Test Video Interface target areas
Test Video Interface Segment VI EM

Decoder FPGA Memory Test - VI VI Memory VI Memory
Encoder FPGA Memory Test - VI VI Memory VI Memory
VPDM ASIC Memory Test - VI VI Memory VI Memory
VPDM SDRAM Test - VI VI Memory VI Memory
Tab. 22 Basic Test target areas
Test RC BE VI EM
Physio POST Test
System Level Tests - RC, BE, VI+
B Mode B Mode B Mode B Mode B Mode

Test RC BE VI EM
BC-Mode BC Mode BC Mode BC Mode
Doppler Audio Check - BE, VI, IO, Speakers Audio
Test Summary and Test Results

The executed tests will produce a series of results which can be found in the Report Files
area. To bring up the information:
1. In the upper right corner, select Reports. This will bring up the Report Files page.
2. Click Test Results to bring up a directory of results.
Fig. 57:

3. Find and click Test Results.htm in the Hierarchal listing to show a detailed report of
the test, which may be used for further troubleshooting.
Fig. 58:
4. If multiple TestResults.htm items appear in the log, use the date and time to deter-
mine which summary is the most recent.
NOTE If the E Module test or any of the board tests fails, scroll through
the test results to identify which module/board is the root cause.
Use the information in (Appendix A: Test Results and Test
Summary / p. 54)
5. A brief summary of the test results can also be found in TestSummary.
Transmit test 0
The transmit test exercises all 192 transmit circuits (EM level test) or all 64 transmit cir-
cuits (TR0, TR1, TR2 level tests). Antares has two transmit voltage sources (TXV0 and
TXV1). The transmit test uses TXV0 and then TXV1; the resulting sets of data (192 or 64
rows) are analyzed independently. The outputs of the transmit circuits on the TR board
are routed to the TI board where a resistor combiner combines the 192 or 64 channels
onto one signal line. This signal line is routed from the TI to the RC board. On the RC
board the signal is routed to the RXBF ASIC corresponding to channel 16 and the wave-
forms are stored in the SRAM of this ASIC. The stored SRAM data is then analyzed.

Tab. 23 Transmit Receive Tests and Related Failures
Failing EM Failing EM board data Corresponding Image Troubleshooting Sugges-

board type presentation indication tion
TR Median Pwr to Chan Vari- Image may indicate a Refer to (Channel
ation limit failures Typically dead channel correspond- Map / p. 51) to link failing
1 or 2 channels out of ing to the failing channel. channel to TR board.
range, or 8 consecutive Refer to (Channel The TR test will indicate
channels corresponding to Map / p. 51)to correlate which board is failing. Swap
TXPG groupings (refer to diagnostic failure to imag- TR boards to ensure the fail-
(Channel Map / p. 51)) ing observation ures are board-related.
Absolute THI power limit Image may indicate a Refer to (Channel
failures dead channel in THI mode Map / p. 51) to link failing
Typically 1 or 2 channels corresponding to the fail- channel to TR board.
out of range, or 8 consec- ing channel, refer to The TR test will indicate
utive channels corre- (Channel Map / p. 51)to which board is failing. Swap
sponding to TXPG correlate diagnostic fail- TR boards to ensure the fail-
groupings (refer to (Chan- ure to imaging observa- ures are board-related.
nel Map / p. 51)) tion.
All 192 channels failing If this occurs 1 of the 3 TRs

Absolute Median and is the probable cause;
Mean Power Limits It is possible to remove a TR
board, boot up the system,
and execute TR tests on the
others.
When the defective TR is
removed, the transmit test
will pass on the other TRs
RC Absolute Median and Image may not indicate a
Mean Power limit failures, problem since RC failures
where all channels or a of this type are limited to
large number of channels diagnostic related hard-
fail. This would be caused ware and unique diagnos-
by a problem on the RC tics measurement path.
unique to processing of
the combined signal on
the RC.

Failing EM Failing EM board data Corresponding Image Troubleshooting Sugges-

board type presentation indication tion
TI Absolute Median and Image may not indicate a
Mean Power limit failures, problem since TI failures
where all channels or a of this type are limited to
large number of channels diagnostic related hard-
fail. This would caused by ware and unique diagnos-
a problem with the resis- tics measurement path.
tive combiner on the TI.
RM, BE, VI RM, BE or VI not known to
cause ONLY a transmit
test failure.
Receive Test 0
The receive test exercises all 192 receive circuits (EM/RC level test) or all 64 receive cir-
cuits (TR0, TR1, TR2 level tests). The receive test uses two gain settings (26 and 14); the
resulting two sets of data are analyzed independently. The RC board has a stimulus
source that is used for the receive test. This stimulus source is routed to the TI board
where a resistor divider distributes this stimulus to the 192 or 64 channels. From the TI,
these signals are routed to the TR where filtering and gain is applied. From the TR these
signals are routed to the RC board and then the waveforms are stored in the SRAM of
respective RXBF ASICs. The stored SRAM data is then analyzed.

Tab. 24 Receive Test and Related Failures
Failing EM Failing EM board data presentation Corresponding Troubleshooting

board type Image indication Suggestion
TR Rel to Med Chan Variation Limit fail- Image may indicate a Swap TRs and then
ures, typically 1 or 2 channels out of dead channel or noise repeat test.
range corresponding to the If the failing chan-
failing channel, refer to nel(s) remains the
(Channel same then the RC
Map / p. 51)to corre- board is the cause.
late diagnostic failure
to imaging observa- If the failing channel
tion. moves with the TR
per the (Channel
RC One or two channel failures; channel Image may indicate a Map / p. 51) then TR
failures in groups of 16 corresponding dead channel(s) or is the cause
to a RXBF; or all channels failing in a noise corresponding to
similar manner. the failing channel,
refer to (Channel
Map / p. 51) to corre-
late diagnostic failure
to imaging observa-
tion.
RM, BE, VI RM, BE or VI not known to cause
ONLY a receive test failure.
Zm System B-Mode Test 0
This test inputs a known set of data into the RC board and the system processes this data
from the RC through the DR, EP, and SC sections of the BE and then to the VI board. A
CRC is a method of detecting a 1 bit mismatch. Once a CRC fails, this failure will propa-
gate through the remaining CRC checks. Thus the true failure information is contained in
the first failing CRC read from top to bottom.

Tab. 25 Zm System B-Mode Test.

RC RC can cause CRC failures starting at Gross to subtle image If a DR on the BE
the DR SA memory checks or EP pers artifacts Board is the first fail-
Buffer checks on the BE Board. ure, the RC has a
RC will not cause CRC failures starting higher probability than
at SC Raster or VI Image the BE of causing the
failure; If the EP pers
BE BE can cause CRC failures starting at Buffer is the first fail-
the DR SA memory checks, EP Pers ure, the RC and BE
Buffer checks, or SC Raster have equal probability
of causing the failure
VI VI can cause CRC failure starting at

the VI Image check
False Fail- This test sometimes has a problem Press the freeze but-
ure with data transfer between BE and VI, ton before entering
which creates a false failure indication the test tools menu
and then repeat the
test. If BE to VI trans-
fer problem remains,
then it is a true failure.
Zm System BC-Mode Test 0
This test inputs a known set of data into the RC board and the system processes this data
from the RC through the DR, EP, FP, and SC sections of the BE and then to the VI board.
A CRC is a method of detecting a 1 bit mismatch. Once a CRC fails, this failure will con-
tinue through the remaining CRC checks. Thus the true failure information is contained in
the first failing CRC.

Tab. 26 Zm System BC-Mode Test

RC RC is likely to cause CRC failures start- Digital image noise
ing at the DR SA memory checks
RC can but is unlikely to cause CRC
failures starting at EP pers Buffer
checks, or FP FPGA Even Pers checks
RC will not cause CRC failures starting
at SC Raster or VI Image on the BE
Board.
BE BE can cause CRC failures starting at
the DR SA memory checks, EP Pers
Buffer checks, FP FPGA Even Pers
checks or SC Raster
VI VI can cause CRC failure starting at
the VI Image check
RTC Sequence Test (RC sequence, TR0 sequence, TR1 sequence, TR2
sequence) 0
RTC FPGA programs the TR boards and RXBF ASICs at high speed. The target regis-
ters and tables are first cleared. Patterns are stored in the RC index state machines
tables. A sequence is loaded that is expected to move the patterns out to the TXPG and
RXBF ASICs. The sequence is executed and the results verified.
Tab. 27 RTC Sequence Test and related failures

RC Failures in address range: 0xC000000 Typically will shut- TR interchange; if
to 0xC43FFFF down imaging, leav- failure follows TR
ing a screen with no with interchange then
TR0 Failures in address range: 0xC460000 ultrasound image TR board is source of
to 0xC47FFFF problem; if failure
TR1 Failures in address range: 0xC480000 does not move then
to 0xC49FFFF RC is source of prob-
lem
TR2 Failures in address range: 0xC4A0000
to 0xC4BFFFF
TI Failures in address range: 0xC4C0000
to 0xC4DFFFF


RC Since the RTC is the component used
to implement this test, a RTC failure is
more likely to create failures on
addresses that span multiple boards.
If the LED on RC board is off, this test
is expected to failure.
FE memory (includes RC memory, TR0 memory, TR1 memory, TR2 memory) 0
Standard memory test performed on all testable registers and memory spaces in the fron-
tend. Buses used are PCI bus between RM and BE; Febus between BE and RC, and
TCbus between RC and TR.
Tab. 28 FE memory (includes RC memory, TR0 memory, TR1 memory, TR2 memory)

RC Failures in address range: TR interchange; if fail-
0xC000000 to 0xC43FFFF; RXBF ure follows TR with
failures interchange then TR
board is source of
TR0 Failures in address range: problem; if failure does
0xC460000 to 0xC47FFFF; TXPG not move then RC is
failures source of problem
TR1 Failures in address range:
0xC480000 to 0xC49FFFF; TXPG
failures
TR2 Failures in address range:
0xC4A0000 to 0xC4BFFFF; TXPG
failures
RM/BE Since the RM and BE are used to
implement this test, a RM or BE fail-
ure is more likely to create failures on
addresses that span multiple boards.
Also the BE memory test is likely to
fail as well.
Damaged Damage connector pins
connector (shorted/open) can create multiple
pin TCbus related failures.

DC cal/DC cal check 0
Adjusts a system parameter, measures DC offset of all 192 channels and verifies that all
are within a set of test limits. The initial parameter adjustment is executed in the tune up
menu. The EM and individual board tests execute the a subsequent verification of limits.
Tab. 29 DC cal/DC cal check

TR Can cause a DC cal failure (more TR interchange; if fail-
likely than RC or TI) ure follows TR with
interchange then TR
RC Can cause a DC cal failure (less likely board is source of
than TR; more likely than TI) problem; if failure does
not move then RC is
source of problem
TI Can cause a DC cal failure (least
likely)
Probe Relay test 0
The probe relay test uses a test method similar to the receive test. Both use a stimulus
generated on the RC board and both route the signals for analysis through the TR to the
RC where the data is stored in the RXBF SRAM for analysis. The main difference is in the
routing of the stimulus on the TI board. For this test the stimulus is routed through the
relays on the TI board before being output to the TR boards.
Tab. 30 Probe Relay test

RC An RC board with a receive problem
can cause this test fail. Typically all
relays for probes A, B and C will fail
when the RC board is at fault.
TR A TR board with a receive problem can TR Swap
cause this test fail. Typically all relays
for probes A, B and C will fail when the
TR board is at fault.
TI A true relay fault on the TI board will
create a single fault or a fault with an
entire relay bank.

BE memory 0
tend. Buses used are PCI bus between RM and BE and local BE buses
Tab. 31 BE memory
Failing Failing EM board data Corresponding Image indication Troubleshooting

EM board presentation Suggestion
type
BE All failures should be Doppler problems, gross image
caused by BE problems
VI memory 0
tend. Buses used are PCI bus between RM and VI and local VI buses
Tab. 32 VI memory
Failing Failing EM board data presentation Corresponding Troubleshooting

EM board Image indication Suggestion
type
VI All failures should be caused by VI no image, incorrect
colors
Control DAC test 0
The RC board contains the Digital to Analog Converters (DAC) used to control five vari-
able voltages on the Antares system. The five voltages are VTGC, VFC, VMID, TXV0, and
TXV1. This test uses all possible digital inputs to the DACs in ascending order to produce
a ramp analog output. The test then analyzes the Slope (m), Offset (b), and RMS (stan-
dard error) for the resulting output (y=mx + b). For VTGC, VFC, and VMID these voltages
are routed from the RC to the TRs. From the TRs, these are routed to a separate mea-
surement signal path that returns to the RC, where a serial Analog to Digital converter
(ADC) is used to measure voltages. For TXV0 and TXV1, the output of the DACs are
routed to the PSA and the resulting TXV0 and TXV1 voltages are routed from the PSA
back to the TRs. The same measurement path to the ADC is used for these voltages as
for the other three voltages. Pass/Fail criteria is based on the calculated Slope, Offset,
and RMS values. A TXV0 and TXV1 trip point test is also part of this test group. Plots of
the data are also displayed as part of the test.

Tab. 33 Control DAC test

type
RC Since the actual DACs and associated cir- Always use either
cuitry is contained on the RC board, the RC the EM test group
board is a primary cause of failure for these or TR0 test group
tests. Especially slope, offset and gross to execute the
RMS failures. The plots that deviate signifi- Control DAC test.
cantly from a straight line are usually indica- The control DAC
tive of a RC fault. test in the RC test
group does not
test all of the Con-
trol DAC circuitry.
TXV PSM timer failures are caused by RC
only
TR The TR can cause a RMS failure on the
TXV0 and TXV1 voltages due to a marginal
part in the measurement path that routs the
voltages to the ADC on the RC board.
There are 3 TRs in the system and for this
test only 1 is needed to rout the voltages to
the RC board. When the EM or RC is test is
executed TR0 is used. When TR0 is tested
TR0 is used. When TR1 is tested TR1 is
used. When TR2 is tested TR2 is used. If
an RMS failure occurs due to a RC board
the failure would occur when testing all
three TRs. If a RMS failure occurs due to a
TR board then the failure would only occur
when testing that TR board. A TR board
caused RMS failure is unique to diagnostics
and does not affect imaging performance.
PSA PSA can cause TXV0 or TXV1 DAC test
failures or TXV0 or TXV1 TRIP failures
TI There is a high accuracy 2.5V reference on
the TI that is used to calibrate the ADC on
the RC used for the measurement. An
inaccurate 2.5V reference could affect the
measurements, but this is unlikely.

A2D Diag Test 0
The RC board has an ADC that is used to measure DC voltages in the system. For A2D
Diag test various system DC voltages on the RC board, the TR board, and the TI board
are routed via multiplexers to this ADC on the RC board. Some of these voltages are cre-
ated on the PSA and PSD directly, while others are created using regulators on individual
boards.
Tab. 34 A2D Diag Test

type
RC A defective RC could cause all measure-
ments to fail.
A defective RC could cause the voltages
created by RC regulators to fail.
TR A defective TR could cause those volt-
ages routed from the TR to fail.
TI A defective TI could cause the voltages
created by RC regulators to fail
A defective TI could cause those voltages
routed from the TR to fail
There is a high accuracy 2.5V reference
on the TI that is used to calibrate the ADC
on the RC used for the measurement. An
inaccurate 2.5V reference could affect
the measurements, but this is unlikely.



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Antares

Print No.: US03-101.840.01.02.02 English

Antares US03-101.840.01.02.02 Page 2 of 106 Siemens

Siemens US03-101.840.01.02.02 Page 3 of 106 Antares

1 _______ Troubleshooting Guide ___________________________________________ 6

Antares US03-101.840.01.02.02 Page 4 of 106 Siemens

Siemens US03-101.840.01.02.02 Page 5 of 106 Antares

NOTICE When an E Module board is replaced, an E Module test must be

Acronyms and Terms 0

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Basic Troubleshooting steps 0

Rules for Interchanging Boards/Modules 0

NOTICE The system license information will be corrupted if multiple

Siemens US03-101.840.01.02.02 Page 9 of 106 Antares

NOTE Interchanging two TR boards in the E Module for image testing or

System Serial Number

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Using the Flowchart 0

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Siemens US03-101.840.01.02.02 Page 15 of 106 Antares

Fig. 6: P10 Connector into J10 Connection

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Antares US03-101.840.01.02.02 Page 22 of 106 Siemens

Power Test Points 0

Tab. 1 PSAC Power Test Points

FRU TP Description Comment

Fig. 14: AC Tray (PSAC) Test Points and Transformer Fuses

Siemens US03-101.840.01.02.02 Page 23 of 106 Antares

FRU TP Description Comment

Tab. 3 PSD Power Test Points

FRU TP Description Comment

Antares US03-101.840.01.02.02 Page 24 of 106 Siemens

Fig. 15: PSA and PSD test points

Siemens US03-101.840.01.02.02 Page 25 of 106 Antares

FRU TP Description Comment

Fig. 16: I/O Board Test Points

Antares US03-101.840.01.02.02 Page 26 of 106 Siemens

FRU LEDs Description

Fig. 17: I/O Module LEDs

Siemens US03-101.840.01.02.02 Page 27 of 106 Antares

FRU LED Description

LEDs 1 and 2 will be flashing under normal operation.

Fig. 18: Control Panel LEDs

AC/DC Power Connections 0

Tab. 7 AC/DC Power Connections

FRU Connector Pin Signal

AC transformer J49/P49 1 48V PS AC MAIN N

Antares US03-101.840.01.02.02 Page 28 of 106 Siemens

FRU Connector Pin Signal

Isolation trans- J41 Monitor AC fused at F1 1 216 VAC, not switched

PSA Power J36/P36 A1 48V_PSA

PSD Power J37/P37 A1 48V_PSD

PS Fans J32/P32, J92/P92 1 PFANS1

1 _ Troubleshooting Guide _____________________________________ 6