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A
A
B Y
AB
Wired OR
A
Contents
` Introduction
` NMOS Logic
` Resistive Load
` Saturated Enhancement Load
` Linear Enhancement Load
` Depletion Load
` Some Gates
` Transient in NMOS Circuit
` Pseudo-NMOS
` CMOS Logic
` Static CMOS Logic Gates
NOT
NAND
NOR
Realization of More Complicated Gate Circuits
` Transmission Gates Family
NMOS Only Switch
CMOS
` Differential Cascode Voltage Switch Logic
` Rules of Thumb
` Summary
Introduction
` Resistive Load
W + Vdd
L VoL C Speed
RL
P RL Area
Vo
Vo
Vdd Vi
VOL
o
Vi
NMOS Logic
VOL
o VIL Vi
VIH
NMOS Logic
VOL
o VIL Vi
VIH
NMOS Logic
i1 = i 2
1
K1 ( VIH VT1 ) Vo Vo 2 2 = K 2 (Vdd Vo VT2 ) 2
2
2(Vdd VT 2 )
VIH = + VT1
3R + 1
NMOS Logic
` Power
VOL
o VIL Vdd Vi
VT VIH
NMOS Logic
Vo i i Vds2 i1 =
1
K1 (Vi VT1 ) 2
= 1 rds2 = 1 2
Vi Vi Vi i1 i1
= K1 ( Vi VT1 )
i 2 = K 2 ( Vgs2 VT 2 ) Vds2 Vds22 2 Vi
Vo K1 (Vi VT1 )
i 2 = 1 =
= K 2 ( VGG Vo VT 2 Vds2 ) Vi K 2 (VGG Vo VT 2 Vds2)
Vds2 VIL = f (Vo)
` VIH
M1 and M2 are in triode
+ Vdd
VGG
M2
Vo
Vi M1
NMOS Logic
` Depletion Load
` Ion implantation processing step is needed to create
depletion device, but overcome the disadvantages of
the previous circuit
+ Vdd
M2
Vo
Vi M1
NMOS Logic
` Depletion Load
` VTC
Vi = Low i1 = 0, M1 in cutoff i1 = i 2 = 0
K2
if M2 is in saturation then i 2 = (Vgs2 VT 2 ) 2 , Vgs2 = 0 i 2 > 0
2
` Therefore M2 is in triode Vo
Vdd
VOL
o VIL Vdd Vi
VT VIH
NMOS Logic
` Depletion Load
` VOL, VIL, VIH
K
K1 ( VOH VT1 ) VOL VOL 2 2 = 2 (0 VT 2 ) 2 VOL = ?
2
Vo K1 (Vgs1 VT1 )
= 1 = 1, i1 = i 2 VIL = ?
Vi K 2 (Vgs2 VT 2 Vds2)
K Vo
i1 = K1 ( VIH VT1 ) Vds1 Vds12 2 = i 2 = 2 (0 VT 2 ) 2 , = 1 VIH = ?
2 Vi
NMOS Logic
` Some Gates
` In all previous structures which different only in load,
the following Gates can be implemented. Note that the
NMOS Gates are not available as separately packaged
individual circuits, but they are used extensively in LSI
systems
NOR Gates
NAND Gates
NMOS Logic
` Some Gates
` NOR Gate
+ Vdd
RL A
Y
Y
A M1 B M2 B
NMOS Logic
` Some Gates
` NAND Gate
+ Vdd
RL
Y A
Y
A M2 B
B M1
NMOS Logic
` Some Gates
` In NOR Gate two transistors are paralleled but in
NAND Gate two transistors are in series. Because of
the need for increased area when adding NAND inputs,
NAND logic with more than 2 inputs is not
economically be attractive in NMOS. NOR logic is
preferable
` In NAND the M2 has body effect
` In NOR we need the less interconnection (this can be
shown from layout)
NMOS Logic
Vi M1 Cd sub1
` Pseudo-NMOS
` What makes a circuit fast?
I = C dV/dt -> tpd (C/I) DV
low capacitance
high current
small swing
` Logical effort is proportional to C/I
` PMOS are the enemy!
High capacitance for a given current
` Can we take the PMOS capacitance off the input?
` Various circuit families try to do this
NMOS Logic
` Pseudo-NMOS
` In the old days, NMOS processes had no PMOS
Instead, use pull-up transistor that is always ON
` In CMOS, use a PMOS that is always ON
Make PMOS about effective strength of pulldown
network
NMOS Logic
` Pseudo-NMOS
` Uses a p-type as a resistive pullup, n-type network for
pulldowns
+ Vdd
M2
Vo
Vi M1
NMOS Logic
` Pseudo-NMOS Characteristics
` Compared to CMOS, this
family has higher packing
density, since for n inputs only + Vdd
n+1 transistors are required
` The main disadvantages with
Pseudo-NMOS Gates is the
large static power dissipation
M2
that occurs whenever a pull-
down path is activated
Vo
` Has much smaller pullup
network than static gate
` Pulldown time is longer Vi M1
because pullup is fighting
NMOS Logic
Vi M1
NMOS Logic
2 2
Kp Y
VOL = K n (Vdd VT ) 1 1 2
Kn
A B C D
Assuming that VT = VTn = VTp
VOL 0 K p << K n
NMOS Logic
2.5
2.0 W/Lp = 4
1.5
Vout [V]
W/Lp = 2
1.0
W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]
NMOS Logic
` Pseudo-NMOS Gates
` Design for unit current on output Y
` PMOS fights NMOS inputs
f
NMOS Logic
` Pseudo-NMOS Power
` Pseudo-NMOS draws power whenever Y = 0
Called static power P = IVDD
A few mA / gate * 1M gates would be a problem
This is why NMOS went extinct!
` Use Pseudo-NMOS sparingly for wide NORs
` Turn off PMOS when not in use
en
Y
A B C
NMOS Logic
Out
M2
Vi Vo
M1
CMOS Logic
M3 M4
Y
B M2
A M1
CMOS Logic
B
Y
CMOS Logic
A
B Y
C
CMOS Logic
B C
CMOS Logic
B
CMOS Logic
B A
Y = AB + AB
B B
A A
CMOS Logic
B A
Y = AB + AB
B B
A A
CMOS Logic
M1 M2
A B
CMOS Logic
+ Vdd
A B Y
M3
0 0 Vdd
M4
Y = AB + AB
0 Vdd 0
M1 M2
Vdd 0 0
Vdd Vdd Vdd-Vth
A B
CMOS Logic
A B Y + Vdd
a
0 0 Vth M2
M3
A B b Y = AB + AB
0 Vdd Vdd-Vth
a
Vdd 0 Vdd M4
M1
b
Vdd Vdd 0 A
CMOS Logic
En = 1 Y = D
En = 0 Y = Hi Z + Vdd
En
D Y
Y
En
D
CMOS Logic
En
D
CMOS Logic
Vdd X
3.0
In In
Out
2.0
Voltage [V] x
1.0
0.0
0 0.5 1 1.5 2
Time [ns]
CMOS Logic
V dd
Vdd
Level Restorer Mr
B
M2
X
A Mn Out
M1
CMOS Logic
low VT transistors
In2 = 0V A = 2.5V
on
Out
off but
leaking
In1 = 2.5V B = 0V
sneak path
CMOS Logic
low VT transistors
In2 = 0V A = 2.5V
on
Out
off but
leaking
In1 = 2.5V B = 0V
sneak path
CMOS Logic
A Z
B
CMOS Logic
` CMOS
C
C
A Y
A Y
C C
CMOS Logic
B B B
A Z
A Z A Z
OR
B'
B' B'
A Z
BOOK ME
C
C
A Y
A Y
C C
CMOS Logic
VA
C
Vdd S I
P
Vy A Y
IN CL
D
t
C
CMOS Logic
N = sat C
0 t t Vy = V ICL = I N + I P
TP
P = sat
N = sat IP
t Vy = V t t Vy = Vdd V rP CL A Y
TP TN
P = triode
IN CL
N = off
t Vy = Vdd V t t Vy = Vdd rP CL
TN
P = triode C
CMOS Logic
VA (t) = Vddu(t) C
t
Vy(t) = Vdd 1 exp u(t) IP
TG A Y
IN CL
TG = R TG CL
R TG = rN rP C
CMOS Logic
R
2VAN
rN rP rN
N (Vdd VTN ) 2
2VAP
rP
P (Vdd VTP ) 2
R TG = rN rP
Y = A + AB = (A + A)(A + B) = A + B
A
A
B Y
AB
Wired OR
A
CMOS Logic
A S = 1
Y=
B S = 0
S
S
Y
B
S
CMOS Logic
F = (In1S + In 2 S) Vdd
GND
In1 S S In2
CMOS Logic
B
Y = AB
B
CMOS Logic
B
Y = AB + AB
B
CMOS Logic
2) Hold Q n = Q n-1
LD Q
LD
Q
D
LD
LD
LD
CMOS Logic
1) Load LD = 1 D Q=D
D=Q
2) Hold LD = 0
Q
Q
CMOS Logic
LD
Q
D
LD
Q
Weak Inverter
CMOS Logic
64447444
m
8
` Delay Optimization
` Delay of RC chain
n
n(n + 1)
t P = 0.69 C R e q k = 0.69C R e q
k =1 2
` TG Points to Remember
` Stored charge leaks away due to reverse-bias leakage
current
` Stored value is good for about 1 ms
` Value must be rewritten to be valid
` If not loaded every cycle, must ensure that latch is
loaded often enough to keep data valid
` Capacitance comes primarily from inverters gate logic
CMOS Logic
` TG Layout
CMOS Logic
` TG Properties
` Strong pull-up
` Strong pull-down
` May be difficult to design into a circuit (layout) because
of close proximity of N and P devices (design rule
separation)
` Always requires 2N transisitors for any N x TG design
` Many logic functions (multiplexers in particular) are
easily implemented using TG based designs
CMOS Logic
A S
A PT Network A
B F
F S L Y
B
B
S
A A
A Inverse PT F L Y
F S
B Network B
B
CMOS Logic
` CPL
B B
A
B
A
B
AND/NAND
CMOS Logic
` CPL Advantages
` Differential so complementary data inputs and outputs
are always available (so dont need extra inverters)
` Still static, since the output defining nodes are always
tied to Vdd or GND through a low resistance path
` Design is modular, all gates use the same topology,
only the inputs are permuted
` Simple XOR makes it attractive for structures like
adders
` Fast (assuming number of transistors in series is small)
CMOS Logic
` CPL Disadvantages
` Additional routing overhead for complementary signals
` Still have static power dissipation problems
` VOH is very weak! Then we need an inverter at the
output
CMOS Logic
Y Y
Inputs
f f
CMOS Logic
Y = AB Y =A+B
A
Series
A B B
CMOS Logic
A B C F 0 1
0 0 0 1 _ + _ + _ + _ +
C
0 0 1 0
0 1 0 0
_ + _ +
0 1 1 1 B
1 0 0 0
1 0 1 1 _ +
A
1 1 0 1
1 1 1 1
CMOS Logic
a b a b
_ + _
x x x x +
u u u
u
u = ax + bx
a b a b a b
x _ + _ + x _ +
u1 u2
u1 u2
CMOS Logic
0 1
0 1
C
_ + _ + _ + _ + _ + _ +
C
_ + _ +
B _ + _ +
B
_ +
A
_ +
A
CMOS Logic
` Rules of Thumb
` Step-up (alpha) ratio of 2.7 (e) produces minimum power-
delay product
` P vs. N (beta) ratio of 2 balances pull-up and pull-down
times and noise margins
` Approximately 75% of static logic are NAND stacks (limit
stack to 3-4, use ordering and tapering for speed)
` Glitches consume approximately 15% of overall chip power
` Crossover (short-circuit) current consumes ~ 10% of a
static chips total power (but is a function of input/output
slews, ie sizing)
Summary
` Introduction
` Dynamic CMOS Logic
` CMOS Domino Logic
` CD Domino Logic
` Dynamic CVSL
` Sample-Set Differential Logic (SSDL)
` Summary
Introduction
Y
Dynamic CMOS Logic
` The Foot
` What if pulldown network is ON during precharge?
` Use series evaluation transistor to prevent fight
precharge transistor
Y
A
foot
Dynamic CMOS Logic
Mp
1 L
Me
Precharge (Clk = 0)
Evaluate (Clk = 1)
Dynamic CMOS Logic
` Canonical Forms
Dynamic CMOS Logic
` Leakage Sources
` Subthreshold conduction
` Transistors cant abruptly turn
ON or OFF
` Reverse-biased PN junction 109
tox
` Leakage Sources
` Output settles to an intermediate voltage determined by a resistive
divider of the pull-up and pull-down networks
` Once the output drops below the switching threshold of the fan-out
logic gate, the output is interpreted as a low voltage
CLK
2.5
V o lta g e (V )
1.5 Out
0.5
-0.5
0 20 40
Time (ms)
Dynamic CMOS Logic
` Leakage Sources
` Subthreshold leakage is dominant in modern transistors
CLK
VOut Evaluate
e
Precharge
Leakage sources
Dynamic CMOS Logic
Mp M kp
Me
Dynamic CMOS Logic
` Charge Sharing
` Charge stored originally on CY is redistributed (shared) over CX
leading to static power consumption by downstream gates and
possible circuit malfunction
` When Vout = - Vdd (CX / (CX + CY )) the drop in Vout is large
enough to be below the switching threshold of the gate it drives
causing a malfunction
Y Y
A x CY Charge sharing noise
B=0 Cx x
CY
V x =V Y = V dd
C x + CY
Dynamic CMOS Logic
(
Vout = Vdd ( Ca + Cc ) Ca + Cc + C y
)
= 2.5V ( 30 ( 30 + 50 ) ) = 0.94V
Load
CLK inverter
y=A B C
A A Cy =50fF
a
Ca =15fF b
B B B Cb =15fF
B
c d
Cc =15fF C C Cd =10fF
CLK
Dynamic CMOS Logic
` Backgate Coupling
` Susceptible to crosstalk due to
High impedance of the output node
Capacitive coupling
Out2 capacitively couples with Out1 through the gate-source and gate-
drain capacitances of M4
CLK Mp M6 M5
Out1 =1
Out2 =0
A=0 M1 M4
CL1 CL2
B=0 M2 M3 In
CLK Me
` Backgate Coupling
` Capacitive coupling means Out1 drops significantly so Out2
doesnt go all the way to ground
3
Due to clk feedthrough
2
Voltage
Out1
Due to backgate
1
Clk
0
In Out2
-1
0 2 4 6
Time, ns
Dynamic CMOS Logic
` Clock Feedthrough
` A special case of capacitive
coupling between the clock Mp
input of the precharge transistor
and the dynamic output node
due to the gate to drain L
capacitance
` So voltage of Out can rise above
Vdd. The fast rising (and falling Me
edges) of the clock couple to
Out
Dynamic CMOS Logic
2.5
1.5
Voltage
In &
0.5 Clk
Out
-0.5
0 0.5 Time, ns 1
Clock feedthrough
Dynamic CMOS Logic
` Other Effects
` Capacitive coupling
` Substrate coupling
` Minority charge injection
` Supply noise (Ground bounce)
` Floating output nodes
Dynamic CMOS Logic
0
s
0
Dynamic CMOS Logic
` Advantages:
` For n inputs, dynamic logic requires
n+2 transistors
` have small area, high speed and CLK PCLK
compact layouts
` Disadvantages:
` Circuit operation is more complex NMOS
due to the required clock Logic
` The inputs can only change during Circuit
the precharge phase and must be
stable during the evaluate portion of
the cycle N CLK
` Need Monotonicity
can not be cascaded
Dynamic CMOS Logic
` Monotonicity
` Dynamic gates require monotonically rising inputs
during evaluation
violates monotonicity
during evaluation
A
` Monotonicity Woes
` Dynamic gates produce monotonically falling outputs during
evaluation
` Illegal for one dynamic gate to drive another!
A1 =
X
X monotonically falls during evaluation
Y
Y should rise but cannot
Dynamic CMOS Logic
` Cascading V
Clk
In
VTn
Out1
V
Out2
t
Only 0 1 transitions allowed at inputs!
Dynamic CMOS Logic
` Cascading
` Input going from high to low during evaluation
a is 5V when precharge b = 5V, c = 5V
During evaluation:
Wanted: b 0V, c 5V
But, b takes some time to drop to 0V
Consequently, c may fall to some unknown value
` Solution
` NP-CMOS b c
` NORA Logic a
` Domino logic
Dynamic CMOS Logic
` NP-CMOS
` Only 0 1 transitions allowed at inputs of PDN
` Only 1 0 transitions allowed at inputs of PUN
Mp Clk Me
Clk
1 1
Out1
1 0
In1 In4 PUN
In2 PDN In5
0 0
In3 0 1
Out2
Mp (to PDN)
Clk Me Clk
Dynamic CMOS Logic
` NORA Logic
` WARNING: Very sensitive to noise!
Mp Clk Me
Clk
1 1
Out1
1 0
In1 In4 PUN
In2 PDN In5
0 0
In3 0 1
Out2
Mp (to PDN)
Clk Me Clk
to other to other
PDNs PUNs
Dynamic CMOS Logic
` An example
Dynamic CMOS Logic
Out
In1
In2
In3
In4
GND
Dynamic CMOS Logic
` Power Consumption
` Power only dissipated when previous Out = 0
1 L
e
Dynamic CMOS Logic
` Power Consumption
` Dynamic Power Consumption is Data Dependent
Assume signal probabilities (Dynamic 2-input NOR Gate)
PA=1 = 1/2
PB=1 = 1/2
A B Out
Then transition probability
P10 = Pout=0 = 0 0 1
0 1 0
1 0 0
1 1 0
` Rules of Thumb
` Dynamic logic is best for wide OR/NOR structure (e.g. bit-
lines), providing 50% delay improvement over static CMOS
` Dynamic logic consumes 2x power due to its phase activity
(unconditional pre-charging), not counting clock power
Dynamic CMOS Logic
` Notes
` No need to implement the complement of the function,
leading to smaller area
` We can avoid the long PMOS chains
` Handle the charge sharing problem and floating output
nodes
` Input transistors should not change from on to off
during evaluation
CMOS Domino Logic
` pc = 1 and ev = 2
pc = 1 ev = 2
cycle
pc
V W X Y 1
n- network
1 2
ev 2
precharge evaluate
pc = 2 ev = 1
cycle
2
precharge
precharge
evaluate evaluate
input latched output latched
here here
CMOS Domino Logic
` Why Domino?
` Like falling dominos!
CMOS Domino Logic
domino AND
W
W X Y Z X
A
Y
B C
Z
dynamic static
NAND inverter
A W X A X
H Y =
B H Z B Z
C C
CMOS Domino Logic
` Domino Optimizations
` Each domino gate triggers next one, like a string of dominos toppling
over
` Gates evaluate sequentially but precharge in parallel Thus evaluation
is more critical than precharge
` HI-skewed static stages can perform logic
` Static inverter can be optimized to match fan-out
S0 S1 S2 S3
D0 D1 D2 D3
Y
H
S4 S5 S6 S7
D4 D5 D6 D7
CMOS Domino Logic
` Leakage
` Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0)
Dynamic value will leak away over time
Formerly miliseconds, now nanoseconds!
` Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
weak keeper
1 k
X
H Y
A 2
2
CMOS Domino Logic
` Noise Sensitivity
` Dynamic gates are very sensitive to noise
Inputs: VIH Vtn
Outputs: floating output susceptible noise
` Noise sources
Capacitive crosstalk
Charge sharing
Power supply noise
Feedthrough noise
And !
CMOS Domino Logic
` Example
` During precharge, x, y, z = 1, x, y = 0
` During evaluation, x = 0 when a = b = 1
` Therefore, z = a b c d
x y z
x y
a
b c d
CMOS Domino Logic
` Advantages:
` Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS
requires 2n)
` Single clock can be used to precharge and evaluate all stages at the
same time
` It is attractive for high-speed circuits
` 1.5 2x faster than static CMOS
` Widely used in high-performance microprocessors
` Disadvantages:
` Each logic block must incorporate a separate inverter
` Each block performs only non-inverting logic
` Monotonicity
` Leakage
` Charge sharing
` Noise
CMOS Domino Logic
` Example AND/NAND
` Given A_h, A_l, B_h, B_l
` Compute Y_h = A * B, Y_l = ~(A * B)
` Pulldown networks are conduction complements
Y_l Y_h
= A*B A_h = A*B
A_l B_l B_h
CMOS Domino Logic
` Example XOR/XNOR
` Sometimes possible to share transistors
Y_l Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h
CMOS Domino Logic
` Rules of Thumb
` Typical domino keepers have W/L = 5-20% of effective width
of evaluate tree
` Typical domino output buffers have a beta ratio of ~ 6:1 to
push the switch point higher for fast rise-time
CD Domino Logic
Mpre
Out = a+b
a b
` Advantages
` Uses single-rail circuits, rather than dual-rail for
standard domino
` Provides both inverting and non-inverting functions
` High-speed, large fan-in NOR and OR circuits
CD Domino Logic
` Delay Matching
` CD domino requires delay matching between the
slowest dynamic gate at a level and a delay element
` A 20% margin is typically added to the delay of the
fixed delay element to account for PVT variations
` Thus, 20% of the speed gain possible with CD domino
is not realized
` Average speed gain of (60+20)% is theoretically
possible
` Use digitally programmable delay elements
(PDEs) to reduce the margin and attain a speed
improvement without affecting the reliability in
the presence of variations
CD Domino Logic
` Clocking Scheme
` The circuits are fully levelized
` The delay element on each level is tuned to the
slowest gate at its level, plus a 20% margin
(other. gates) (other. gates) (other. gates)
. . .
dynamic dynamic dynamic
gate gate gate
F F
In{ } In
C NMOS C
Logic Array
Sample-Set Differential Logic (SSDL)
F F
C C
In{ } In
NMOS
Logic Array
Summary