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CLOCK CLOCK
CLOCL
BUFFER
CKE
De
co
der 2 MX16
CELL ARRAY
CS#
COMMAND CONTROL (BANK #A)
RAS#
CAS# DECODER SIGNAL
GENERATOR Column Decoder
WE#
UDQM
LDQM
DQ0
COLUMN
Buffer |
COUNTER
DQ15
MODE
REGISTER De
A0 co
ADDRESS der 2 MX16
~ BUFFER CELL ARRAY
A11
(BANK #B)
BA0
BA1
Column Decoder
REFRESH
COUNTER
De
co
der 2 MX16
CELL ARRAY
(BANK #C)
Column Decoder
De
co
der 2 MX16
CELL ARRAY
(BANK #D)
Column Decoder
Pin Descriptions
Table 1. Pin Details of EM639165
Command State CKEn-1 CKEn DQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE#
BankActivate Idle(3) H X X V Row address L L H H
BankPrecharge Any H X X V L X L L H L
PrechargeAll Any H X X X H X L L H L
Write Active(3) H X X V L Column L H L L
address
Write and AutoPrecharge Active(3) H X X V H (A0 ~ A8) L H L L
Read Active(3) H X X V L Column L H L H
address
Read and Autoprecharge Active(3) H X X V H (A0 ~ A8) L H L H
Mode Register Set Idle H X X OP code L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active(4) H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
AutoRefresh Idle H H X X X X L L L H
SelfRefresh Entry Idle H L X X X X L L L H
SelfRefresh Exit Idle H X X X
L H X X X X
(SelfRefresh) L H H H
Clock Suspend Mode Entry Active H L X X X X X X X X
Power Down Mode Entry Any(5) H X X X
H L X X X X
L H H H
Clock Suspend Mode Exit Active L H X X X X X X X X
Power Down Mode Exit Any L H X X X X H X X X
(PowerDown) L H H H
Data Write/Output Enable Active H X L X X X X X X X
Data Mask/Output Disable Active H X H X X X X X X X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
CLK ..............
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
The BankPrecharge command precharges the bank disignated by BA signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
3 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Dont care, A10 = "H", A0-A9 and A11 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.
4 Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
CLK
COMMAND
READ A NOP NOP NOP NOP NOP NOP NOP NOP
CLK
COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP
CAS# latency=3
tCK3, DQ's DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
DQM
COMMAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP
CLK
1 Clk Interval
DQM
CAS# latency=2
tCK2, DQ's DIN A0 DIN A1 DIN A2 DIN A3
: "H" or "L"
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
DQM
COMMAND NOP NOP READ A NOP NOP WRITE B NOP NOP NOP
CAS# latency=2
tCK2, DQ's DIN B0 DIN B1 DIN B2 DIN B3
: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND READ A NOP NOP NOP Precharge NOP NOP Activate NOP
CAS# latency=2
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK2, DQ's
CAS# latency=3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK3, DQ's
CLK
COM M AND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP
The first data element and the write Extra data is masked.
are registered on the same clock edge.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COM MAND NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP
1 Clk Interval
CLK
COMMAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP
CAS# latency=2
DIN A0 don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3
tCK2, DQ's
CAS# latency=3
tCK3, DQ's DIN A0 don't care don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
Input data for the write is masked.
data contention.
CLK
DQM
tRP
BANK
ADDRESS BANK (S) ROW
COL n
tWR
DQ DIN DIN
n n+ 1
: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",
A0-A8 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND Bank A NOP NOP Write A NOP NOP NOP NOP NOP
Activate AutoPrecharge
tDAL
CAS# latency=2
tCK2, DQ's
DIN A0 DIN A1
*
tDAL
CAS# latency=3
tCK3, DQ's
DIN A0 DIN A1
*
tDAL= tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CLK
tCK2
CKE
Clock min.
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
tRP
DQ Hi-Z
Function RFU* RFU* WBL Test Mode CAS Latency BT Burst Length
*Note: RFU (Reserved for future use) should stay 0 during MRS cycle.
2 words:
8 words:
9 No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
CLK
COMMAND READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP
CAS# latency=3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK3, DQ's
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP
CAS# latency= 2, 3
DIN A0 DIN A1 DIN A2 don't care
DQ's
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = Dont care, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system.
-6/7
Symbol A.C. Parameter Min. Max. Unit Note
tRC Row cycle time
60/63
(same bank)
tRCD RAS# to CAS# delay
18/20
(same bank)
tRP Precharge to refresh/row activate command
(same bank) 20/20 ns
tRRD Row activate to row activate delay
12/14
(different banks)
tRAS Row activate to precharge time
42/42 100000
(same bank)
tWR Write recovery time 2
CLK
tCCD CAS# to CAS# Delay time 1
tCK2 CL* = 2 9/10
Clock cycle time 9
tCK3 CL* = 3 6/7
tCH Clock high time 2.5/2.5 10
tCL Clock low time 2.5/2.5 10
tAC2 Access time from CLK CL* = 2 7/7
10
tAC3 (positive edge) CL* = 3 5/5.4 ns
tOH Data output hold time 2.5/2.7 9
tLZ Data output low impedance 1
tHZ Data output high impedance 5/5.4 8
tIS Data/Address/Control Input set-up time 1.5/1.5 10
tIH Data/Address/Control Input hold time 1 10
tPDE Power Down Exit set-up time 1.5/1.5
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
LVTTL Interface
Reference Level of Output Signals 1.4V / 1.4V
Output Load Reference to the Under Output Load (B)
Input Signal Levels 2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals 1ns
Reference Level of Input Signals 1.4V
1.4V
3.3V
1.2k 50
Z0= 50
Output Output
30pF 30pF
870
LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a
fixed slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.
9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200seconds minimum is required. Then, it is recommended that DQM is
held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
Timing Waveforms
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10 RAx RBx RAy RAz RBy
t IS
A0-A9,A11 RBx CAx RBx CBx RAy CAy RAz RBy
DQM
tRCD tDAL t IS
tRC tIH t WR tRP tRRD
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate Write with Activate Write with Activate Write Precharge Activate Activate
Command AutoPrecharge Command AutoPrecharge Command Command Command Command Command
Bank A Command Bank B Command Bank A Bank A Bank A Bank A Bank B
Bank A Bank B
CLK
t IS t IH tIH
CS#
RAS#
CAS#
WE#
BA0,1
t IH
A10 RAx RBx RAy
t IS
A0-A9,A11 RAx CAx RBx CBx RAy
tRRD
tRAS
DQM tRC
tAC2 tAC2 t HZ tRP
Hi-Z tRCD t LZ
DQ Ax0 Ax1 Bx0 Bx1
t OH t HZ
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
tRC tRC
DQM tRP
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High level Minimum of 2 Refresh Cycles are required
is reauired
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,A11
DQM
tRP tRC
DQ Hi-Z
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
*Note 2
*Note 1 *Note 4 tRC(min) *Note 7
RAS#
*Note 8
*Note 8
CAS#
BA0,1
A0-A9,A11
WE#
DQM
Hi-Z Hi-Z
DQ
T0 T 1 T2 T3 T4 T5 T6 T T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22
7
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
tHZ
DQ Hi-Z Ax3
Ax0 Ax1 Ax2
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
tHZ
DQHi-Z Ax0 Ax1 Ax3
Ax2
Clock Suspend
Activate Read Clock Suspend 2 Cycles Clock Suspend
Command Command 1 Cycle 3 Cycles
Bank A Bank A
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
DQM
tHZ
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3
Clock Suspend
Activate Read Clock Suspend Clock Suspend 3 Cycles
Command Command 1 Cycle 2 Cycles
Bank A Bank A
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
DQ
Hi-Z DAx0 DAx1
DAx2 DAx3
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2
2
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
DQ
Hi-Z DAx0 DAx2 DAx3
DAx1
Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2 tPDE
t IS
CKE
Valid
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
RAx CAx
A0~A9,A11
DQM
tHZ
Hi-Z
Ax0 Ax1 Ax2 Ax3
DQ
ACTIVE PRECHARGE
STANDBY STANDBY
Activate Read Clock Mask Clock Mask Precharge Power Down
Command Command Start End Command Mode Exit
Bank A Bank A Bank A
Power Down Power Down Any
Mode Entry Mode Exit Command
Power Down
Mode Entry
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ Aw0 Aw1 Aw2 Aw3Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z Az0
DQ Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
DQHi-Z DBw0DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
tRCD
DQM tAC1 tRP
Hi-Z
DQ
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 By2
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3
DQ Ax4 Ax5 Ax6 Ax7 By0 By1
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
Hi-Z
DQ Bx6 Bx7 Ax7 By0
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKEHigh
CS#
RAS#
CAS#
WE#
BA0,1
Hi-Z
DQ DAx0 DAx1 DAx2
DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
Hi-Z
DQ DAx0 DAx1 DAx2 DAx3 DAx4DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1DAy2 DAy3 DAy4
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
Hi-Z
DQ DAx0 DAx1 DAx2 DAx3DAx4 DAx5 DAx6 DAx7 DBx0 DBx1DBx2 DBx3 DBx4 DBx5 DBx6 DBx7DAy0 DAy1 DAy2 DAy3
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 DAy0DAy1 DAy3 Az0 Az1
Az3
Activate Write The Write Data Read The Read Data Precharge
Command Command is Masked with a Command is Masked with a Command
Bank A Bank A Zero Clock Bank A Two Clock Bank B
Read Latency Latency
Command
Bank A
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3
Activate Read Write The Write Data Read The Read Data
Command Command Command is Masked with a Command is Masked with a
Bank A Bank A Bank A Zero Clock Bank A Two Clock
Latency Latency
Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
DQM
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3
Activate Read Write The Write Data Read The Read Data
Command Command Command is Masked with a Command is Masked with a
Bank A Bank A Bank A Zero Clock Bank A Two Clock
Latency Latency
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
tRCD tAC1
DQM
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3
Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
tRCD tAC2
DQM
DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3
Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx RBx
A10
tRCD tAC3
DQM
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3
Precharge
Activate Read Read Read Read Read Prechaerge Command
Command Command Command Command Command CommandCommand Bank A
Bank A Bank A Bank B Bank B Bank B Bank A Bank B
Activate
Command
Bank B
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
CBy CBz
RAx CAx RBw CBw CBx CAy
A0~A9,A11
tRP
tRCD tWR tRP
DQM
tRRD
Hi-Z
DQ DAx0 DBz2
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz3
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQ Hi-Z DAx0DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1DBy0 DBy1DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By3 Bz2
Ax0 By2 Bz0 Bz1 Bz3
Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2
Activate Read Activate Read with Read with Activate Read with Activate Read with
Command Command Command Auto Precharge Auto Precharge Command Auto Precharge Command Auto Precharge
Bank A Bank A Bank B Command Command Bank B Command Bank A Command
Bank B Bank A Bank B Bank A
Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3
Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A0~A9,A11 RAx CAx RBx CBx CAy RBy CBy RAz CAz
DQM
Hi-Z
DQ DAx0 DAx1 DAx2 DAx3
DBx0 DBx1DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Activate Write Activate Write with Write with Activate Write with Activate Write with
Command Command Command Auto Precharge Auto Precharge Command Auto Precharge Command Auto Precharge
Bank A Bank A Bank B Command Command Bank B Command Bank A Command
Bank B Bank A Bank B Bank A
Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
`
BA0,1
DQM
Hi-Z
DQ DAx0 DAx1 DAx2 DAx3DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2DBy3
Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
A10 RBx RBy
tRRD tRP
DQM
Hi-Z
DQ Ax Ax+1 Ax+2 Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7
Ax-2 Ax-1 Ax Ax+1 Bx
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
tRP
DQM
Hi-Z
DQ Ax Ax+1 Ax+2Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5 Bx+6
Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
tRP
DQM
DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Activate Read Activate Read Full Page burst operation does not Precharge Activate
Command Command Command Command terminate when the burst length is Command Command
Bank A Bank A Bank B Bank B satisfied; the burst counter Bank B Bank B
The burst counter wraps increments and continues
from the highest order bursting beginning with the Burst Stop
page address back to zero starting address. Command
during this time interval
Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Hi-Z
DQ DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+ 1DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6
Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
Data is ignored
DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+ 1
DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
A10 RAx
LDQM
UDQM
Activate Read Upper 3 Bytes Lower Byte Write Upper 3 Bytes Read Lower Byte Lower Byte
Command Commandare masked is masked Command are masked Command is masked is masked
Bank A Bank A Bank A Bank A
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A
CS#
RAS#
CAS#
WE#
BA0,1
RBu RAu RBv RAv RBw RAw RBx RAx RBy RAy RBz RAz
A10
RBu CBu RAu CAu RBv CBv RAv CAv RBw CBw RAw CAw RBx CBx RAx CAx RBy CBy RAy CAy RBz CBz RAz
A0~A9,A11
tRP tRP tRP tRP tRP tRP tRP tRP tRP tRP
DQM
DQ Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0
Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate
Command Command Command Command Command Command Command Command Command Command Command Command
Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A
Read Read Read Read Read Read Read Read Read Read Read
Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B
with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A0~A9,A11 RAx RBx CAx CBx CAy CBy CAz CBz RBw
tRP
DQM
tRRD tRCD
DQ
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A0~A9,A11 RAx RBx CAx CBx CAy CBy CAz CBz RBw
tWR tRP
DQM
tRRD tRCD
DQ DAx0 DBx0DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1
DBz2
Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
CAy
RAx CAx RAy RAz CAz
A0~A9,A11
tRP
tWR tRP Precharge
Termination of
a Read Burst.
DQM
DQ DAz6 DAz7
DAx0 DAx1
DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz0 DAz1 DAz2
DAz3 DAz4 DAz5
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
DQM
DQ DAx0 DAx1
DAx2 DAx3 Ay0 Ay1 Ay2 Az0 Az1 Az2
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
Write Data
is masked Precharge Termination
of a Write Burst
54 28
0.254
HE
E
L1
1 27
D
A1 A2
C
A
S B e L L1
y