TESTING OF DIGITAL VLSI CIRCUITS

Course Code : 12EC378

Class applicable for: 8th Semester
Credits: 3 Credits
Name of the Faculty: Nagamani A N
Lectures per Week: 3 hours per week
Tutorials per Week: NIL
Core/Elective: Elective
Course Pre- Logic Design, VLSI Design
requisites:
Course Description: As VLSI design continues to grow in its complexity, VLSI testing and design-
for-testability is becoming more and more important issues. This course will
cover VLSI testing techniques such as VLSI fault modelling (struck-at-fault0,
Automatic test generation, memory testing, design for testability (DFT), etc.
VLSI scan testing and built-in self-test (BIST) will also be covered. Students
will learn various VLSI testing strategies and how to design a testable VLSI
circuit.

Syllabus: UNIT-I 7 Hours

INTRODUCTION TO TESTING AND
FAULT MODELING
Defects, Errors, Faults Functional Versus Structural Testing, Levels of Fault
Models, A Glossary of Fault Models, Single Stuck-at Fault, Fault
Equivalence, Equivalence of Single Stuck-at Faults
Fault Collapsing, Fault Dominance and Checkpoint Theorem.

UNIT II 10 Hours
COMBINATIONAL CIRCUIT TEST GENERATION
Algorithms and Representations, Structural vs. Functional Test, Definition of
Automatic Test-Pattern Generator, Algorithm Completeness, ATPG Algebras,
Redundancy Identification (RID), Definitions. Significant Combinational ATPG
Algorithms D-Calculus and D-Algorithm, PODEM, FAN. Introduction to
Sequential circuit testing

UNIT III 8 hours

MEMORY TESTING
Memory density and defect trends, Memory fault models, March Test,
Memory Testing , functional RAM Testing, Cache RAM Testing, Functional
ROM Testing

UNIT -IV 7 hours

DESIGN FOR TESTABILITY : DIGITAL DFT AND SCAN DESIGN

Ad-Hoc DFT Methods, Scan Design, Scan Design Rules, Tests for Scan
Circuits, Multiple Scan Registers, Overheads of Scan Design, Physical
Design and Timing Verification of Scan, Partial-Scan Design,

UNIT V 7 Hours
BUILT-IN SELF-TEST
Random Logic BIST, Definitions BIST Process, BIST Pattern Generation
BIST Response Compaction, Built-in Logic Block Observers, Device Level
BIST, Test Point Insertion,
Text Books /
References: TEXT BOOK:
M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits", Kluwer Academic Publishers,
2000.

REFERENCE BOOK:
M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing
and Testable Design", IEEE
Press, 1990.

Course / Learning On successful completion of this Course, the students would

Outcomes: 1. Be familiar with knowledge and testing in VLSI testing and
Validation.
2. Be familiar with VLSI fault modeling, testing strategies for
combinational/sequential circuits, memory..
3. Be familiar with delay testing, design for testability(DFT), built-in self-
test(BIST) and boundary scan.

Assessment Tools / Two Tests

Methodology: Assignments / Quiz
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