Beyond CMOS computing

4. Tunneling FETs

Dmitri Nikonov
Thanks to Uygar Avci
Dmitri.e.nikonov@intel.com

1 Nikonov 4. TFET
Outline

Band-to-band tunneling
Tunneling FET operation principles
Experimental realizations
Atomistic simulations
Homojunction TFET
Heterojunction TFET

2 Nikonov 4. TFET
 Motivation
Need lower VDD to lower Switching Energy (~C.VDD2)
When CMOS supply voltage is scaled <0.5V, performance suffers significantly

TFET offers sharper turn-on devices compared to MOSFET

Better performance for ultra low-power applications

For the same low switching

Atomistic Model Prediction energy and leakage power, TFET
outperforms CMOS

InAs CMOS@0.3V
TFET
Low-power Switching
0.3 fJ
MOSFET 8x Energy
Leakage
0.5 nW
Power

TFET
Lg=20nm

(VLSI 2011)

3 Nikonov 4. TFET
 MOSFET
Vg Gate
Source Drain Subthreshold slope in
Vd MOSFETs is limited by the tail
N i N of the Fermi distribution
1
eV eV
f exp
1 exp
kT kT
To the thermodynamic limit
value
~ 1 / Subthreshold
Slope (mV/dec)
d log( I ) e
60mV / decade
1
SS
dVg kT

Typically 80-120mV/dec at low

current depends on
electrostatic control.
4
4 Nikonov 4. TFET
 Tunneling Field-Effect Transistor

Vg Gate
Source Drain Tunnel FETs operate by
Vd tunneling through the S/D
P+ i-InAs N barrier rather than
diffusion over the barrier
Two required conditions:
Thin enough barrier over
a large enough area for
effective (high current)
tunneling.
Sufficient density of
states on both the
Tunneli transmission and
receiving sides to
ng provide energetic
barriers locations for the carriers.
Courtsey M. Luisier (Purdue)
M. Luisier and G. Klimeck, EDL, 2009
5
5 Nikonov 4. TFET
 Cartoon of density of States
* per 1 spin state

Fermi level

kF

6 2 width of band: 2m density of states:

Ew narrow band N max it is larger for a
ma heavy mass a 3 2
heavy mass
Bands parabolic close to edge = effective mass approximation
mk F a=0.3nm
N m=mass ~ 0.2me=0.2*9.1*10-31kg
2 2 2 kF=Fermi momentum~3/nm
N=4*1046/(J*m3)=0.07/(eV*atom)
6 Nikonov 4. TFET
Quantum Tunneling

Probability of tunneling
http://en.wikipedia.org/wiki/Quantum_tunneling
w=width=1nm
2 w 2 mbU b mb=mass= 0.2* 9.1*10-31kg
T exp Ub=height=0.8eV
T~0.016

Heavier mass smaller tunneling probability

Tunneling current density

http://arxiv.org/abs/0711.1461

A~0.3m
2 e V
2
N= 4*1046 /(J*m3)
J TU b2 N l N r a 4
J/V=1.2*1014 S/m2

V / J RA 0.5 m 2
7 Nikonov 4. TFET
TFET Device and Operation
MOSFET-like structure, but with opposite type
doping in Source and Drain
Can use different device geometries like MOSFET

Over
the
Vg Barrier
MOSFET

Through
the
Barrier
TFET Vg

8 Nikonov 4. TFET
Device Operation

S S

D D

S S

D D

M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)

9 Nikonov 4. TFET
Device Operation

S S

D D

S S

D D

M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)

10 Nikonov 4. TFET
Device Operation

S S

D D

S S

D D

M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)

11 Nikonov 4. TFET
Device Operation

S S

D D

S S

D D

M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)

12 Nikonov 4. TFET
Homojunction vs. Heterojunction
Heterojunction can achieve higher tunneling current

Heterojunction
Homojunction

Material- A Material- B

13 Nikonov 4. TFET
Si TFET (UC Berkeley)
Show of highest possible current with Si with sub-60 mV/dec
SS
Best published Si or Ge TFET
Shows high-angle to gate interface tunneling increases current

VLSI 2010

14 Nikonov 4. TFET
SiGe TFET (CEA-LETI)
Show of high current with no sub-60 mV/dec SS
Possibly not a TFET but metal contact to channel. No sub-
60mV/dec expected.

VLSI 2012

15 Nikonov 4. TFET
Vertical III-V (Intel, Penn-State, Notre Dame)
Intel: Showed sub-60mV/dec SS
Penn-State: High-current capability of heterojunction TFET
Notre Dame: High-current with tunneling perpendicular to gate
interface

Intel (IEDM 2011) Penn-State (VLSI 2012) Notre Dame (EDL-2012)

16 Nikonov 4. TFET
Intel TFET Demonstration !

Heterojunction InGaAs TFET. Side-

gated. Better electrostatic control.
The only semiconductor TFET (there
was one carbon-nanotube before) with
<60mV/decade. Albeit at small Vds,
over a small Vg range.
G. Dewey et al., IEDM, 2011.

17 Nikonov 4. TFET
Other Experimental TFET
Stanford (2006): CNT
Good SS at very low current (pA)

Stanford (2008): Strained-Ge Double-gate

Either high-current or good SS, not together

Hitachi (2010): Novel TFET device idea (Si)

Peking Uni. (2011): Novel TFET device idea (Si)

Hokkaido Uni. (2012): InAs nanowire on Si

he-j TFET
Very good SS ~21mV dec. with low Idsat
No clear understanding of how this was achieved

18 Nikonov 4. TFET
Most Experimental Still Poor Performance

Still MUCH lower drive

32nm MOS
@ Vds = 0.8V currents than
conventional MOS
Require band-gap
engineering with hetero-
junction d layers[1]
Sub-threshold slope still
poor

S. Mookerjea et al., IEDM 09 [1] K. Jeon, et al., VLSI (11.4.1.-1) 2010

[2] W. Choi et al., IEEE-EDL vol.28, no.8, p.743 (2007)
[3] F. Mayer et al., IEDM Tech Dig., p.163 (2008)
[4] T. Krishnamohan et al., IEDM Tech Dig., p.947
(2008)
19 Nikonov 4. TFET
TFET Modeling Approaches
For accurate prediction, quantum solution with band-structure
calculation is chosen

Analytic modeling using Atomistic quantum

Kanes model modeling

Fast computation Very slow computation

Requires calibration to Requires input of tight-binding

electrical data for reliable parameters for bandstructure
prediction. calculation.

Suitable large geometries Suitable for small geometry

Used in this study

20 Nikonov 4. TFET
Atomistic Quantum Modeling
3D ballistic quantum transport and atomistic full-band tight-
binding band structure calculation
No fitting to experimental electrical characteristics. The only input
parameters are bandstructure of the material and geometry.

Atomistic structure Density of states spectrum

E

Ec

Ev
x
OMEN

21 Nikonov 4. TFET
 TFET Sub-threshold Slope
Tunneling current increases sharply at the onset of Source
Valence Band and Channel Conduction Band overlap

TFET
1.E-04

S 1.E-05
ID (A/um)

1.E-06

Ch 1.E-07

1.E-08
D VDS=0.4V
1.E-09
0.0 0.1 0.2 0.3 0.4
VG (V)

22 Nikonov 4. TFET
 TFET Sub-threshold Slope
Tunneling current increases sharply at the onset of Source
Valence Band and Channel Conduction Band overlap

TFET
1.E-04

S
S 1.E-05
ID (A/um)

1.E-06

Ch 1.E-07

1.E-08
Ch
D VDS=0.4V D
1.E-09
0.0 0.1 0.2 0.3 0.4
VG (V)

23 Nikonov 4. TFET
 Effect of Gate-length
TFET subthreshold-slope improves significantly at longer
gate-length for a 10nm-body with a single-gate

Lg=25 nm
Id (uA/um)

50 nm
100nm

Single-gate
Vg (V) 10nm body

24 Nikonov 4. TFET
Single-gate vs. Double-gate
Increased gate-control continues to improve TFET
characteristics, whereas MOSFET is limited by 60mV/dec

DG TFET
2.5x
SG TFET

SG or DG
MOSFET
~60

40 <20 mV/dec
5nm body
Lg=100nm
For cnst. IOFF=1nA/um

25 Nikonov 4. TFET
 Effect of Body thickness
Thinner body has lower SS and higher drive
The effect is much less pronounced than SG/DG difference

tB=10 nm

20 nm

thinner
Single-gate
Lg=100nm
For cnst. IOFF=1nA/um

26 Nikonov 4. TFET
Effect of Device Geometry on
Subthreshold-Slope

2x Lg
tB
SGDG Lg=50nm tB=10nm SG
Lg=100nm tB=10nm SG
Lg=100nm tB=5nm SG
Lg=100nm tB=5nm DG

27 Nikonov 4. TFET
 InAs TFET Device Design
Narrow bandgap (e.g. InAs) required for high ION
Drain underlap to lower ambi-polar IOFF leakage

1.E+02

1.E+01
ID (uA/um)

1.E+00 LG = 20 nm
tBody = 5 nm
1.E-01
tOx(SiO2) = 1 nm
ITRS Low Power CMOS NSource = 5e19 cm-3
1.E-02
NDrain = 5e18 cm-3
1.E-03
TFET- S/D Symmetric
TFET with Drain underlap
1.E-04
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
VDS=0.5V
VG (V)
28 Nikonov 4. TFET
 Transistor Characteristics - II
TFET has better Rout in the saturation region (high VDS)
TFET has higher saturation voltage (VDSAT-EFF)
30 VGS 30
TFET =0.35V MOSFET (ITRS)
25 25 0.35V
VDSAT-EFF
20 20
ID (uA/um)

0.3V
15 15 IOFF =1nA/m
10 0.25V 10 0.3V
VDSAT-EFF
5 0.2V 5
0.25V
0 0 0.2V
0.0 0.1 0.2 0.3 0.0 0.1 0.2 0.3
VDS (V) VDS (V)
29 Nikonov 4. TFET
 Transistor Characteristics
Subthreshold Slope (SS): 34-45 mV/dec
Strong IOFF dependence on VDS
1.E+02
TFET
1.E+01
1.E+00
ID (uA/um)

1.E-01
1.E-02 0.5V
1.E-03
0.4V VDS
1.E-04 0.3V
1.E-05 0.2V
0.1V
1.E-06
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
VG (V)
30 Nikonov 4. TFET
HTFET Material Considerations

Lattice matched to InP Metamorphic Growth on InP or GaAs

Staggered and broken gap systems have higher tunneling probability.

11
Theresa Mayer and Suman Datta, Penn State, SRC review 2011

31 Nikonov 4. TFET
InAs TFET, on current

Nikonov, Avci, Rios, Kuhn

32 Nikonov 4. TFET
InAs/GaSb TFET, on current

Nikonov, Avci, Rios, Kuhn

33 Nikonov 4. TFET
 Heterojunction TFET
Both simulations and experimental data show significant
improvement for heterojunction channel design over
homojunction
Heterojunc.
Lg=15nm
Homojunc. Simulation
(Avci, VLSI Tech 12)
Heterojunc.
Lg=100nm
Experimental
Homojunc.
(Dewey, IEDM11)

34 Nikonov 4. TFET
 InAs/GaSb Heterojunction TFET
T-FET ION/IOFF characteristic was improved for both N-type and P-type with:
Thinner channel
Changing device material from InAs homo-junction to a GaSb/InAs hetero-junction.
P-TFET sub-threshold slope has MOS-like thermal behavior ~60mV/dec, due to
low density of sates (DOS) in the conduction band.
N-type P-type
1.E+03 1.E+03

1.E+02 1.E+02

1.E+01 1.E+01
30-45 ~60
Id (uA/um)

Id (uA/um)
1.E+00
mV/dec VDS = 0.5V mV/dec 1.E+00
1.E-01 IOFF = 10pA/um 1.E-01

1.E-02 P1272 MOS 1.E-02

P1272 MOS
1.E-03 1.E-03
5nm Homo-jnc 5nm Homo-jnc
1.E-04 1.E-04
2.5nm Hetero-jnc 2.5nm Hetero-jnc
1.E-05 1.E-05
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
VG (V) VG (V)

35 Nikonov 4. TFET
 TFET Capacitance
Increased TFET CGD capacitance quoted in literature, due to the
choice of TFET material (Si or Ge). But lower capacitance at
smaller voltages beneficial for delay.
TFET

S Channel D

EF
EF

Filled
states

Y. Yang et. al. (EDL 2010)

36 Nikonov 4. TFET
 III-V N-TFET Capacitance
III-V Conduction Band has low density of states resulting in low
N-TFET Cgate and CGD

1E+20 E
Eff. Density of States (1/cm3)

Valance
Band
1E+19
DOS
EF LOW

1E+18 EF

1E+17
Conduction
HIGH
Band
1E+16
Ge
Si

InGaAs

InSb
InAs

x (nm)
37 Nikonov 4. TFET
 TFET Summary
Benefits
Vg Gate
Steep sub-threshold slope
Source Drain (< 60 mV/dec)
Vd Large Ion/Ioff ratio
P+ i-InAs N
Geometry scales well
Some designs are compatible with
conventional SiGe/Si CMOS
processes
Challenges
Poor experimental drive currents
Ambipolar conduction
(high DB leakage for bulk devices)
No comparable PTFET
Asymmetric device behavior (issues in
Tunneli SRAM)
ng Most attractive at very low operating
voltages (where product frequencies
barriers may be not so interesting)
Courtsey M. Luisier (Purdue)
M. Luisier and G. Klimeck, EDL, 2009

38 Nikonov 4. TFET
Summary

Band-to-band tunneling underpins TFET

Gate voltage changes tunneling in a TFET
Most experimental devices are still far from
ideal (Intel stands out)
Atomistic simulations with NEGF method
Homojunction TFET = lower on-current
Heterojunction TFET = higher on-current

39 Nikonov 4. TFET