Professional Documents
Culture Documents
Version: V6.30.201
ZTE CORPORATION
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Postcode: 518057
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Revision History
II
III
IV
Intended Audience
l Planning engineers
l Equipment installation engineers
l Commissioning engineers
l Maintenance engineers
Chapter Summary
Chapter 3, Subrack Describes the functions, structure, and interfaces of the ZXG10 iBSC
subrack.
Chapter 4, Shelf Describes the types, configuration, and interconnection of the ZXG10
iBSC shelf.
Chapter 5, Board Describes the functions, structure, and interfaces of the ZXG10 iBSC
board.
Chapter 6, Auxiliary Devices Describes the functions and structure of the ZXG10 iBSC auxiliary
devices.
Appendix A, Combined Describes meaning of combined indicator status of the ZXG10 iBSC
Indicator Status Descriptions board.
II
1-1
The ZXG10 iBSC cabinet meets the CompactPCI standard. The front door is navy blue,
with dense vents. The cabinet body is navy blue.
Hardware Composition
The ZXG10 iBSC consists of the following hardware:
l Cabinet
A cabinet consists of a top, a front door, a rear door, one or more racks and a busbar.
l Subrack
Subracks include power distribution subrack, fan subrack, and dust-proof subrack.
1-2
l Shelf
Shelves include control shelf, resource shelf, gigabit resource shelf, and packet
switched shelf.
l Board
Boards include front board, rear board, and backplane.
l Auxiliary device
Auxiliary devices include alarm box and GPS-related devices.
1-3
1-4
Dimension (side door included) 2000 mm 600 mm 800 mm 2000 mm 650 mm 800 mm
(H W D) 19 cabinet (H W D) 19 cabinet
Power Distribution Subrack adopting new power distribution adopting old power distribution
subrack, providing two subrack, providing one
independent power outputs independent power output
for each shelf in the cabinet for each shelf in the cabinet
2-1
2-2
Top Fan
The top fan is an iminterfaceant component of the whole equipment for ventilation and
dissipation. It consists of a bottom installation plate, six fans, and a monitoring circuit
plate.
For the top fan structure, see Figure 2-3.
2-3
Top Filter
The top filter is a interface for power input of the whole equipment. The -48 V power cable
from the equipment room is connected to the input end of the top filter. After the power
is filtered, the power cable is connected to the internal power distribution subrack of the
cabinet.
For the top filter structure, see Figure 2-4.
Wire Reel
The wire reel is used to wrap remaining fibers. It consists of the bottom plate, wire post,
and cover.
For the wire reel structure, see Figure 2-5.
2-4
2.2.3 Rack
The rack is composed of the top shelf, bottom shelf, post, adjustable rail, and side door.
For its structure, see Figure 2-7.
2-5
Note:
When multiple cabinets are installed side by side, only the side doors of the two cabinets
located outside need to be installed.
2-6
2.2.4 Busbar
The power distribution cable and grounding cable of the ZXG10 iBSC are connected in the
unified manner through the busbar. For the busbar structure, see Figure 2-8.
The busbar is located at the right side of the cabinet back and provides six groups of
connectors. The signal definition of the busbar connectors is shown in Table 2-2.
2-7
2-8
2-9
Note:
Among the signal cables of the ZXG10 iBSC, only fibers are led from the front board panel
and all the other cables are led from the rear board panel.
2-10
Power
1. The normal voltage for system operating is -48 V DC. It ranges from -40 V DC to -57
V DC.
2. The system power uses the fully distributed design. The board itself provides a power
module that implements one-off voltage conversion and isolation from -48 V to board
voltage such as +5 VDC, +3.3 VDC, +2.5 VDC, and +1.8 VDC.
3. The cabinet power input is a power distribution subrack that has two power inputs.
One of them is selected by using the switch to provide power for all shelves and fans.
The two power inputs are mutually backed up. The -48 V power is transmitted from
the power distribution subrack downwards through a busbar. The power of all shelves
and fan subracks is from one -48 V busbar.
Grounding
There are two grounding types.
1. -48 VGND: -48 V ground
2. GNDP: system protection ground
The active board GND and electrostatic GNDE of each shelf are converged to the
GNDP through a filter and connected to PE of the busbar. The PE binding post at the
upper right of the subrack is used to connect the GNDP to the grounding bar of the
equipment room.
Note:
Judgment method of left and right PE binding posts: From the back of the cabinet, the
PE binding post on the left is the left PE binding post and the one on the right is the
right PE binding post.
The -48 VGND is led from the power subrack and uses a busbar to connect the -48
VGND of all subsystems.
The -48 VGND is connected to the GNDP securely in the equipment room.
The subrack provides two grounding types: grounding upwards and grounding
downwards. The subrack pick-up impedance ranges from 0.1 to 0.3 . The
grounding impedance of the equipment room must be less than 1 .
Anti-Dust
1. A anti-dust mesh is installed at the bottom air intake of the subrack. The anti-dust
mesh is made of a frame (ABS plastic) and nylon mesh. It is soft and convenient for
installation and uninstallation.
2. The anti-dust mesh on the door panel is made of a metal frame with secondary
polyurethane foaming plastic.
2-11
The two types of anti-dust meshes can be cleaned and reused. In addition, they can be
easily uninstalled or replaced.
Dissipation
For dissipation air duct of the ZXG10 iBSC, see Figure 2-11.
2-12
EMC
The EMC design lies in the shielding and grounding processes of shelves and subracks.
The shielding process is of the subrack level. The minimum shielding characteristic is 40
dB when the frequency ranges from 30 MHz to 1 GHz.
Subracks supinterface EMC shielding and adopt electroplating and surface treatment. This
ensures that the subracks have good conductivity.
The contact between subracks and plug-ins or between plug-ins are connected by using
conductive springs.
To ensure normal grounding, subracks have special anti-static grounding devices for
connecting subracks and shelves.
2-13
2-14
Power Input Two power inputs, providing Two power inputs, providing
mutual backup to each other mutual backup to each other
Power Output Two power outputs, providing One power output, no backup
mutual backup to each other
3-1
For the rear panel of an old power distribution subrack, see Figure 3-3.
3-2
For the rear panel of a new power distribution subrack, see Figure 3-5.
Flashing at 1 Hz:
indicates that the power
distribution subrack
operates normally.
Not lit: indicates that
the power distribution
subrack operates
RUN Green Operating indicator abnormally.
3-3
3-4
l Implements detection and alarming for rack power and environment, fan detection
and control.
l Supports being monitored and managed by the OMP board through the RS485 bus,
reports the detected information to the OMP board, and provides related indications
through the indicators on the panel of the power distribution subrack.
3-5
The PWRD consists of several parts, including one power distribution module, one main
monitoring module, one transit board (PWRDB),and four fan group control modules.
1. The power distribution module processes the input two channels of -48 V power
including filter, lightning protection and isolation, and supplies power for all shelves
through the busbar. In addition, the power distribution module samples the power
before the two channels of power merge at the busbar and sends the power to the
PWRD for overvoltage or undervoltage monitoring.
2. The PWRD processes the two channels of -48 V voltage, including overvoltage
and undervoltage detection, rotation detection for 24 fans, temperature detection,
humidity detection, smoke sensing detection, infrared alarm detection, and door
access detection for cabinet and equipment room.
The power distribution subrack consists of the power distribution module and PWRD.
3. The fan subrack consists of the 2 x 3 fan group and fan group control module.
The fan subrack gets the -48 V power from the busbar and sends the fan monitoring
signal to the PWRD.
4. The PWRDB board provides a interface for the PWRD board to access environmental
monitoring signals.
3-6
Default Setting
DIP Switch
Name Usage 1 (High Bit) 2 3 4 (Low Bit)
Used for
setting the
working mode
S2 to normal or ON OFF ON ON
debug. The
default value
is debug.
3-7
2. When the PWRD board is located at the middle of the 485 bus, 485 signals need to
be transmitted to the corresponding output interface, that is, pins 3 thru 4 and 7 thru
8 are short circuited.
3-8
3-9
3-10
4-1
For shelf location in the cabinet when resource shelves are used, see Figure 4-2.
4-2
5-1
5-2
Button Description
5-3
5-4
5-5
Button Description
5-6
5-7
5-8
5-9
Button Description
5-10
5-11
5-12
5-13
Button Description
Special indicator
Lit: indicates that the
Status indicators for con- control-plane cascading FE
L1-L46 Green trol-plane cascading network interfaces are connected.
interfaces 1 to 46 Not lit: indicates that the
control-plane cascading FE
interfaces are not connected.
5-14
5-15
5-16
Button Description
Active/standby status
ACT Green
indicator
Refer to Appendix A.
ALM Red Alarm indicator
Special indicator
Status indicators for Lit: indicates that the control-plane
control-plane cascad- cascading FE interfaces are connected.
L1-L46 Green
ing network interfaces Not lit: indicates that the control-plane
1 to 46 cascading FE interfaces are not
connected.
5-17
The function modules of the CLKG (CLKG) board are described as follows:
1. Main control unit
Manages the board, communicates with the system control unit, implements the
core clock control algorithm, controls clock signal output in accordance with the data
provided by the phase discrimination and phase lock unit, and selects the clock
reference.
2. Reference selection unit
Selects a proper reference clock from multiple input reference clocks under the control
of the main control unit.
3. Voltage controlled oscillator unit
Provides a high-precision clock source for the board by using an oven controlled crystal
oscillator that meets the level-3 clock standard.
5-18
5-19
Button Description
5-20
and an alarm is
reported.
Flashing at 1 Hz:
indicates that the board
can be removed. If
the micro switch is
turned on during board
operation and the board
operates in standby or
idle state, the board
can be removed.
Not lit: indicates that
the micro switch is in
normal state.
5-21
5-22
Debugging
X48 It is open when
- Open
X50 the board operates
normally.
Protection ground
jumper used for When pins 1 and 2
connecting to the are short circuited,
X53 Pins 1 and 2 short
coaxial cable shell the coaxial cable shell
X56 circuited
in the case of two is connected to the
channels of 2 Mbit/s or protection ground.
2 MHz clock inputs
5-23
5-24
The function modules of the CLKG (ICM) board are described as follows:
l Main control unit
Manages the board, communicates with the system control unit, implements the
core clock control algorithm, controls clock signal output in accordance with the data
provided by the phase discrimination and phase lock unit, and selects the clock
reference.
l Reference selection unit
Selects a proper reference clock from multiple input reference clocks under the control
of the main control unit.
l Voltage-controlled oscillator unit
Provides a high-precision clock source for the board by using an oven controlled
crystal oscillator that meets the level-3 clock standard.
l Phase detection and phase lock unit
Adjusts the phase comparison between the clock signal and input reference, and
provides quantitative data to the main control unit so as to control the voltage
controlled oscillator unit. The phase-lock system uses the loose coupling phase-lock
principle.
l Active/standby changeover unit
Implements the active/standby board changeover. The impact of the active/standby
switch on the clock is acceptable. The active and standby CLKG (ICM) boards are
locked to one reference for smooth changeover.
5-25
Button Description
5-26
Button Description
5-27
5-28
5-29
Settings
S1 ON ON ON ON
75
S5 ON ON ON ON
S1 ON ON ON ON
100
S5 OFF OFF OFF OFF
5-30
5-31
5-32
Button Description
5-33
5-34
5-35
5-36
Flashing at 2 Hz:
indicates that the
antenna feeder
operates normally but
fails to find the satellite.
Flashing at 0.5 Hz:
indicates that short
circuit occurs in the
antenna.
Flashing at 5 Hz:
indicates that no
message is received
during initialization.
Settings
DIP Switch
Mode Name 1 2 3 4
S1 ON ON ON ON
75
S5 ON ON ON ON
S1 ON ON ON ON
100
S5 OFF OFF OFF OFF
5-37
Settings
DIP Switch
Mode Name 1 2 3 4
5-38
The board has two independent CPUs, namely CPU A and CPU B. Each CPU provides
a control-plane FE electrical interface and an FE electrical interface for communication
between active and standby boards. In addition, CPU A supports board main control.
2. Logic unit
Supports all logic processing functions.
3. Power management unit
Implements board power management and distribution.
5-39
Button Description
Operating indicator of
RUN1 Green Refer to Appendix A.
CPU unit A
5-40
Operating indicator of
RUN2 Green Refer to Appendix A.
CPU unit B
5-41
5-42
Button Description
5-43
Button Description
Operating indicator of
RUN1 Green Refer to Appendix A.
CPU unit A
5-44
Operating indicator of
RUN2 Green Refer to Appendix A.
CPU unit B
5-45
Receives the clock from the backplane. After the clock is processed such as frequency
division and timeslot adjustment, it is provided for the board.
5-46
5-47
Button Description
5-48
Settings
DIP Switch
Name Usage Mode 1 2 3 4
Used for 75 ON ON ON ON
setting the
S1-S6 matching
S9 receive
impedance 120 OFF OFF OFF OFF
S12
of each E1
channel to
5-49
Settings
DIP Switch
Name Usage Mode 1 2 3 4
75 or 120
.
Used for 75 ON ON ON ON
showing the
matching
S7 receive
S8 impedance 120 OFF OFF OFF OFF
of each E1
chip for the
CPU.
5-50
5-51
Button Description
5-52
5-53
Settings
DIP Switch
Name Usage Mode 1 2 3 4
Used for 75 ON ON ON ON
setting the
matching
receive
S18-S25 impedance
120 OFF OFF OFF OFF
of each E1
channel to
75 or 120
.
Used for 75 ON ON ON ON
showing the
matching
S7 receive
S8 impedance 120 OFF OFF OFF OFF
of each E1
chip for the
CPU.
5-54
5-55
5-56
Button Description
5-57
5-58
DIP Settings
Switch
Name Usage Mode 1 2 3 4
5-59
5-60
5-61
Button Description
5-62
5-63
DIP Settings
Switch
Name Usage Mode 1 2 3 4
5-64
5-65
Button Description
5-66
5-67
5-68
Button Description
5-69
5-70
Receives clock from the system clock board and provides the reference clock signals
extracted from the STM-1 interface.
6. EC subcard
5-71
5-72
Button Description
5-73
5-74
2. Interface unit
Connects to the circuit switch unit and provides an STM-1 interface.
3. Circuit switching unit
Switches the circuit and HW of the interface unit.
6. EC subcard
Implements echo suppression.
5-75
5-76
Button Description
5-77
5-78
5-79
5-80
5-81
Button Description
5-82
5-83
l Interface unit
Provides one GE interface.
5-84
5-85
Button Description
5-86
5-87
5-88
5-89
Button Description
5-90
5-91
5-92
5-93
Button Description
5-94
5-95
5-96
5-97
Button Description
5-98
5-99
Implement 16K circuit changeover and provides an inner circuit switch network for the
GB resource shelf.
l Ethernet switching unit
5-100
5-101
Button Description
5-102
5-103
5-104
Implement 16K circuit changeover and provides an inner circuit switch network for the
GB resource shelf.
l Ethernet switching unit
5-105
5-106
Button Description
5-107
5-108
5-109
l Logic unit
Supports all logic processing functions.
l Timeslot switching unit
Implement 16K circuit changeover and provides an inner circuit switch network for the
GB resource shelf.
l Ethernet switching unit
5-110
5-111
Button Description
5-112
5-113
Implements conversion between TDM and IP packets over the Ater interface, that is,
searches for 20 ms TRAU frames by channel and assembles them as IP packets.
l Abis interface processing board BIPB
The CS and PS services from the BTS are switched to the BIPB board through
the circuit switch network of the resource shelf. The interface searches for 20 ms
TRU (PCU) frames by channel on the BIPB board, assembles them as IP packets,
5-114
and sends them to the TCU for code pattern conversion and rate adaption or to the
user-plane processing unit (UPU).
l Dual-rate conversion board DRTB
Implements code pattern conversion, provides code pattern conversion and rate
adaption for TRAU frames, and supports the FR, EFR, HR, AMR, and TFO functions.
5-115
l Clock unit
Provides necessary clock signals for all units on the board.
l Circuit switch unit
Connect the serial interfaces of multiple DSP chips to the circuit packet network.
5-116
Button Description
5-117
On the STM-1 or E1 Abis interface, the CS and PS services from the BTS are
switched to the BIPB2 board through the circuit switch network of the resource shelf.
The interface searches for 20 ms TRU (PCU) frames by channel on the BIPB2
board, assembles them as IP packets, and sends them to the TCU for code pattern
conversion and rate adaption or to the user-plane processing unit (UPU).Except the
above functions, the BIPB2 board uses the IP Abis interface to process RTP packets.
l A interface processing board AIPB2
Processes RTP packets on the A interface and assembles the data as IP packets.
5-118
l CPU unit
Manages the board, processes Abis signaling, and provides an external control-plane
FE interface.
l Logic unit
Supports all logic processing functions.
l DSP unit
Provides multiple DSP chips for code pattern conversion, rate adaption, or data packet
conversion.
l Ethernet switching unit
Connects multiple DSP chips over Ethernet and provides an external user-plane GE
interface.
l Clock unit
Connect the serial interfaces of multiple DSP chips to the circuit packet network.
5-119
Button Description
5-120
5-121
5-122
l CPU unit
Manages the board, processes Abis signaling, and provides an external control-plane
FE interface.
l Logic unit
Supports all logic processing functions.
l DSP unit
Provides multiple DSP chips for code pattern conversion, rate adaption, or data packet
conversion.
l Ethernet switch unit
Connects multiple DSP chips over Ethernet and provides an external user-plane FE
interface.
l Clock unit
Provides necessary clock signals for all units on the board.
l Circuit switch unit
Connect the serial interfaces of multiple DSP chips to the circuit packet network.
5-123
Button Description
5-124
5-125
The board has two independent CPUs, namely CPU A and CPU B. Each CPU provides
a control-plane FE electrical interface, an FE electrical interface for communication
between active and standby boards, RS232 and RS485 interfaces for communication
with other units. In addition, CPU A supports board main control.
2. Logic unit
5-126
5-127
Button Description
Operating indicator of
RUN1 Green Refer to Appendix A.
CPU unit A
5-128
operates in standby or
idle state, the board
can be removed.
Not lit: indicates that
the micro switch is in
normal state.
Flashing at 5 Hz:
HD1 Red Hard disk indicator 1 indicates that the hard
disk is operating.
Operating indicator of
RUN2 Green Refer to Appendix A.
CPU unit B
5-129
Flashing at 5 Hz:
HD2 Red Hard disk indicator 2 indicates that the hard
disk is operating.
5-130
Button Description
5-131
Button Description
Operating indicator of
RUN1 Green Refer to Appendix A.
CPU unit A
5-132
Flashing at 5 Hz:
HD1 Red Hard disk indicator 1 indicates that the hard
disk is operating.
Operating indicator of
RUN2 Green Refer to Appendix A.
CPU unit B
5-133
Flashing at 5 Hz:
HD2 Red Hard disk indicator 2 indicates that the hard
disk is operating.
5-134
5-135
Button Description
5-136
5-137
5-138
5-139
Button Description
Board removal
ENUM Yellow Reserved
indicator
Active/standby status
ACT Green Reserved
indicator
5-140
5-141
5-142
Button Description
Board removal
ENUM Yellow Reserved
indicator
Active/standby status
ACT Green Reserved
indicator
5-143
5-144
5-145
5-146
Button Description
5-147
5-148
5-149
5-150
Button Description
5-151
5-152
5-153
5-154
Button Description
5-155
5-156
5-157
5-158
Button Description
5-159
Settings
DIP Switch
Name Usage Mode 1 2 3 4
Used for 75 ON ON ON ON
setting the
S3-S6 matching receive
120 OFF OFF OFF OFF
impedance of
each E1 channel.
5-160
Settings
DIP Switch
Name Usage Mode 1 2 3 4
Used for 75 ON ON ON ON
setting the
S2 matching receive
120 OFF OFF OFF OFF
impedance of
each E1 chip.
1. S3-S6 are used for setting the matching receive impedance of each E1 channel. OFF
indicates that the matching impedance is 120 and ON indicates that the matching
impedance is 75 .
l Channels 1 thru 4 of S3 represent E1 channels 1 thru 4 of the SPB board.
l Channels 1 thru 4 of S4 represent E1 channels 5 thru 8 of the SPB board.
l Channels 1 thru 4 of S5 represent E1 channels 9 thru 12 of the SPB board.
l Channels 1 thru 4 of S6 represent E1 channels 13 thru 16 of the SPB board.
2. S1 and S2 are used for setting the long-haul and short-haul status of the E1 chip and
its matching receive impedance. The CPU reads the status and initializes the E1 chip
in accordance with the status.
Channels 1 thru 4 of S1 and S2 represent parts 1 thru 4 of the E1 chip, that is, E1
channels 1 thru 4, 5 thru 8, 9 thru 12, and 13 thru 16.
l S1: OFF indicates the long haul and ON indicates the short haul.
l S2: OFF indicates that the matching impedance is 120 and ON indicates that
the matching impedance is 75 .
Processes MTP2 and X.25 packets and extracts 8K synchronization clock from lines.
l Gb interface processing board GIPB2
Processes FR, NS, and BSSGP packets of the GPRS and supports Gb interfaces.
5-161
5-162
Button Description
5-163
5-164
5-165
5-166
Button Description
5-167
5-168
5-169
5-170
Button Description
5-171
5-172
5-173
l CPU unit
Connects the timeslot switch unit, logic unit, and Ethernet switch unit through the
control bus and implements switch unit configuration, logic unit configuration and
management, and resource shelf/GB resource shelf management.
Provides debugging, active, and standby Ethernet interfaces.
l Logic unit
5-174
Button Description
5-175
5-176
5-177
l CPU unit
Connects the timeslot switch unit, logic unit, and Ethernet switch unit through the
control bus and implements switch unit configuration, logic unit configuration and
management, and resource shelf management.
Provides debugging, active, and standby Ethernet interfaces.
l Logic unit
5-178
5-179
Button Description
5-180
5-181
5-182
l CPU unit
Connects the timeslot switch unit, logic unit, and Ethernet switch unit through the
control bus and implements switch unit configuration, logic unit configuration and
management, and resource shelf management.
Provides debugging, active, and standby Ethernet interfaces.
l Logic unit
5-183
5-184
Button Description
5-185
5-186
5-187
5-188
Button Description
5-189
5-190
5-191
5-192
For a description of the external interfaces on the RCHB1 V040502 board, refer to Table
5-121.
Table 5-121 External Interfaces on the RCHB1 V040502 Board
5-193
5-194
5-195
For a description of the external interfaces on the RCHB2 V040502 board, refer to Table
5-123.
Table 5-123 External Interfaces on the RCHB2 V040502 Board
5-196
5-197
For a description of the external interfaces on the RCKG1 V071200 board, refer to Table
5-125.
5-198
5-199
5-200
For a description of the external interfaces on the RCKG2 V071200 board, refer to Table
5-127.
5-201
5-202
5-203
5-204
5-205
5-206
5-207
5-208
5-209
5-210
5-211
5-212
5-213
5-214
5-215
For a description of the external interfaces on the RSVB V090300 board, refer to Table
5-138.
5-216
5-217
5-218
5-219
5-220
5.5 Backplane
5.5.1 BCTC Board
5.5.1.1 BCTC Backplane Structure
The BCTC is a control shelf backplane. Its has two versions: V040203 and V060201.
5-221
5-222
5-223
For DIP switch configuration of the BCTC board, refer to Table 5-142.
S1/X2 Used for configuring an office The office number is the value
number of three bits on the left of S1 or
at the bottom of X2.
S2/X3 Used for configuring a rack The rack number is the value of
number all four bits on S2 or X3 plus the
value 1.
S3/X4 Used for configuring a shelf The shelf number is the value
number of two bits on the left of S3 or at
the bottom of X4 plus the value
1.
5-224
5-225
5-226
5-227
5-228
5-229
5-230
6-1
6-2
The voice management at background realizes the voice recording, edit and
pre-play, and downloads the voice file into the FLASH of the alarm box.
c. LCD screen
6-3
There are some function buttons on the alarm box, which realize the operation
and maintenance functions together with LCM.
4. Logic unit
Use EPLD to implement the required combinational and sequential logic.
5. Power supply unit
The input voltage of the alarm box is -48 V DC from the equipment room, and is
converted to +5 V, +3.3 V and other voltages for each unit by DC-DC power converter.
When the alarm box is in the duty room outside the equipment room, there may not be -48
V DC power, in this case, a external AC/DC power adapter is required to convert 110/220
V AC to 48 V DC, providing -48 V DC power to the alarm box. AC/DC power adaptor is an
optional accessory of the alarm box.
The left top of the panel is the indicator in arc shape and the LCD screen is located in the
center of the panel.
6-4
ZXG10 iBSC uses 2 to connect Hub and background EMS, 4 to download alarm box
versions, 6 to connect DC power supply, and 7 for power supply.
1. The alarm box comprises cover components, body components, PCB board,
apparatus, and assembly fasteners.
a. Cover components include LCD screen, buttons, indicators, and lamp plate.
b. Body components are the sheet-metal parts to mount the motherboard and
speakers.
c. PCB comprises motherboard, lamp plate, keyboard, and modem board.
d. Apparatus contains LCD screen, indicators, buttons, switches, RJ11, RJ45, DB9,
earphone hole, mobile antenna, GPS interface, 48V socket, and speakers.
e. Alarm box is locked.
f. The outline dimensions of an alarm box is: 220 mm x 310 mm x 58 mm (H x W x
D)
2. Interface Description
The relevant interfaces on the alarm box board are described in Table 6-1
6-5
The parallel bus of the master unit attaches cable MODEM chip,
to provide the external cable modem interface and to implement
Cable modem in- the cable transmission of alarm information (currently, ZXG10
terface iBSC does not use this interface).
Name Description
6-6
6-7
ALB expansion function enables ALB to be installed in remote areas and connected
to the remote server, and receives on-site alarms through the data network. One ALB
can simultaneously connect five background servers at most.
6-8
Function Description
The GPS antenna receives GPS satellite navigation and positioning signals, and
demodulates the frequency, clock signal, and AGPS information through GPS signal
receiver. The clock signal is sent to relevant units in ZXG10 iBSC system while the AGPS
information is sent to the processing unit.
The GPS antenna lightning protector/frequency divider uses dual-frequency-dividing
coaxial cable protector, which is installed at the connector between communication
equipment and coaxial cable, or at lightning protection devices between two
communication equipments. It effectively prevents damages due to temporary
over-voltage caused by lightning induction.
The GPS antenna lightning protector/frequency divider adopts the high-frequency filter
principle and performs three-level protection for the DC feed channel. The RF insertion
loss is small, the discharge current is large, and the measured limiting voltage is low. It is
an ideal protection device for various public antenna communication equipments.
Device Description
1. Figure 6-6 shows the active GPS antenna.
6-9
Wiring Description
Figure 6-8 shows connections between ICM, GPS active antenna, and GPS antenna
lightning protector/frequency divider (fixed on the cabinet top).
6-10
Figure 6-8 Connection of ICM, Active GPS Antenna, and Lightning Protector/Frequency
Divider
1. GPS antenna
2. GPS Antenna Lightning
Protector/Frequency
Divider
Technical Parameters
1. Table 6-4 shows the technical parameters of active GPS antenna.
Parameter Specification
DC voltage 4.5 ~ 6 V
DC current <35 mA
Parameter Specification
Insertion loss 4 dB
6-11
Parameter Specification
Parameter Specification
Gain 45 dB 2 dB
Connectors TNC
2. Table 6-7 describes technical parameters of the GPS L1 indoor transmitting antenna.
Parameter Specification
Gain 26 dB 2 dB
6-12
Parameter Specification
Connectors TNC
Cable length 10 m
Parameter Specification
Current 80 mA
Connectors TNC
Parameter Specification
DC voltage 5.5 V
Remained voltage 20 V
Installation Mode Installing through the wall; installing by the copper lug
6-13
Parameter Specification
6-14
Periodically flashing
Running normally at 1 Hz Always OFF Normal running
Periodically flashing
at 5 Hz Always OFF Version being downloaded
Periodically flashing
Always OFF at 5 Hz Board self-test failure.
A-1
Periodically flashing
at 1 Hz Always ON Hardware clock is lost.
A-2
II
III
IV
VI
VII
VIII
IX
XI
XII
CCS
- Common Channel Signaling
CS
- Circuit Switched
GLI
- Gigabit Ethernet Line Interface
GLI4
- Gigabit Line Interface board version 4
GPRS
- General Packet Radio Service
GPS
- Global Positioning System
PS
- Packet Switched
PWRD
- Power Distributor
PWRDB
- POWER Distributor Backplane
XIII
SBCX
- X86 Single Board Computer
SBCX2
- X86 Single Board Computer version 2
SPB
- Signaling Process Board
SPB2
- Signaling Process Board version 2
SPB3
- Signaling Process Board version 3
XIV