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compliant IP cores for major Reference designs for SFI-4, DDR 1 SDRAM controller
system interface protocols. This Realize Over 1 Gbps performance with the unique built-in ChipSync technology
allows the designer to focus on ChipSync source-synchronous technology embedded in every I/O
the user application rather than Dynamic programmable delay/data centering with per-bit de-skew on every I/O
Bitslip module for training patterns
interoperability and standards
Internal SerDes modules and regional clocks
compliance.
With Virtex-4 FPGA Source- Discover the complete hardware development and evaluation platform
64 MByte SystemACE
SDRAM Module
Example: Tx Diagram. 1 Gbps, 2.5V LVDS, PRBS23 pattern.
User System 3.3 Volt Complete Solution: The kit comes with the following Xilinx
LEDs
System 2.5 Volt Productivity Advantage (XPA) options:
VCCAUX 2.5 Volt
ML450 Platform including Compact Flash, clock modules,
VCCO 2.5 Volt
documentation, reference designs, cables, and evaluation software
VCCO 1.2 Volt
ISE Foundation Software
Voltage Regulators
IP Cores: SPI-4.2, RapidIO*, and GFP*
Training, Premium, and Titanium services
* Check with your Xilinx sales representative for availability
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All other trademarks are the property of their owners.