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PowerFactory
V001Relay model description
Published by
DIgSILENT GmbH, Germany
Table of Contents
The ABB REG 216 PowerFactory relay model consists of a main relay model and 8 subrelays:
The main relay contains the measurement and acquisition units, the output logic and all other subrelays:
The voltage and the current are measured by two current transformers (Ct and Neutral Ct blocks) and one voltage
transformer (Vt block). Two additional current transformers are used by the differential elements: the Remote Ct block
represents the Cts located at the generator/motor ground terminals. The Remote Ct Transf block represents the Cts located at
the CSU transformer terminals.
Six measurement units (Measure, Delta Measure , Measurement Seq, Meas Neutral I, Remote Measurement and
Remote Measurement Transf blocks) are fed by these CTs and the VT.
1.1.2 Functionality
The input signals are sampled at 12 samples/cycle; a DFT filter operating over a cycle calculates then the voltage and current
values used by the protective elements.
Please note that the nominal current and the nominal voltage values MUST be entered in all the measurement units.
1.2.2 Functionality
This block is operating the breaker. Please disable the Logic block to disable the relay model ability to open the power circuit.
The signal operating the breaker is yout. Eleven additional output signals (OUT1 OUT11) freely configurable are
available.
Three ground current definite time overcurrent elements (3I0 Current DT 1, 3I0 Current DT 2 and 3I0 Current DT
3 block)
Three 3 phase definite time directional overcurrent elements (3ph DirCurrent DT 1, 3ph DirCurrent DT 1 angle,
3ph DirCurrent DT 2, 3ph DirCurrent DT 2 angle, 3ph DirCurrent DT 3 and 3ph DirCurrent DT 3 angle block)
Three ground current definite time directional overcurrent elements (3I0 DirCurrent DT 1, 3I0 DirCurrent DT 1
angle, 3I0 DirCurrent DT 2, 3I0 DirCurrent DT 2 angle ,3I0 DirCurrent DT 3 and ,3I0 DirCurrent DT 3 angle
block)
Three neutral current definite time directional overcurrent elements (IN DirCurrent DT 1, IN DirCurrent DT 1
angle, IN DirCurrent DT 2, IN DirCurrent DT 2 angle ,IN DirCurrent DT 3 and ,IN DirCurrent DT 3 angle
block)
Two 3 phase inverse time directional overcurrent elements (3ph DirCurrent Inv 1, 3ph DirCurrent Inv6 1 angle,
3ph DirCurrent Inv 2 and 3ph DirCurrent Inv 2 angle block)
Two ground current inverse time directional overcurrent elements (3I0 DirCurrent Inv 1, 3I0 DirCurrent Inv 1
angle, 3I0 DirCurrent Inv 2 and 3I0 DirCurrent Inv 2 angle block)
Two neutral current inverse time directional overcurrent elements (IN DirCurrent Inv 1, IN DirCurrent Inv 1
angle, IN DirCurrent Inv 2 and IN DirCurrent Inv 2 angle block)
One ground current peak value time defined element with frequency block (3I0 Current-Inst and 3I0 Current-Inst
Frequency limit block)
One neutral current peak value time defined element with frequency block (IN Current-Inst and IN Current-Inst
Frequency limit block)
Two negative sequence inverse time overcurrent elements (NPS-Inv 1 and NPS-Inv 2 block)
Two negative sequence time defined overcurrent elements (NPS-DT 1 and NPS-DT 2 block)
Two phase undercurrent elements(3ph Current DT MIN 1 and 3ph Current DT MIN 2 block)
One stator overload element (OLoad-Stator, OLoad-Stator IB, tmax, tmin, and tg block)
One voltage restrained/controlled element (V dep OC I> and V restraint block). To select which voltage logic is
enabled, the restraint factor (V Dep OC k Set variable) and the restraint voltage levels (V Dep OC V<1Set and V
value derived from the phase voltages or the value measured by the open delta VT) is used can be set in the logic
tab page of the VPol Measured or Derived block.
1.3.2 Functionality
The model contains a full choice of phase, zero sequence (Holmgreens connection internally calculated), and neutral current
overcurrent elements. There is a set of directional and a set of no directional elements. There is one instantaneous (peak)
phase element, one instantaneous (peak) zero element sequence, one instantaneous neutral element which can be set to be
blocked when the frequency is falling below a given threshold.
The inverse time overcurrent elements support the following trip characteristics:
The relay IB setting in the OLoad-Stator IB block in the Logic tab page.
The relay I-Start setting in the Oload-Stator block as Current setting.
The relay k1-Setting setting in the Oload-Stator block as Time dial.
The relay t-min setting in the tmin block as Time setting.
The relay t-max setting in the tmax block as Time setting.
The relay tg setting in the tg block as Time setting.
The relay Current setting in the I>Ucontrol Current block as Current setting.
The relay Delay setting in the I>Ucontrol Delay block as Time setting.
The relay Hold-Voltage setting in the I>Ucontrol Voltage block as Voltage.
The relay Hold-Time setting in the I>Ucontrol HoldTime block as Time setting.
Two phase-ground time defined undervoltage elements (27P 1 and 27P 2, 27P 1Inst and 27P 2 Inst block)
Two phase-phase time defined undervoltage elements (27PP 1 and 27PP 2, 27PP 1 Inst and 27PP 2 Inst block)
Two phase-ground time defined overvoltage elements (59P 1 and 59P 2, 59P 1 Inst and 59P 2 Inst block)
Two phase-phase time defined overvoltage elements (59PP 1 and 59PP 2, 59PP 1 Inst and 59PP 2 Inst block)
Two zero sequence time defined overvoltage elements (59G 1 and 59G 2, 59G 1 Inst and 59G 2 Inst block)
Two negative sequence time defined overvoltage elements (59Q 1 and 59Q 2, 59Q 1 Inst and 59Q 2 Inst
block)
Two positive sequence time defined overvoltage elements (59V1 1 and 59V1 2, 59V1 1 Inst and 59V1 2 Inst
block)
Two positive sequence time defined undervoltage elements (27V1 1 and 27V1 2, 27V1 1 Inst and 27V1 2 Inst
block)
1.4.2 Functionality
The more common over/undervoltage protection elements have been implemented. For each protective element two blocks are
available: one fed by the voltage RMS values, one fed by the voltage instantaneous values. Please notice that the protective
elements fed by the voltage instantaneous values must be used only for the EMT simulations.
1.5.2 Functionality
The restraint logic of the change of frequency elements can be customized using the equation present in the Logic tab page
of the dfdt1logic, dfdt3logic, dfdt3logic and dfdt4logic block. Please notice that in such equation the win1 input is
coming from the voltage restraint block (Block Voltage dfdt x with x = 1,2,3,4) and the win2 input is coming from the
frequency restraint block (dfdt Frequency block x with x = 1,2,3,4)
1.6.2 Functionality
The subrelay implements two elements tripping when the active power is smaller than the given thresholds.
1.7.2 Functionality
The transformer differential feature has a current restraint threshold and an unrestraint threshold (Differential current base
threshold and Unrestrained differential threshold setting in the Transformer differential block). The 2nd harmonic blocking is
available as well (Harmonic blocking tab page). Please notice that in the provided relay scheme only two sets of 3ph current
inputs are connected. The relay ability to adapt the CT ratio and connection type can be mocked using the Winding 1 Adapter,
Winding 2 Adapter, Winding 3 Adapter block.
DIgSILENT
[sec.Ohm]
2,80
2,40
2,00
1,60
1,20
0,80
0,40
-5,20 -4,80 -4,40 -4,00 -3,60 -3,20 -2,80 -2,40 -2,00 -1,60 -1,20 -0,80 -0,40 0,40 0,80 1,20 1,60 2,00 2,40 2,80 3,20 3,60 4,00 [sec.Ohm]
-0,40
-0,80
-1,20
-1,60
-2,00
-2,40
-2,80
-3,20
-3,60
-4,00
S1\Cub_2\A BB REG 216
No user input is required is the Polarizing, in the Sup IN and in the Output Logic block.
DIgSILENT
[sec.Ohm]
-4,40 -4,00 -3,60 -3,20 -2,80 -2,40 -2,00 -1,60 -1,20 -0,80 -0,40 0,40 0,80 1,20 1,60 2,00 2,40 2,80 3,20 3,60 4,00 4,40 4,80 [sec.Ohm]
-0,40
-0,80
-1,20
-1,60
-2,00
-2,40
-2,80
-3,20
-3,60
-4,00
-4,40
-4,80
-5,20
-5,60
-6,00
-6,40
-6,80
S1\Cub_2\A BB REG 216
No user input is required is the Polarizing, in the Sup IN and in the Output Logic block.
1.10.2 Functionality
This subrelay implements a simplified model of the OOS logic present in the relay; the simplified model consists of two slip
zones and the OOS logic where the number of slips can be entered. No WarnAngle, TripAngle or t-Reset setting is
available in the model.
The ZA, ZB, ZC relay settings must be entered in the ZA, ZB, ZC model block as Reactance setting. The relay phi
angle setting is the Relay angle setting. Please notice that Relay angle must be phi+ 90.
The number of slip is the OOS, No. of crossing in the Out Of Step Outer-Inner model block.
DIgSILENT
REG 216:
wIabs_A;wIabs_B;wIabs_C
0
wIopr_A;wIopi_A;wIopr_B;wIopi_B;wIopr_C;
1
wUpol_A;wUpol_B;wUpol_C
2
Ur_A;Ui_A;Ur_B;Ui_B;Ur_C;Ui_C
3
Iabs
4
wIopr;wIopi yover..
5 0
wPol
6
wPolr;wPoli Overcurrent elements (F50 - F51 .. OUT1
7 ElmRelay 0
Iabs1
8
wIopr;wIopi1
9
Iabs2
10
Iabs_A;Iabs_B;Iabs_C1
11
12
Iabs4
13
14
1 OUT 1
wUabs1
1
2
yvolt..
1
Voltage elements (F27 - F59)
0 0 3 ElmRelay
wUabs2
1 1 4
M
2
easurement S..
2
RelMeasure wUabs..
3 5
wUabs
4 6
wUabs..
7
Iabs3
8
wUabs..
9 2 OUT 2
0
Meas delta0 wUlabs_A;wUlabs_B;wUlabs_C
1
RelMeasure wUabs..
2 1
0
1
2
0 3
Ia
0 0 1
Ib yfreq
1 1 2 Frequency elements (F81) 2
Ic ElmRelay
Ct 2 2
StaCt* 3I0
3 3 3
4 I2r_A;I2r_B;I2r_C 4 3 OUT 3
5 I0x3r 5
Measurement
6
RelMeasure*
7
Ua
0 4 8
Vt Ub
1 5 9
StaVt* Uc
2 6 10
11
12
13 U0x3r 0
1
yrevp
0 3
0
wIr_A..
0 0
Remote Ct1 wIr_B..
1
StaCt* wIr_C..
2 2 1
y lof
4
2
0
wIr_A..
0 0
Remote Ct Tranf wIr_B..
1 1
StaCt* wIr_C..
2 2 1
6 OUT 6
Remote Measur..
RelMeasure*
2 clock
y dis
5
1 7 OUT 7
2
0
8 OUT 8
1
o1
2
wIabs..
3
y dif f
Dif f erential (F87) 6
wIr_A.. ElmRelay
4
wIabs_A;wIabs_B;wIabs_C2 5
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_2 6
9 OUT 9
ICT2_..
7
IrCT2_A;IiCT2_A;IrCT2_B;IiCT2_B;IrCT_C;I
8
0
0 Z1block
1 10 OUT 10
1 Z2block 11 OUT 11
2 Pole slip
ElmRelay
2 Z3toZ5block
yoos
3 3 7
iblock 4
14
13
12
11
10
Iabs4
Iabs3
Iabs_A;Iabs_B;Iabs_C1
Ur_A;Ui_A;Ur_B;Ui_B;Ur_C;Ui_C
2
1
0
REG 216 overcurrent elements scheme:
RelLogdip2
Abs 1
0
wIabs..
wIabs..
Meas Freq
RelFmeas*
wIabs..
Iabs1..
Iabs(..
RelLogdip*
OLoad-Stator IB
wPolr..
O-Load Stator
Iabs_A;Iabs_B;Iabs_C
wU1abs
Iabs6
wIopr..
wIopr..
wPol
wUpol..
RelToc*
wPolr..
1
0
Oload-Rotor
Iabs2..
wIopr..
wIopr..
Iabs2
wPol(..
wUpol..
wstart_A;wstart_B;wstart_C
wPolr..
wIabs..
wstar..
Ur_A;..
wIopr..
wIopr..
Iabs
Iabs1
wPol(..
wUpol..
wstart_A;wstart_B;wstart_C(1)
tg
tmin
Ur_A;..
tmax
y _A;y _B;y _C
RelTimer*
RelTimer*
RelTimer*
wIopr..
wIopr..
Iabs1..
wPol(..
Iabs(..
wPolr..
wUpol..
ymin_A;ymin_B;ymin_C
wIopr..
ymax_A;ymax_B;ymax_C
Ur_A;..
yg_A;..
wIopr..
wIopr..
Iabs1..
wPol(..
Iabs(..
wPolr..
wUpol..
3
2
0
wIopr..
Ur_A;..
RelLogdip*
1Load-Rotor L..
wIopr..
Ur_A;..
3.2 Overcurrent
wInp
wIopr..
wIabs..
wIopr..
Iabs_..
Iabs5
wPolr..
wPol(..
wPol(8)
0 0
wPolr;wPoli(8)
I> Ucontr.. I>Ucontrol Curr..
RelTimer wor RelIoc*
1 I>Ucontrol 0Seal L.. y_s 1
RelLogdip*
1
wIabs..
I>Ucontro..
RelUlim1 ibloc.. I>Uco..
RelLo..
wintu<
0
wands
I>Ucontro..
RelTimer
1 0 0 0
0
IN DirCurrent.. IN DirCurrent Inv1 1 angle 0
3I0 DirCurren.. 1
3I0 DirCurren.. 0
3ph DirCurren.. 1
3ph DirCurren.. 3ph Current D..
RelToc* 1 wfwd;.. RelDir 2 RelToc* 1 wfwd;.. RelDir 2 wfwd_A;wrev_A;wfwd_B;wrev_B;wfwd_C
RelToc* 1 RelDir 2 RelIoc*
wIabs..
3 3 3
Iabs1(8)
NPS-Inv 1 IN DirCurrent.. IN DirCurrent Inv1 2 angle 3I0 DirCurren.. 3I0 DirCurrent Inv1 2 angle 3ph DirCurren.. 3ph DirCurren.. 3ph Current D..
wInp(..
wInp(..
0 0
y3pUc..
RelToc* RelIoc* 1 wfwd;.. RelDir 2 RelIoc* RelIoc* 1 wfwd;.. RelDir 2 RelIoc* 0
3ph DirCurren.. 1
3ph DirCurren.. 3ph Current D..
wfwd_A;wrev_A;wfwd_B;wrev_B;wfwd_C;wrev_ RelIoc*
3 3 RelIoc* 1 RelDir 2
3
0 0
0
0 0
NPS-DT 2 IN DirCurrent 0DT 3 IN DirCurrent DT1 3 angle IN Current DT 3 3I0 DirCurrent 0DT 3 3I0 DirCurrent DT1 3 angle 3I0 Current D.. 0
RelIoc* RelIoc* 1 wfwd;.. RelDir 2 RelIoc* RelIoc* 1 wfwd;.. RelDir 2 RelIoc* 0
3ph DirCurren.. 3ph DirCurrent DT1 3 angle 3ph Current D..
wfwd_.. RelIoc*
3 3 RelIoc* 1 RelDir 2
3
0
3ph Current-I.. 0
RelIoc* 3ph Current-I..
y3pDT..
0
IN Current-Inst 0 0
3I0 Current-Inst 0 RelFrq 1 iblock
RelIoc* IN Current-Inst Frequency limit RelIoc* 3I0 Current-Inst Frequency limit iblock
yI0Di..
y INDirInv 1
y NDT1
y3pDT..
yI0Di..
y 3pDirInv 2
y INDirInv 2
yI0DT..
y NDT2
yI0Di..
y INDT1
y 3pDirDT1
y INDirDT1
I0Dir..
yI0DT..
y NDT3
y INDT2
INDirDT2
y 3pDT2
3pDirDT2
y NDT4
yI0Di..
yI0DT..
y INDT3
y 3pDT3
y INDirDT3y
y 3pDirDT3y
y3I0I..
y 3pInst
y 3INInst
y 3pDT1
9
8
7
6
5
4
3
2
1
0
34
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
33
32
Trip Logic
RelLogdip
y out
DIgSILENT
16
3.3 Voltage
DIgSILENT
REG 216 voltage elements (F27/59):
wUabs_A;wUabs_B;wUabs_C
0
wU1abs
1
wU0abs
2
wUlabs_A;wUlabs_B;wUlabs_C
3
wU2abs
4
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
27V1 2
27PP1
27PP2
27P1
27P2
27V1
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
59V1 1
59V1 2
59PP1
59PP2
59G1
59G2
59Q1
59Q2
59P1
59P2
y27V11
y 59V12
0
y 59V11
1
y 59PP2
2
y 59PP1
3
y 27PP2
4
y 59Q2
5
y 27PP1
6
y 59Q1
7
y 27V12
8
y 59G2
9
10
y 59G1
11
y 27P2
12
y 59P2
13
y 27P1
14
y 59P1
15
wUabs_A;wUabs_B;wUabs_C1
5
wUabs
6
wUabs1
7
wUabs_A;wUabs_B;wUabs_C2
8
wUabs2
9
27V1 2 Inst
27PP1 Inst
27PP2 Inst
27P1 Inst
27P2 Inst
27V1 Inst
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
59V1 2 Inst
59PP1 Inst
59PP2 Inst
59G1 Inst
59G2 Inst
59Q1 Inst
59Q2 Inst
59P1 Inst
59P2 Inst
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
RelUlim
y 59V12inst
16
y 59V11inst
17
y 59PP2inst
18
y 59PP1inst
19
y 27PP2inst
20
y 59Q2inst
21
y 27PP1inst
22
y 59Q1inst
23
y 27V12inst
24
y 59G2inst
25
y 27V11inst
26
y 59G1inst
27
y 27P2inst
28
y 59P2inst
29
y 27P1inst
30
y 59P1inst
31
Ur_B;Ui_B
Ur_A;Ui_A
Ur_C;Ui_C
2
1
REG 216 frequency elements:
RelUlim
RelUlim
RelUlim
RelUlim
RelFmeas*
2
1
0Meas Freq0
Block Voltage..
Block Voltage..
Block Voltage..
Block Voltage df dt 3
RelUlim
RelUlim
RelUlim
RelUlim
Block Voltage..
Block Voltage..
wInp1
0
1
V/Hz calculat..
RelLogdip2
U/F inv2
RelChar
win1
wInp
0
Frequency 1
RelFrq
iblock
1
win11
win12
iblock3
0
Frequency 2 iblock1
RelFrq 1
3.4 Frequency
win13
0
Frequency 3 iblock2
RelFrq 1
0
Frequency 4
RelFrq 1
0
dfdt1logic
RelLogdip win2
1
0 0
dfdt1 iblock4 dfdt Frequenc..
RelFrq 1 RelFrq 1 iblock
0
dfdt2logic
RelLogdip
fluM2
win21
1
0 0
dfdt2 iblock5 dfdt Frequency block 2
RelFrq 1 1 iblock
RelFrq
fluM1
0
dfdt3logic
RelLogdip win22
1
0 0
dfdt3 iblock6 dfdt Frequency block 3
RelFrq 1 1
RelFrq iblock
yf1
0
dfdt4logic
RelLogdip win23
1
yf2
0 0
dfdt4 iblock7 dfdt Frequency block 4
RelFrq 1 1 iblock
RelFrq
yf3
9
8
7
6
4
3
2
1
0
5 Output
RelLogdip
logic
y out
DIgSILENT
18
3.5 Reverse power
DIgSILENT
REG 216 reverse power (F32) scheme:
wfwd
0
1
RelIoc*
32P1
Iabs
1
Ir_A;Ii_A;Ir_B;Ii_B;Ir_C;Ii_C
y_s
0 0
Ur_A;Ui_A;Ur_B;Ui_B;Ur_C;Ui_C
1 1
0
Power Calculator y out y out(1)
RelLogdip 1 Q 0 0 0
Unom
2 2
Output logic
RelLogdip
_32P2T
1 1 1
wfwd
0
yout1
RelIoc*
32P2
0
1
y_s
DIgSILENT
REG 216 differential scheme:
0 0
1 1
ICT1_A;ICT1_B;ICT1_C;IrCT1_A;IrCT1_B;IrC
Winding 1 Ada.. 0
2
RelCtadapt
2
Harm2ICT1_A;Harm2ICT1_B;Harm2ICT1_1
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_C 1
Measure 1 - 2..
RelMeasure
y trdif
0 0
wIabs_A;wIabs_B;wIabs_C1
3 0
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_1
4 1
Harm2ICT1_A;Harm2ICT1_B;Harm2ICT1_C
Winding
2 2 Ada.. 2
RelCtadapt
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_C
RelBiasidif f
Harm2ICT2_A;Harm2ICT2_B;Harm2ICT2_C
3
Measure 2 - 2..
RelMeasure
wIr_A;wIr_B;wIr_C Diff RMSMeas..
1
RelMeasure
wIabs_A;wIabs_B;wIabs_C2
5 0
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_2 Trip logic
6 1
ICT3_A;ICT3_B;ICT3_C;IrCT3_A;IrCT3_B;IrC RelLogdip
Winding
2 3 Adapter 4
RelCtadapt y out
0
y gendif f
1 0 1
2
3
Idif f ..
DIgSILENT
REG 216 underimpedance (F21) scheme:
wsup
Sup IN
RelIoc*
Underimpedance 1
wsupadd 1
RelDismho*
2
wstart y1
3 0 0 0
Underimpedanc..
Iabs_A;Iabs_B;Iabs_C
dummy 4
RelTimer
dummy 5 wands 1 1 T delay
wtimer 6
Iopr_A;Iopi_A;Iopr_B;Iopi_B;Iopr_C;Iopi_
Uopr_A;Uopi_A;Uopr_B;Uopi_B;Uopr_C;Uopi_
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_C
0 0
wUr_A;wUi_A;wUr_B;wUi_B;wUr_C;wUi_C
1 1
0
Polarizing 1 Output logic y out
RelZpol* RelLogic
2 Upolr_A;Upoli_A;Upolr_B;Upoli_B;Upolr_C;Upoli_C
3 dummy
0
Underimpedance 2
wsupadd 1
RelDismho*
2
wstart(1) y2
3 0 0 1
dummy 4
Underimpedance 2 Delay
RelTimer
dummy 5 wands 1 1 T delay
wtimer 6
DIgSILENT
REG 216 underreactance (F40) scheme:
Sup IN
RelIoc*
wsup
0
Underreactance 1
wIr_A;wIi_A;wIr_B;wIi_B;wIr_C;wIi_C
Iabs_..
0 0 wsupadd 1
RelDismho*
wUr_A;wUi_A;wUr_B;wUi_B;wUr_C;wUi_C Iopr_A;Iopi_A;Iopr_B;Iopi_B;Iopr_C;Iopi_
1 1 0 2
Polarizing 1 Uopr_A;Uopi_A;Uopr_B;Uopi_B;Uopr_C;Uopi_ wstart y1
3 0 0 0
RelZpol* Upolr_A;Upoli_A;Upolr_B;Upoli_B;Upolr_C;
2 4
Underreactanc..
RelTimer
3 5 wands 1 1
6
Tdelay
2
0
Underreactance 2
wsupadd 1
RelDismho*
2
wstart(1) y2
3 0 0 1
4
Underreactanc..
RelTimer
5 wands 1 1
6
Tdelay 1
DIgSILENT
REG 216 Pole slip:
1 ZA 0
2 RelDismho* 1 y_A;y_B;y_C
wsup_A;wsup_B;wsup_C 3
Iop_ri_ABC
Uop_ri_ABC
outermhoyout
0
wIr_A;wIi_A;wIr_B;wIi_B;w..
0 0 1
wI0x3r;wI0x3i ZB
1 1
wUr_A;wUi_A;wUr_B;wUi_B;w.. RelDisbl*
2 2 0 2
innerblinderyout
RelZpol* 2 Upolr_A;Upoli_A;Upolr_B;Upoli_B;Upolr_C;Upoli_C
3 T memory
0
outerzonetrip Z1block
1 0 0 0 0
Logic outer-inner Z2block
0 outerblindery out 1 1
Iabs_A;Iabs_B;Iabs_C wsupadd RelLogdip* innerzonetrip Z3toZ5block
3 0 1 0 2 1
Out Of Step Outer-Inner
1 2 2
I superv ision ZC RelDispspoly *
iblock RelIoc RelDismho*
4 1 2 1 3
wsup_A;wsup_B;wsup_C 3 2 3
wstart
0
OOS PickUp Delay
RelTimer
1
y1
0
Logic y out
3
RelLogdip*
y2 1
The model implementation has been based on the information available in the REG216, REG216 Compact
REC216 Numerical Generator Protection Numerical Control Unit Operating Instructions 1MDU02005-EN/3/Rev. 1 Edition March
2001 document.