Analysis of Dynamic Voltage Drop with PVT Variation in FinFET Designs
Yongchan Ban, Changseok Choi, Hosoon Shin, laewook Lee, Yongseok Kang and Woohyun Paik
System IC R&D Lab., LG Electronics
19, Yangjae-daero Ilgil, Seocho-gu
Seoul 137-130, South Korea
Phone: +82-10-5046-8692, E-mail: yc.ban@lge.com
Abstract
In this paper we have analyzed vectorless dynamic voltage
(IR) drops and characterized the impact of transistor-level PVT
(process-voltage-temperature) variation and metal-level RC
(resistance-capacitance) comer variation in FinFET SoC
(system-on-a-chip) designs. The impact of systematic process
variations on signal interconnects is also considered for
analyzing the worst case voltage drop in our design. Then, we
discuss factors that can affect the design closure metrics for
power and voltage integrity.
Keywords; Dynamic voltage drop, IR drop, power, vectorless,
PVT variation, systematic variation, FinFET, SoC
I. Introduction
Designing a power grid has a direct impact on chip
performance and reliability [1-2]. It should be guaranteed that
the power grid provides enough power supply voltage to all
transistors in cells in order to work the chip well with a certain
noise margin for all possible operations [2-3]. However, since
the threshold voltage of transistors does not scale down as fast
as the supply voltage with technology shrinking, circuit
tolerance to voltage drop becomes highly decreasing, which
results in smaller logic noise margins, chip performance
degradation, and even IC functional failures [4].
In addition, the impact of process, voltage, and temperature
(PVT) variation and inter die/within die process variation in
nanometer node design makes designers difficult to analyze
the design margin and estimate the voltage drop [5-6].
Moreover, 3D-type FinFET transistors facilitate voltage drops
due to their large driving strength. In this reason, a robust
analysis of voltage drop is crucial in high performance and
ultra-low power SoC (system-on-a-chip) designs.
Static IR drop computes an average voltage drop in an early
design stage to roughly estimate the IR drops and to provide
some feedback in an initial power grid design. However, the
verification with static voltage drop is not enough to ensure
power integrity because it does not consider power density,
switching activity, and the impact of inductance and
decoupling capacitances [4].
In this paper, we have analyzed vectorless dynamic voltage
(IR) drop (DVD) in an early FinFET design stage. The impact
of process, voltage, temperature variation and metal RC comer
variation has taken into consideration. In addition, we also
compute the impact of lithographic, etch and CMP
(chemical-mechanical polishing) systematic variations for
analyzing the worst case voltage drop.
978-1-4799-5127-71$31.00@)2014IEEE - 132 -
II. Calculation of Dynamic Voltage (IR) Drop
A. Power Estimation
Dynamic Power is comprised of internal power and
switching power as shown in Eq. (1).
PdynamiC + PsWltchmg C eff V2
=
P internal . . = X X
JI'elk (I)
where the internal power is dissipated due to charging and
discharging of the internal load and the switching power is
dissipated by the charging and discharging of the load
capacitance at the output of a cell.
B. Dynamic Voltage Drop
Dynamic voltage drop evaluates the IR drop for peak current
demand causing by the impact of decaps, inductance, and
spatial and temporal circuitry switching [3-4]. Vectorless DVD
uses current constraints to capture the circuit uncertainty at an
early design stage, and evaluates the worst-case voltage drops
at each node on the power grid [I].
C. Impacts ofProcess Variations
Interconnect distortions caused by process variations might
impact on voltage drop by changing the internal and load
capacitance. Since the patterning of signal interconnects still
use ArF (193nm wavelength) lithography to print sub-20nm
node, there are many unwanted effect resulting in large
distortions for the shapes on the wafer. The etch loading effect
induces etch bias variation which is not a constant value for all
kinds of features. While CMP varies the interconnect thickness
which leads to electrical shorts or increased wire resistance.
III. Experimental Condition and Results
For analyzing DVD in 16nm node FinFET design, we have
designed a CPU with an ARM Cortex-A57 CPU as shown in
Fig. 1. Standard cell library and memory macro library were
given from TSMC 16nm foundry. The maximum frequency
target in our CPU design is 1.2GHz at setup timing condition
with 9 track standard Vth and low Vth cell libraries.
CA57 CPU floorplan (b) Result of dynamic IR drop
Fig. 1. Cortex-A57 CPU tloorplan and a map ofiR drop
ISOCC2014
 TABLE 1 DVD WITH INPUT VOLTAGES TABLE 3 DVD WITH METAL RC CORNERS

#DVD #DVD Worst Worst #DVD #DVD Worst Worst

Voltage (Vdd) RC corners
Max. Min. Instance Wire Max. Min. Instance Wire

0.72 V 4256 1837 52.1% 50.2% RCBest DPT 531 426 27.8% 27.0%

0.8 V 4122 1586 45.4% 43.5% RCBest dPV 712 433 29.1% 27.6%

RCBest 561 433 28.4% 27.6%

0.88 V 4543 1086 40.3% 38.5%
Typical 1537 513 32.9% 31.6%
Simulation of dynamic IR drop was done with Apache RCWorst 4722 1199 40.5% 38.7%
Redhawk. We extracted the routed design netlist in DEF
RCWorst dPV 2365 400 33.5% 30.5%
format and the library technology in LEF format. Timing
information with SDC format, the instance-specific toggle RCWorst DPT 4543 1086 40.3% 38.5%

information and the technology file given from foundry were

used. In this experiment, since in an early design stage we did RCBest_DPT corners, where "_DPT" is a new corner
not place low power architectures and power switches. We are induced by double patterning lithography, shows better for
going to focus on the trends of variation to DVD in this paper. DVD compared to RCBest, meanwhile RCWorst shows worse
We swept PVT (process, voltage, and temperature) corners DVD than RCWorst DPT.
for the front-end FinFET transistor devices. The temperature The impact of design retargeting due to lithography/etch
across the chip was analyzed from -40C to 125C. The corner (width) and CMP (thickness) process variation was also
files of metal line parasitic were extracted from Synopsys considered at DVD simulation. By directly applying bias table
Star-RCXT. In addition to the conventional RC corners in extraction, R&C values for metal/via layers are updated. We
(Typical, RCbest and RCworst), we further analyzed DPT implemented the design retargeting due to process at RCBest
(double pattern technology) lithography induced RC corners: and RCWorst corners which are renamed with RCBest dPV
RCbest DPT and RCworst DPT. and RCWorst_dPV, respectively. As shown in Table 3, at
Table 1 shows DVD violations in terms of input voltage. The RCBest_dPV corner DVD increases because the design target
PVT for the front-end devices was set to a typical process is thinner (higher R&C) than one at RCBest corner. Meanwhile,
corner and 125C. RCworst parasitic corner is used for metal DVD decreases at RCWorst_dPV corner due to thicker design
interconnects. The limitation of voltage fluctuation is 15% of target from process variations. Due to the metal retargeting,
Vdd. #DVD Max denotes the amount of instances where DVD DVD on wire is highly reduced.
is in beteween Vdd and the maximum DVD point. #DVD Min
is vice versa. Worst Instance and Worst Wire are the portion IV. Conclusion and Future Works
of maximal DVD at the level of VDD in instance and wire, Dynamic voltage drops with PVT and RC corner variations
respectively. As the input voltage decreases, the DVD are reported. As the input voltage decreases, the temperature
violation and the portion of instance and wire violations are increases, and at RCWorst parasitic corner, the DVD on
increased. This is due to that theat at the lower input voltage, a instances and wires increases in 16nm FinFET design. Vector
small voltage fluctuation could induce huge impact. DVD with VCD (value changed dump) will be analyzed for
better accuracy for power sign-off. The optimal power switch
TABLE 2 DVD WITH CHIP TEMPERATURES
will be also proposed in FinFET designs.
#DVD #DVD Worst Worst
Temperature
Max. Min. Instance Wire
References
_40C 1413 84 32.6% 29.8%
[1] W. Zhao , Y. Cai and J. Yang, "Fast Vectorless Power Grid
o C 1760 275 33.3% 30.5% Verification using Maximum Voltage Drop Location Estimation,"
Asia and South Pacific Design Automation Conference, 2014.
85C 2028 388 34.8% 31.7%
[2] S. Lin and N. Chang, "Challenges in power-ground integrity",
125C 4543 1086 40.3% 38.5% International Coriference on Computer Aided Design, 2001.
[3] N SK, G. Shanmugam, S. Chandrasekar, "Dynamic voltage (IR)
drop analysis and design closure: Issues and challenges,"
DVD on signal interconnects in terms of ambient chip International Symposium on Quality Electronic Design, 2010.
temperature is shown in Table 2. RCbest parasitic corner is [4] K. Arabi, R. Saleh and X. Meng, "Power Supply Noise in SoCs:
used for metal lines. When the higher temperature is applied, Metrics, Management,and Measurement," IEEE Publication
the DVD violation increases. This is because the instances and Design & Test of Computers, vol. 24, pp. 236-244, 2007.
wires have more resistive as temperature increases. Moreover, [5] Y. Ban, S. Sundareswaran, and D. Pan, "Total Sensitivity Based
instances induce more current due to temperature inversion at DFM Optimization of Standard Library Cells," International
16nm node and cause more spontaneous voltage drops. Symposium on Physical Design, 2010.

Table 3 shows the DVD violation with the back-end [6] Y. Ban et aI., "Layout induced variability and manufacturability

parasitic RC corners. The PVT for the front-end devices was checks in FinFETs process", international Symposium on SPIE
Advanced Lithography, 2014.
set to a O.88V Vdd. Compared to Typical corner, the number of
DVD violation at the RCWorst corner has higher (worse). This [7] Y. Ban et aI., "Analysis and Optimization of Process-Induced
Electromigration on Signal Interconnects in 16nm FinFET SoC,"
is because the interconnects have more resistive just like as
International Symposium on SPIE Advanced Lithography, 2014.
temperature. At RCBest corner, the number of DVD violation
is smaller than Typical corner.

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