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2mneotr bor How to find Sotup ime an hols ime fer D ip flop?- Electrical Engjinoring Stack Exchange Electrical Engineering Stack Exchange Hore's how itworks: is.a question and answer ste for electronics and electrical engineering professionals, students, and tnthusiasts. Join them: it only takes a minute ‘Anybody can ask Anybody can The bestanswers are voted ‘question ‘answer ‘up and fse othe top How to find Setup time and hold time for D flip flop? {Lam simulating D flip flop in cadence, how to find set up and hold time in d FF? ‘And 1 have design negative D FF using Pass gate and Inverter when | change same circult to positive O FF by changing ck to InvClk and lavelk to lk Clee 1 Pass gts wnat ype alos git = thet? im Desrsen Sepa moa Usualy 2 SPICE simulation ft pyle yout. Sup 919 1951 C@uncearden there ae some oxales of at ate ge thst Sherence sactexchange cr /a[sos6a/1 i063 epaconsia Sap 9132 041 ‘eranoranb eo a ok bt wasn sre what the difeence is between@ PTL gate and an AND gate. Hoey e muphxe = oy aka Sep B98 LSraweran thanks bt cant see where you special bel something 35 pass gate’ In Your ‘hermes oueinnt answer T woul erume te sesaly an 'AND ate tot forest ne gueson but you know what ey Soy abot mating essumgzons. The reason Teameanted was not becouse {Sd know about pe ate and tc contin jut Dat ve Never hear eee oh those Petts hh woud sop ahermy hod conttng wah ura son 2 Answers Looking for the values of setup time that cause the FF to "fall to operate" isnot a ‘good Idea, A FF will malfunction long before it starts to completely fall, Ths Is a very ‘aptimistic speciation for setup time, an it can lead to erroneous estimates of MTBF for metastabity, “The effect of setup time on clock-to-Q delay is well known and has been documented for several kines of fip-lops. Here's an example from 1996: hpslelecrorics stackexchange comiquesions/8170Snow-lo-ind-seip-tme-and-hld-ime-for-dipop w amor bor How to find Sotup time an hols ime fer D ip flop?- Electrical Enginoring Stack Exchange Figure 4 The Metastablty Window, W, can be determined by ‘accurately measuring the Propagation Delay timelty_cq) at Gitferent Set-up (tsu) Hold (th) times. The value for ts giv in the datasheet or chosen by the designer as the maximum tolerable Clock o @ Outpt dele. Foley, Cu, “Characterizing metastabllty" Symposium on Aévanced Research in [Asynchronous Creults and Systems, 1996,, pp.275,184, 18-21 Mar 1996, col 10.1 109/ASYNC.1996.494449, Here's another example from 2001, regarding 2 0.2541m process. In this figure you can see that the measured setup time 's 190ps, allowing a 5% increase in clock-to- Q delay. If instead the setup time was estimated to be the smallest value that allows the fip-lp to operate the autors would have selected a much smaller YYalue, about 220ps. However, this would lead to Invalid timing analysis because wien the setup time is reduced to 120ps the actual lack-to-Q delay has increased aramatically, from an nominal value of 1060ps to 1200ps, Of course, you could choose to specfy the setup time to be 12009s far timing analysis but then you have a longer criieal path and a slower clock frequency, pat cL ‘wure 1. Definitions of setun and hold times, Dejan Markov, Borivoje Nikolic, and Robart Brodersen. 2002. Analysis and design of low-energy flip-flops. In Proceedings of the 2001 International Symposium en Low Power Electronies and Design, pp. 52-55. dol: 10.1145/383082 383003 Similar data for a 45nm process isin "Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise” by Okumura and Hashimoto, 2010. In ‘Multi-Comner, Energy-Delay Optimized, NBTI-Aware Flip-Flop Design” (Abrisham Hatami, and Pedram in 2010 ISQED) the authors present data for a 65am process with regard to both setup anc hold time, The effect of setup time on elack-to-Q elay is often discussed in the important context of metastabilty, such asin "Comparative Analysis and Study of Metastabilty on High-Performance Flip-Flops" (U, Chuang, ane Sachdev in 2010 ISQED) which again uses @ 65am process. Another example is "Performance, Metastadllty, and Sof-Error Robustness Trade- offs or Flip-Flops in 40nm CMOS" by Rennie et a. In IEEE Trans, on Gireuts and Systems, August 2012. hpslelecrories stackexchange comiquestions/8170Snow-lo-ind-seup-tme-and-bld-ime-for-dtip op amor bor How to find Sotup ime an hols ime fer D ip flop?- Electrical Engjinoring Stack Exchange ‘This i what Ido, First, run a simulation with the O input changing one-half clack cele before the relevant clock edge. Measure the clack-to-q delay under these oncitions and consider that to be the nominal clack-to-q delay. Now start moving the D input transition closer and claser to the relevant clock edge, noticing that the clock-te-g delay wil start to increase. When you have the D input edge at a point where the clock-to-g delay is 5% greater than nominal (or choose the percentage ‘you like) then the time from D to clack is the FF setup time specication, dich’ invent this technique, It is well documented in, for example, the HSPICE ‘Applications Manual. in this manual, they refer to this effect as *pushaut” of the clock-te-Q delay and state For setup- or hold-time optimization analysis, a normal bisection method varies ‘the input timing to find the point just before failure. At this pont, delaying the Input more results infallure, and the output does not transition. In pushout ‘analysis, Instead of fining the last point just before fale, the first successful ‘output transition is used as the golden target, You can then apply @ maximum allowed pushout time to decide ifthe subsequent results are classified as passes Or failures. Finding the optimized pushout result is similar to a normal bisection because both are using a binary search to approach the desired solution. The main diference isthe goal or the optimization criteria. ‘The manual aso supplies this figure to explain the method WT Ht Lower Pushout Norm Upper J ox] he clock-to-g delay is very sensitive tothe D-to-clack time as you get clase to this, point so I strongly recommend using a binary search (bisection) In your simulation to find the setup time, I know this seems Ike lot of work but you do ft more than once you will be glad you invested the time. Learn how to automate measurements For @ more in-depth discussion of why this Is an important criterla for defining the setup time and some SPICE simulation examples, you might also want to look at 408 Budi Sulstyo's Master's Thesis from Virginia Tech ("On the Characterization of Library Celts", 2000). Sulstyo notes that (emphasis mine) ‘Setup time is defined as the amount of time before the latching clock edge in Which an input signal has to already reaches its expected value, so that the ‘output signal will reach the expected logical value within a specific delay. Deciding what is an acceptable increase in clock-to-Q (59%? 1942) i @ tricky business. Pick a small percentage and you get very conservative setup time values, which mit the maximum clack rate of your design. Pick a large percentage and you run the risk of introducing timing failures thatthe synthesizer can't see because it luses the nominal clock-t0-q hpslelecrorics stackexchange comiquesions/8170Snow-lo-ind-seip-tme-and-hld-ime-for-dipop amor bor How to find Sotup ime an hols ime fer D ip flop?- Electrical Engjinoring Stack Exchange “interpreted your question to be specifically about running SPICE simulations to ‘determine satup time. I instead you want to ask about the process of ‘characterizing a standard cel flip-flop then we can talk about simulating over process corners, supply voltage, temperature, input slope, and output loading. ‘These decisions are strana influenced by whet your synthesis taols need. For ‘example, In an earlier life I generated characterization libraries for Synopsys’ Design CCompller, There were separate libraries for eifferent operating conditions and you Included the appropriate set of libraries when performing static timing analysis. Each ‘characterization ibrar typically provided a 2-cimensional table for every timing parameter, showing varation due to Input slope and output load. For the best Fesults, setup and hold ime shoulé be characterized separately for @ rising D input and a falling D input Jo Hass 1 Ths answer run contrary te stand practise ad awn eeu fess and des not eb ounay ‘hte and reer varie (whch derinates).Yousauak of dong any search a9 Grtermnti dots, foran een hat hasan soup vanaton, an stead you tlk bow ceangng te et ne acs ‘etd Qtr am say) Wat ype ea a you eons = ap fr you sre that te moasure paramere clck0-9? Ie seen this methed usa whe measuring {Gos ot 8 to 30% of @)- Te erence ete O's noe and dacs ede fr wiih he propsgaion {hte doubles (or hater percenogs ane acest se) isconsered setup ine We came [Poteet ur for clsibting tne hl tine wnie siting the doe afta aoge oc rm poste aroton.~ vey Sop 0°38 1201 L@raworon eae references and aps to enone your questions. The crests we ae cussing ‘retype mastarsbve be custom or andordal CMOS VLSI deg, where he pons ae ng detnedihorctertead othe tanga leve~ ees ep Toa 2 ‘evastyzutanv Yes, cek-to-s te important parameter, 2 tats the parameter used during state liming aati Ive saded some exam fom the Mraute tat hope wl day Uh =n los Sap Cetotass 1 undatec ny oot wit eee of ane your ictres and nae deal, ner the dteence realy can haapen nauscays ana cea does ro hagpen ob 54 res youve atl see Up our est deson, Yu" arguing tat ane mors mae sre to rip the crane wth she thu when stating youre, thar was ere or model Ts I Js my tartar nstea.=lesstaerSep 3 ‘You have to skew the clock signal vs. the D input and then look through the resulting waveform for when the FF falls to operate or starts to operate again, One way isto have slightly diferent clock source frequencies. If your simulator allows for control over the voltage sources under Monte Carlo simulation then that is also an ‘option, Running a complete sulte of corner cases (PTV - process ~ temperature - ‘oltage) especially selecting the adverse cases (Fast N slow P, or Slow P fast N) ‘ete. and picking an appropriate sigma level in the medals wil then allow you to pick the appropriate delay numbers. Youll find that the design fails very abruptly for simple logic gates transitioning over 2 period of @ few ps soa simple sweep will be more than adequate at each PTY level. ‘There are a couple key factors to realize, A SPICE simulation by itself is ‘deterministic, unless you bring n foundry data and Schmoo (vary the the ‘conditions) with foundry data your results are meaningless to determine a safe level for operational parameters. Here is a plot of 7G Based Dif withthe D vs. Ck transition changing 10 ps on every 2.5 ns clack period so a change af 0.04 ns/ 2.5 1s = 0.4% variation per clock. The high It trace is the Output (green - Q) and you! ‘can see the circuit almast generating a runt pulse (one the RHS). hpslelecrorics stackexchange comiquesions/8170Snow-lo-ind-seip-tme-and-hld-ime-for-dipop ammeter bor - How ta fin Sot time ard hela ime fer D ip op? - Electrical Erginoaring Stack Exchange ‘This is a very reasonable erteria to use to then do multiple cuns at diferent PVT's, [And from using the factory skewed data you can easily determine the 3 sigma level effects an the setup and hold parameters, The library industry standard is to use 3 sigma level data. More granularity (10 ps) in this case is clearly unwarranted Processes at or below 65 nm need to also bring In lotto lot variance ontop of mismateh to ensure that parameters are modelled and contrbute according in the following picture the two vertical red lines represent rough limits on the lengthening of Tclk-Q with the approach of the setup, The red arrows represent the sparVwidth In this dlagram, The green arrow represents the limit of the setup time (it corresponds the position ofthe vertical red line an the LHS. The green fuzzy band Fepresents the statistical variation and the mismateh, With the Blue afrow representing the value that represents the safe limit of choice of Tsetup (represented by the vertical green line). added these features to a snip from the the other post and then added in a more realistic situation, More about that later hpslolecreries stackexchange comiquestions8170Show-o-nd-setip-tme-and heldtime-fr 87 Data-cuxips) Figure 1. Definitions of setup and hold times. While the frst image from the older paper shows this transitional aree as lackadaisical event which is ezsly on the same scale as the setup time, For Processes that are 0,5u and below this drawing Is misleading. In the simulation above, the crcut transitioned within ane clock shift (in this ease 10 ps) whichis perhaps at most 20% of the Tsetup (0.35 um process, TG based FlipFlop). The Statistical variation from process and mismatch will be many factors larger than this transitional region, ‘The crux of the point is that there really is no point is trying to determine this knee value when 1) its so much more abrupt - in this case using a binary search { might have refined it to 8 ns vs, the 10 ns bin I choose, 2) this wil be hidéen in the noise ‘of a value that has been choosen for yield {must note that in my drawing - lower part that I put In 20 ns band (red lines), Even then you can stil see thatthe fuzzy green band will dominate, [And this drawing is for llustrative purposes only 1s is possible, that you coulé have such a soft transition in this parameter. And if ‘you do then certainly follow Joe Hass's methodology. Sut prepared to have that parameter smeared out with mismatch {do very much doubt that those are real numbers in that chart, But since I no longer have access to 1um spice decks, 1 cannot say, ean only suspect ‘other features. 1 didnot do the analysis for hold as the F's normally used have negative hold time and It would have complicated things. 1 di¢ ask around to two different croups that maintain libraries (one a library vendor ‘one within @ IDM) to make sure I wasn't screwing Up. hpslelecrorics stackexchange comiquesions/8170Snow-lo-ind-seip-tme-and-hld-ime-for-dipop amor bor How to find Sotup ime an hols ime fer D ip flop?- Electrical Engjinoring Stack Exchange acceler hpslelecrorics stackexchange comiquestions/8170Sow-Io-ind-seup-tme-and-hld-ime-fr-dtipop oa

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