Wireless Communication System

Design with National Instruments

LabVIEW and PXI Platform
Douglas E. Kim, Ph.D.
RF & Communications Round Table
December 2012

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 Agenda
Streaming video over SISO OFDM link
System overview
Hardware/software architecture
High Level Synthesis Tools (HLS) for Wireless Prototyping:
OFDM Physical Layer in DSP Design Module
Channel decoder in LabVIEW FPGA IP Builder
VST SISO Channel emulator
Demo

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 Wireless Streaming Video
Moving Beyond the PHY Layer
A complete end to end system from Application Layer to
RF for a real time wireless system
Seamless HW/SW integration and interoperability all built
on LabVIEW
BER plots are great, but now you can stream video too!

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From PHY Layer . . .

Transmitter (Tx) Receiver (Rx)

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From PHY Layer . . . To APPLICATION
Transmitter (Tx) Receiver (Rx)

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 Hardware Platform Overview
OFDM Transmitter & Receiver

PXIe Quad Core FlexRIO PXIe-7965R

Controller FPGA Module &
5791 RF Transceiver

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NI PXIe-8133 Quad Core PXI Express Controller

Intel Core 1.73 GHz i7-820QM

quad-core processor
2 GB (1 x 2 GB DIMM) dual-
channel 1333 MHz DDR3 standard,
8 GB (2 x 4 GB DIMM) maximum
Other peripherals (ExpressCard/34
slot, DVI-I video connector, IEEE
1284 ECP/EPP parallel port, GPIB
(IEEE 488) controller, and RS232
serial port)

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 NI PXIe-7965R FlexRIO FPGA Module
Virtex-5 SX95T FPGA optimized for
DSP
Peer-to-peer streaming
800 MB/s across PXI Express
backplane
16 simultaneous streams
Onboard DRAM
2x 256 MB banks
1.6 GB/s per bank
Enhanced Synchronization
Share PXI 10 MHz reference
clock or DSTAR_A with adapter
module

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 NI 5791 RF Transceiver Adapter Module
RF Specifications
200 MHz 4.4 GHz
100 MHz Bandwidth
14 bit ADC
16 bit DAC
-94 dBc/Hz Phase Noise
-162 dBm/Hz Nose Floor
(-15 dBm output)
+8 dBm Max Output Power
(2.4GHz)

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 Transmitter Hardware Mapping
Transmitter Host VI Video Processing
8133 Controller
UDP

LabVIEW Host
H.264 Video
MPEG-TS
Encap.
Local UDP
Socket
Reader
Thread
MAC
Encap.
DMA
Transfer

DMA FIFO

RF Front
Transmitter FPGA VI Channel Coding & OFDM Processing
End
Flex RIO - FPGA
OFDM IFFT &

DSP Design Module

Channel
Encoder
Scrambler
Bits to
Symbol
Subcarrier
Mapping
CP
Insertion

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Receiver Hardware Mapping
RF Front Timing &
Sample FFT & FPGA No. 1
End Frequency Channel
Rate CP
Offset Equalization
Change Removal
DSP Design Module
Correction

Channel
Estimation

P2P FIFO
FPGA No. 2
DSP Design Module
LLR
Descramble
Channel
Decoder
QAM
Calculation Demod
(BCJR)
& IP Builder
DMA FIFO
8133 Controller
H.264 Video
UDP
MAC Frame
LabVIEW Host
Reassembly
Writer
Thread
UDP
Socket

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 DSP Design Module

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 LabVIEW DSP Design Module

The LabVIEW DSP Design Module simplifies the creation of complex DSP
subsystems targeted for FPGA deployment, allowing you to:
Quickly prototype real-time FPGA-based DSP subsystems
Use rich signal processing IP libraries that exploit FPGA and surrounding
DSP fabric
Design your own signal processing IP blocks with LabVIEW FPGA or by
importing third-party IP
Explore design trade-offs between timing requirements and resource
constraints

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Simplifying Algorithm Development For Real-Time
Targets
LabVIEW FPGA

DSP Design Module

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 OFDM Tx Subsystem Mapping

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 OFDM Rx Subsystem Mapping

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 Multirate DSP Illustration

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 DSP Design Module
A Simple Example

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 OFDM Tx Implemented in DSP Design Module

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 A Simple Example
Block Diagram

Zero padding
6 zero tail bits added per group of 119 input bits
Convolutional encoder
Rate-1/2 code
Rate required
3Mbps at output

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 A Simple Example
Host-Based Simulation to Verify Algorithm

In algorithms with floating point input and/or output, the additional

step of float to fixed conversion and comparison is needed after this
stage

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 A Simple Example
Implement Using DSP Design Module

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 A Simple Example
Verify Design Using Auto Generated Test Bench

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 A Simple Example
Integrate with LabVIEW FPGA

Auto Generated FIFOs

Generated LabVIEW
FPGA VI

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 LabVIEW FPGA IP Builder
Add-on tool for LabVIEW FPGA

Integrate state-of-the-art HLS compiler with

LabVIEW
Use LabVIEW dataflow
Generate high performance FPGA IP

LabVIEW VI Integrate
+ AutoESL IP with FPGA
Directives VI

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NI CONFIDENTIAL
LabVIEW FPGA IP Builder
Add-on tool for LabVIEW FPGA

Rapidly develop high performance algorithms for

FPGAs
Quickly explore design tradeoffs using directives
Reuse IP to meet new design requirements
LV FPGA VI LV FPGA IP Builder VI

Manual optimization required Optimization using high-level synthesis

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NI CONFIDENTIAL
 Vector Signal Transceiver (VST)
Channel Emulator

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Over The Air (OTA) Transmission
Transmitter (Tx) Receiver (Rx)

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Channel Emulation Tests
Transmitter (Tx) Receiver (Rx)

Channel Emulator

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Point to Point Communication

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Multiple Access Communication

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Multiple Access Communication
Packet Mode Contention

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 Supported Channel Profiles
Custom-Deterministic
User set delays and power (PDP) => constant frequency
selective fading
Channel parameters can be changed during operation
Custom-Stochastic
Time-varying channel coefficients
User set PDP and Doppler spread
IEEE 802.11n (TGn)
Models A ~ F
LTE/LTE-A
Extended Pedestrain A (EPA)
Extended Vehicular A (EVA)
Extended Typical Urban (ETU)

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 TGn/ac Channel Model
Model Desc. No. rms delay max delay No. Taps
Clusters (ns) (ns)
TGn TGac*
A Office, NLOS 1 0 0 1 1
B Residential 2 15 80 9 17
C Small Office 2 30 200 14 27
Typical Office,
D Fluorescent 3 50 390 18 35
Lights
Large Office,
E Fluorescent 4 100 730 18 35
Lights
Large Space,
moving vehicle
F 6 150 1050 18 34
(Bell+Spike
Doppler)
* 80MHz system BW => = 5ns (200MHz sampling)

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 TGn/ac Channel Model
Parameter Value

Max No. of TX Antennas 2

Max No. of RX Antennas 2
MIMO Configurations Supported 1x1, 1x2, 2x1, 2x2
Max No. of Channels 4
Max. RF Bandwidth 80 MHz
ADC/DAC Sampling Rate 120 MHz
Max No. of Taps per Channel 36
Delay Resolution 10 ns
Max Delay 20.6 us

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 Block Diagram
LV Code

HW LV-FPGA IP
Configuration Fading
and Channel
Application Generation Xilinx IP
Control

BW 80 MHz Interp.
RFin < 6 GHz

DDC/ BRAM DUC/

Sample Delay Dot Sample

Rate
1 Change
Bank Product Rate
Change

Interp.

2 DDC/ BRAM DUC/

Sample Delay Dot Sample

Rate Bank Product Rate

Change Change

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