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fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2370948, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
7-Level PWM Inverter Employing
Series-Connected Capacitors Paralleled to a
Single DC Voltage Source
Jin-Sung Choi, and Feel-soonKang, Member, IEEE
AbstractThis paper presents an effective circuit configuration
of multilevel inverter which can increase the number of output
voltage levels with the reduced number of circuit components.
The proposed 7-level PWM inverter consists of a single dc voltage
source with a series of capacitors, diodes, active switches for
synthesizing output voltage levels, and an H-bridge cell. After
theoretical analysis, we carry out computer-aided simulations and
experiments to verify the validity of the proposed approach. Here
we also introduce a modified switching strategy to solve capacitor
voltage unbalancing occurred in series-connected capacitors.
Index TermsInverters, multilevel systems, phase disposition
(PD), pulse width modulation (PWM), total harmonic distortion
(THD)
I. INTRODUCTION
R ECENTLY, multilevel inverters have a great attention
from the industry using high voltage and high power
applications, which are the first motivation of multilevel
inverter researches.
The second motive is that multilevel inverter can synthesize
stepped output voltages similar to sinusoidal wave. Many
number of voltage levels ensure a high quality output voltage,
which shows a good THD with low dv/dt stress and small size
of output filter. But, it needs a large number of circuit
components [1]-[5]. In conventional multilevel inverters,
cascaded H-bridge multilevel inverter (CHB) is one of the best
approaches to increase the number of output voltage levels
thanks to modularization and easy to expansion [6], [7].
However, when CHB increases H-bridge cells, it also increases
the number of switches and moreover, independent input dc
voltage sources. One of the solutions to reduce the number of
Manuscript received April 17, 2014; revised August 19, 2014; accepted
October 20, 2014.
Copyright 2014 IEEE. Personal use of this material is permitted. However,
permission to use this material for any other purposes must be obtained from the
IEEE by sending a request to pubs-permissions@ieee.org
This research was supported by Basic Science Research Program through
the National Research Foundation of Korea (NRF) funded by the Ministry of
Education, Science and Technology (2012R1A1A2006120).
J. S. Choi was with Hanbat National University, Daejeon 305-719, Korea.
He is now with New Power Plasma Co. Ltd., Korea.
F. S. Kang is with the Department of Electronics and Control Engineering,
Hanbat National University, Daejeon 305-719, Korea (phone: 82-42-821-1172;
fax: 82-42-821-1164; e-mail: feelsoon@hanbat.ac.kr).
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1
components in CHB is to use asymmetrical dc voltage sources
[8], [9]. When the dc voltages are scaled in power of three, it
can maximize the number of output voltage levels. However, it
still increases independent dc voltage sources to generate a
higher output voltage levels. To solve this problem, multilevel
inverter employing a cascaded transformer was introduced in
[10]. It also uses a combination of asymmetrical voltage
sources to synthesize multilevel output voltages. The most
advantageous achievement is that it just employs a single dc
voltage source. However, the cascaded transformer makes the
system bulky because it operates in low frequency. To alleviate
the problem, multilevel inverter using four floating power
supplies was introduced in [11]. But, it needs a front-end
transformer to obtain independent dc voltage sources. To
overcome this problem, transformerless circuit topologies were
presented in [12]-[18]. Usually, these kinds of multilevel
inverters were modified and developed from CHB. In [12],
packed U cells multilevel inverter was presented. It shows very
good performance in reduction of the circuit components.
However, it increases conduction losses when it generates each
voltage level because the circulating current passes through
three switching devices in each level generation. Moreover,
voltage across the capacitor has big ripples although it uses a
bulky capacitor of 5000F. Multilevel inverters employing
bidirectional switches and series-connected capacitors were
proposed in [13] and [14]. Theoretically, they can generate a
large number of output voltage levels over 125 levels with the
reduced number of circuit components. However, each
capacitor needs individual dc-to-dc converter to obtain dc
voltage sources. Modular multilevel converter was introduced
in [15]. It has a good modular characteristic so it is easy to be
extended to high voltage levels. But, it increases the number of
bulky capacitors and switches compared to other counterparts.
Multilevel inverter employing series-connected dc voltage
sources was proposed in [16]. It consists of a level generating
stage and polarity selection part to reduce the switching losses.
However, it fails to reduce the number of dc voltage sources
when it increases the output voltage levels. Multilevel inverter
using switched series/parallel dc voltage sources was
introduced in [17]. Although it can increase the number of
output voltage levels, switching pattern is complex, and
moreover it increases conduction losses. Photovoltaic
multilevel inverter using series-connected capacitors was
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2

investigated in [18]. It does not explain how to balance divided by three capacitors connected in series. Lets assume
capacitor voltage although dc-link voltage is controlled by the that all components are ideal and the circuit is in a steady-state.
front-end boost converter. Each capacitor voltage equals to Vdc/3. Then we can obtain 7
Most of the previous approaches given in [12]-[18] use levels in the output voltage wave; Vdc, 2Vdc/3, Vdc/3, 0, -Vdc/3,
series connected capacitors. It is a useful way to minimize the -2Vdc/3, -Vdc. Switches in an H-bridge cell (S1~S4) work to
number of independent dc voltage sources when it increases the determine the polarity of the output voltage with the highest (or
number of output voltage levels once it solves the capacitor lowest) voltage level, Vdc (or -Vdc). Other voltage levels are
voltage unbalancing problem. generated by working of S5, S6, and S7.
In this paper, we present an effective circuit configuration of
multilevel inverter which can increase the number of output
voltage levels with the reduced number of circuit components.
It consists of a single dc voltage source paralleled to
series-connected capacitors, two diodes, three switches for
synthesizing output voltage levels, and an H-bridge cell. To
verify the validity of the proposed approach, we carry out
computer-aided simulations and experiments. Here we also
introduce a modified PWM control scheme to solve capacitor
voltage unbalancing occurred in series-connected capacitors.
Fig. 1. Circuit configuration of the proposed 7-level PWM inverter.

II. PROPOSED 7-LEVEL PWM INVERTER

B. Generation of output voltage levels
A. Circuit configuration To help readers understanding, every current path for
Fig. 1 shows a circuit configuration of the proposed 7-level generating 7-level is given in Fig. 2. Here, the highlighted line
PWM inverter. It has a single dc voltage source, which is and the bigger symbol caption mean the conducting line and

Vdc
3 VC1 D1 S1 S3

S5 iout
Vdc
Vdc
3 VC2 S7 Load
S6 vout
D2
S2 S4
Vdc
3 VC3

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

(j) (k) (l)

Fig. 2. Generation of each output voltage level and load current path, (a) Vdc, (b) 2Vdc/3, (c) Vdc/3, (d) 0, (e) -Vdc/3, (f) -2Vdc/3, (g) -Vdc, (h) opposite current flow at
Vdc and 2Vdc/3 level, (i) opposite current flow at Vdc/3 level, (j) opposite current flow at zero level, (k) opposite current flow at -Vdc/3 level, (l) opposite current flow
at -Vdc level .

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components. each mode is determined by

Level Vdc: Fig. 2(a) shows a current path when output voltage
is Vdc. Three capacitors connected in series supplies energy to Mode 1: P1 0 t 1 and P5 4 t (1)
the output load. It discharges through S1 and S4. If a load is an Mode 2: P2 1 t 2 and P4 3 t 4 (2)
inductive one and the direction of the load current is opposite,
Mode 3: P3 2 t 3 (3)
the current flows through DS1 and DS4, and charges the
capacitor stack as given in Fig. 2(h). Mode 4: P6 t 5 and P10 8 t 2 (4)
Level 2Vdc/3: Fig. 2(b) shows a current path when output Mode 5: P7 5 t 6 and P9 7 t 8 (5)
voltage is 2Vdc/3. Two capacitors C2 and C3 feed the output load. Mode 6: P8 6 t 7 (6)
It discharges through S5, D1, and S4. When the direction of the
load current is opposite, there is no current path under this vref
switching state. In this time, the load current flows through DS1 vcar3
and DS4, and charges the capacitor stack as given in Fig. 2(h). vcar2
Regardless of the load current flows, the output voltage is vcar1
clamped as 2Vdc/3 level by the switching state given in Fig.
2(b).
Level Vdc/3: Fig. 2(c) shows a current path when output
voltage is Vdc/3. The lower end capacitor (C3) supplies energy
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
to the output load. It discharges through DS6, S7, D1, and S4. If
the direction of the load current is opposite, the load current Cc
flows through D2, S7, DS5, and DS4 as shown in Fig. 2(i). Cb
Level 0: To generate a zero level, two switching schemes can Ca
be considered. The basic idea to generate a zero-level is the
S1
voltage cancellation. Fig. 2(d) shows a current path when it
synthesizes zero level. When S2 and S4 turn on simultaneously, S2
the output voltage becomes zero. The other method is to turn S1 S3
and S3 on at the same time. When the direction of the load S4
current is opposite, the current will flow as shown in Fig. 2(j).
Level -Vdc/3: Fig. 2(e) shows a current path when it produces S5
-Vdc/3 level. The upper capacitor (C1) supplies energy to the S6
output load. If the direction of the load current is opposite, the S7
current flows as shown in Fig. 2(k).
Level -2Vdc/3: Fig. 2(f) shows a current path when output Vdc
voltage is 2Vdc/3. Two capacitors C1 and C2 supply energy to 0
the output load. When the load current reverses, it flows t
-Vdc
through DS2 and DS3 as given in Fig. 2(l). Regardless of the load 1 2 3 4 5 6 7 8 2
current flows, the output voltage sustains -2Vdc/3 level by the Fig. 3. Switching pattern for generating 7-level PWM output voltage.
switching state given in Fig. 2(f).
Level -Vdc: Fig. 2(g) shows a current path when output By logical combination of Ca, Cb, Cc, and Pn, it generates
voltage is -Vdc. Three capacitors connected in series supplies switching signals (Sn). The period (Pn) of each mode varies in
energy to the output load. If the load current is opposite, the terms of switching angle n, which is determined by modulation
current flows through DS2 and DS3, and charges the capacitor index (Ma). By using logical expressions AND, OR, and NOT,
stack as given in Fig. 2(l). each switching signal is determined by

C. General switching scheme

S1 Ca ( P6 P10 ) Cc P3 (7)
Fig. 3 shows a general PD (Phase Disposition) switching
scheme for controlling of the proposed 7-level PWM inverter. S 2 Ca ( P1 P5 ) Cc P8 (8)
It uses a reference and three carrier waves, which have the same S3 P6 P7 P8 P9 P10 (9)
frequency and amplitude, but different offset voltages [19], S 4 P1 P2 P3 P4 P5 (10)
[20]. Table I lists up switching patterns for generating seven
output voltage levels. By comparison of the reference and each S5 Cb ( P2 P4 ) Cc P3 (11)
carrier wave, it produces command signals (Ca, Cb, and Cc). As S 6 Cb ( P7 P9 ) Cc P8 (12)
shown in Table I, when vcar1 and vcar2 are lower than vref, Ca and S 7 Ca ( P1 P5 P6 P10 ) Cb ( P2 P4 P7 P9 ) (13)
Cb become 1, and vcar3 is 1 when it is higher than vref. One cycle
of the reference voltage is divided into 6 modes according to As shown in Fig. 3, S1 works at Mode 3 (vout=2Vdc/3 or Vdc)
the output voltage levels, and corresponding period (Pn) for and Mode 4 (vout=0 or -Vdc/3). S2 works at Mode 1 (vout=0 or

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Vdc/3) and Mode 6 (vout=-2Vdc/3 or -Vdc). S3 works at Mode 4 modulation ratio Ma. To synthesize seven levels on the output
through Mode 6 where vout is negative. S4 works Mode 1 voltage wave, one reference and three carrier waves are used.
through Mode 3 where vout is positive. Hence, S3 and S4 are Hence, the modulation ratio (Ma) is given by
operating at the same frequency with the reference (vref). S5
works Mode 2 (vout=Vdc/3 or 2Vdc/3) and Mode 3 (vout=2Vdc/3 or Am
Vdc). S6 works at Mode 5 (vout= -Vdc/3 or -2Vdc/3) and Mode 6 Ma (14)
3 Ac
(vout=-2Vdc/3 or -Vdc). S7 works Mode 1 (vout=0 or Vdc/3), Mode
2 (vout=Vdc/3 or 2Vdc/3), Mode 4 (vout=0 or -Vdc/3), and Mode
Where Ac is the amplitude of a carrier wave, and Am is
5(vout= -Vdc/3 or -2Vdc/3).
amplitude of a reference wave. Thus, the output voltage is
TABLE I defined by
OUTPUT VOLTAGE LEVELS ACCORDING TO SWITCHING
STATE.
vout M a sin t (15)

When Ma is lower than 0.33, output voltage has 3 levels.

Between 0.33 and 0.66, output voltage has 5 levels, and with
Ma of higher than 0.66, it shows 7 output voltage levels.
D. The origin of the capacitor voltage unbalance
The voltage balancing of series-connected capacitors acting
as an energy tank is very important to generate exact output
voltage levels in the proposed multilevel inverter. Thus, we
first find the origin of the capacitor voltage unbalance.

(a)

TABLE II
SWITCHING ANGLES ACCORDING TO MODULATION INDEX.
Ma Ma 0.33 0.33 M a 0.66 Ma 0.66
n
A A
1 sin 1 c sin 1 c
2 Am Am
2A
2 sin 1 c

2 2 Am

3 2
2 2

4 1 1
2
3
5 1 1
2
3 3 (b)
6 2
2 2 Fig. 4. Equivalent circuit of the proposed 7-level inverter and operational
3 3
7 2 2 waveform, (a) equivalent circuit with average currents, (b) output voltage and
2 2 lagging load current.
3
8 2 1 2 1
2
Fig. 4(a) shows the equivalent circuit of the proposed 7-level
inverter. Fig. 4(b) describes the stepped output voltage and
Table II shows a switching angle (n) according to lagging load current. Assuming that the sinusoidal lagging load

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current is iout= Imsin(t-). Then, the average input node voltage regulation of C2 as well as voltage balance of the upper
current i1 is given by and the lower capacitors. Because C2 locates between C1 and C3,
the charging and discharging current of C1 and C3 should flow
1 3 Im through C2. Thus, the voltage regulation of C2 is directly related
I1( avg )
2 3
iout d (t )

cos cos 3 (16) to voltage regulation across C1 and C3. Fig. 5(a) shows the
modified control method for regulating C2 voltage. It controls
Similarly, the average input node currents i2 and i3 are given the amplitude of the carrier wave (vcar2), which is compared
as follows. with the reference (vref). The range of the amplitude is
determined by
1 3 Im
I 2( avg )
2 i 2
out d (t )

cos (cos 2 cos 3 ) (17) vcar1 _ max vcar 2 _ min vcar 2 vcar 2 _ max vcar 3 _ max (24)

1 2 Im
I 3( avg )
2 1
iout d (t )

cos (cos1 cos 2 ) (18) As shown in Fig. 5(a), the control signal Cb changes its
duty-ratio according to the different amplitudes of vcar2. The
duty-ratio of Cb is directly related to the duty-ratio of S5 and S7
In this time, each capacitor voltage should be regulated so for +2Vdc/3 level generation as given in (11), (13), and Fig. 3.
that each capacitor supplies the average current per cycle as When S5 turns on as shown in Fig. 2(b), the output voltage
follows. becomes +2Vdc/3. This period is a discharging time of C2. On
the other hand, when S5 turns off and S7 turns on as shown in
Im Fig. 2(c), the output voltage level becomes +Vdc/3, which
I C1( avg ) I1( avg ) cos cos 3 (19)
allows the charging of C2.
Im
I C 2( avg ) I1( avg ) I 2( avg ) cos cos 2 (20)

Im
I C 3( avg ) I1( avg ) I 2( avg ) I 3( avg ) cos cos 1 (21)

Hence, IC1(avg) < IC2(avg) < IC3(avg) for 1<2 <3. It means that
more charges flow from the lower capacitor C3 than the upper
capacitors (C1 and C2). This is the main reason of the voltage
unbalancing in the series-connected capacitors of the proposed
circuit topology. Hence, each capacitor voltage should be
regulated to feed the appropriate amount of average current by
satisfying (22).
(a)
I C1( avg ) I C 2( avg ) I C 3( avg ) (22)
y
vcari1 ( t)
1

From the relationship of (19), (20), and (21), we obtain vcari2 ( t) y

hy1
Vp,1 2
vref ( t)
I C 2( avg ) cos 3 I C 2( avg ) cos 1 I C 3( avg ) cos 3 Vp,2 1 hy2 2

, , (23) vref ( i) hx
I C1( avg ) cos 2 I C 3( avg ) cos 2 I C1( avg ) cos 1 n

C t C C
dl dr
x1 x2
From (23), we can know that the capacitor voltage d1 dl + dr = d
unbalancing occurs just depending on the switching angles of d2
Cb
1, 2, and 3 regardless of load conditions. In other words, the i i * t

difference between charging and discharging of the series (b)

connected capacitors is determined by the switching angles. It
Fig. 5. Modified control scheme for capacitor voltage balancing, (a) variation of
means that the different period for each voltage level is the Cb according to the amplitude of vcar2, (b) geometrical relation between the
cause of the capacitor voltage unbalance [21]-[24], [28]. carrier wave (vcar2) and the reference (vref).

E. Modified switching scheme for voltage balancing

To solve the capacitor voltage unbalancing, we introduce a
modified switching pattern for the proposed multilevel inverter.
The main idea of the proposed control strategy is to regulate the
charging and discharging rate of the capacitor C2. It ensures the
Fig. 5(b) shows two carrier waves which have different
amplitudes, Vp,1 and Vp,2, respectively. We assume that the
carrier frequency is very high so that the amplitude of the
consecutive intersections of the reference and carrier wave at
positions i and i* is constant. Then the mathematical relation

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for the pulse width of Cb according to the variation of the Fig. 6 shows simulation results of output voltage and the
amplitude of vcar2 is found using a geometrical relation as capacitor voltage with a general switching method. From Fig.
shown in the right-hand side of Fig. 5(b). From the geometry of 6(a), we can find that the middle voltage levels (2Vdc/3) are
the triangle ABC, we have disappeared as times go by. At 0.25 second, the output voltage
level shows just 5 levels like that of 5-level PWM inverter,
T which has two series-connected capacitors. It means that only
hy1 V p ,1 , hy 2 V p , 2 , hx V p , ref sin i , y o (25) the upper and the lower capacitors (C1 and C3) are charged as
2k
Vdc/2, but the middle capacitor (C2) failed to charge up because
Here, k means the number of pulses. T is the period of of insufficient charging time as shown in Fig. 6(b).
+2Vdc/3 level. o means the carrier frequency. Then, each pulse Fig. 7 shows simulation results of the output voltage and
width (d1 and d2) of the i-th pulse is given by capacitor voltages with the modified switching scheme. The
output voltage shows exact 7 levels as given in Fig. 7(a). We
d1 x1 , d 2 x2 (26) can know that the modified switching method works well, so
each capacitor voltage is maintained at near to Vdc/3 (50 V) as
shown in Fig. 7(b).
Since 1=1 and 2=2 then
TABLE III
SPECIFICATION OF SIMULATION AND EXPERIMENT.
hx hy1 hx hy 2
, (27)
x1 y x2 y

Substituting for (25) into (27), it produces

T 1 T 1
d1 o V p , ref sin i , d 2 o V p , ref sin i (28)
2k V p ,1 2k V p,2

Therefore, the difference between d1 and d2 is given by

T 1 1
d d1 d 2 oV p , ref sin i (29)
2k
V p ,1 V p , 2
vout
150V
In (29), the difference (d) of both pulse widths is in inverse
proportion to the amplitude of carrier wave (vcar2). Thus we can
find that the duty-ratio of Cb can be proportionally controlled
by the amplitude of vcar2. It means that the duty-ratio of S5 and 0

S7 are also proportionally controlled by the amplitude of vcar2.

Thus, the proposed control method, which controls the
amplitude of vcar2 is a reasonable way to manage voltage across -150V
the middle capacitor. In summary, when the amplitude of vcar2 300 ms
increases, the pulse width of Cb decreases. Then the duty-ratio (a)
of S5 increases resulted in increasing of the discharging period
of C2. On the other hand, when the amplitude of vcar2 decreases,
the pulse width of Cb increases. Then the duty-ratio of S5
decreases and S7 increases resulted in increasing of the
charging period of C2. During the negative voltage level
(-2Vdc/3), S6 works for the same operation instead of S5.

III. SIMULATION AND EXPERIMENT RESULTS

To verify the validity of the proposed 7-level PWM inverter,
we carried out computer-aided simulations using PSIM and
experiments using a prototype of 1 kW. Input dc voltage sets to
DC 150[V], hence each capacitor voltage divides into DC
50[V] in an ideal case. Frequency of an output voltage is set to
60[Hz]. Specifications of simulation and experiment are given
in Table III.
(b)
Fig. 6. Simulation results with general switching scheme; capacitor voltage
unbalancing and its effect on output voltage levels, (a) output voltage (vout) with
disappearing voltage levels, (b) voltage unbalancing in series-connected
capacitors.

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losses in the middle switches and reverse recovery losses

vout caused by the turn-off of the diodes during switching.
150V
To prove the actual performance of the proposed 7-level
PWM inverter with the modified switching scheme, we carry
out experiments using a prototype shown in Fig. 9. To generate
0 exact switching signals, the proposed system employs a digital
controller using a DSP 28335, and it adds an output LC filter,
because it is insufficient to produce a sinusoidal output voltage
-150V wave with only 7 levels, but the size of the filter is smaller than
300 ms typical inverters.
(a)

(b)

Fig. 7. Simulation results with the modified switching method, (a) output
voltage (vout) with seven levels, (b) balanced voltage in series-connected
capacitors.
Fig. 9. Prototype for experiment.

Fig. 10. Experiment result; each capacitor voltage of series-connected

capacitors.

Fig. 10 shows the experiment result of each capacitor voltage.

Fig. 8. Simulation results of voltage across switching devices when it
synthesize seven output voltage levels with Ma=1.0.
Fig. 8 shows simulation results of voltage across switching
devices when it produces seven output voltage levels with
Ma=1.0. The blocking voltage of S5 and S6 is about 66 % of the
input dc voltage. The blocking voltage of S7 is about 33 % of
the input dc voltage. But, the blocking voltage of H-bridge
switches (S1~S4) is equal to the input dc voltage, and moreover
it is proportional to the output voltage. Thus the proposed
circuit topology is unsuitable to apply high voltage applications.
In addition, we need careful attention to reduce the conduction
Voltage across the middle capacitor (C2) maintains Vdc/3 (50 V).
Other capacitor voltages also support Vdc/3 with some voltage
ripples affected by an input voltage source (Vdc). From this
result, we know that the modified switching scheme
sufficiently solves the voltage unbalancing problem occurred in
series connected capacitors.
Fig. 11 shows experimental waveforms of output voltages
before and after filtering with FFT result. Here output load is a
resistor 10[]. Fig. 11(a) shows the result when modulation
index is 0.6. Because Ma is lower than 0.66, the output voltage
shows just 5 levels. When Ma is 1.0, the output voltage has 7
levels as shown in Fig. 11(b). In this case, the filtered output
voltage slightly distorted due to the modified switching scheme.
During the period of Vdc level, the optimal switching pattern is

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to iterate between Vdc and 2Vdc/3, but the modified switching

pattern additionally iterates between 2Vdc/3 to Vdc/3 as shown in
the circle of Fig. 11(b). However, the measured THDv meets the
general requirement of 5 % below. In a case of over-modulation
given in Fig. 11(c), both flat-tops of output voltage reduce
PWM waves, so the filtered output voltage looks like a square
wave. Fig. 12 shows experimental waveforms of output
voltages when the proposed inverter connects to an inductive
load. Output voltages according to modulation index are the
same as the results shown in Fig. 11. The difference is that the (a)
load current lags to the output voltage due to the intrinsic
characteristic of the inductive load.

(b)

(a)

(c)

Fig. 12. Experiment results with an inductive load; output voltages before and
after filtering, and load current according to modulation index, (a) Ma=0.6, (b)
Ma=1.0, (c) Ma=1.4.

Fig. 13 shows experimental waveforms of output voltages

when the proposed inverter connects to a rectifier load. Output
voltages are the same as the results shown in Fig. 11 and Fig. 12.
But, the filtered output voltage has more distortion because of
(b)
the modified switching pattern and the load current which has a
short conduction angle with somewhat high current peak due to
the intrinsic characteristic of the rectifier load.
Fig. 14(a) shows experiment results of drain-to-source
voltage of each switching device located in an H-bridge cell.
Fig. 14(b) shows drain-to-source voltages of the middle
switches. These experiment results are exactly same to the
simulation results given in Fig. 8.
Fig. 15(a) shows experiment results of series-connected
capacitors and the output voltage when the modulation index is
changed from 0.6 to 0.8. Thus the number of the output voltage
levels changes from 5-level to 7-level. Fig. 15(b) is the results
at vice-versa. In both cases, we can find that the output voltage
(c) goes fast into steady-state and there are no influence on
capacitor voltages.
Fig. 11. Experiment results with a resistive load; output voltages before and
after filtering, and FFT result, (a) Ma=0.6, (b) Ma=1.0, (c) Ma=1.4.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 9

proposed is better than [18] since the carrier frequency is much

higher than [18].

(a)

(a)

(b)

(b)

Fig. 14. Experiment results of voltage across each switching device at Ma=1.0,
(a) drain-to-source voltage of S1, S2, S3, and S4, (b) drain-to-source voltage of S5,
S6, and S7.

(c)

Fig. 13. Experiment results with a rectifier load; output voltages before and
after filtering, and load current according to modulation index, (a) Ma=0.6, (b)
Ma=1.0, (c) Ma=1.4.

Fig. 16(a) shows experiment results of series-connected

capacitors and the output voltage at Ma=0.8 when the output
frequency is decreased from 60 Hz to 50 Hz. Fig. 15(b) is the
results when the output frequency is increased from 60 Hz to 70
Hz. In both cases, there are no influence on capacitor voltages (a)
regardless of the variation of output frequency.
The investigation of THDv is important since the modified
switching pattern slightly departs from the optimal switching
pattern for the best THD as shown in Fig. 11(b). Fig. 17(a)
shows THDv according to modulation index. It was measured
with 1 kW resistive load. It sufficiently meets the general
requirement of 5 % below when the modulation index is set to
between 0.6 to 1. But, it fails to meet the requirement when Ma
is lower than 0.6 and over-modulation. Fig. 17(a) also
compares THDv with [18]. When output voltage is 7-level,
THDv of the proposed and [18] are measured as 5% below. At
Ma=1.0, [18] is better than the proposed approach because the
proposed approach strays from the optimal switching pattern (b)
because of the capacitor balancing control. On the other hand,
Fig. 15. Experiment results of capacitor voltage and output voltage according
when the output voltage is 5-level at Ma=0.6, THDv of the
to the variation of Ma, (a) from Ma=0.6 to Ma=0.8, (b) from Ma=0.8 to Ma=0.6.

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25
Proposed (Experiment)
Proposed (Simulation)

Total Harmonic Distortion [%]

20 Reference [18]

15

10

0
(a) 0.4 0.6 0.8 1.0 1.2 1.4
Amplitude Modulation Index [Ma]

(a)

100

95

90

85
Efficiency [%]

80

75
Ma=0.4 Ma=0.6
70
Ma=0.8 Ma=1.0
(b) 65 Ma=1.2 Ma=1.4

Fig. 16. Experiment results of capacitor voltage and output voltage according
to the variation of output frequency, (a) from fout=60Hz to fout=50Hz, (b) from
fout=60Hz to fout=70Hz.
Fig. 17(b) shows the efficiency comparison according to
modulation index when output power varies from 100 W to 1
kW. It shows that efficiency at higher Ma is better than that of
lower Ma. In over-modulation, it shows high efficiency because
switching losses are considerably reduced. At 800 W and over
Ma=0.6, the proposed inverter has the best efficiency as 92.3 %
on average.
In Table IV, we compare the number of circuit components
with counterparts; flying-capacitors (FC), diode-clamped (DC),
cascaded H-bridge (CH), [12], [13], [16], and [18] when they
generate 7-level output voltage. In Table IV, the minimum
number of components is bolded, and parentheses of the
proposed mean the comparison results with the best case. In
this comparison, the best approaches in the viewpoint of saving
of the number of switches are Ref [12] and [18]. However, Ref
[12] has a higher conduction loss and voltage across the
capacitor has big ripples although it employs a bulky capacitor
of 5000 F. Ref [18] is also good to reduce the number of
switches, but it needs 8 diodes. In the case of the proposed
approach, it increases 1 switch, 2 diodes, and 3 capacitors
compared with the best case of the counterparts. We can say
that the most advantage of the proposed approach is the number
of the independent dc voltage source.
60
0.0 0.2 0.4 0.6 0.8 1.0
Output Power [kW]
(b)
Fig. 17. Comparison of THDv and efficiency, (a) comparison of THDv
according to modulation index, (b) efficiency according to modulation index
and output power.
In Table V, comparison result of the blocking voltage on
switching device, specially focusing on switching devices
located at output terminal. To compare the blocking voltage on
switching devices, a known factor MVR (maximum voltage
ratio) is used as the performance index as follows [25].
Vk (max)
Maximum voltage ratio (MVR) = (30)
Vout (max)
Here, VK(max) means the maximum value of H-bridge (or
sub-module at output terminal). Vout(max) is the maximum value
of the output voltage. The smaller value of MVR means the
reduced voltage stress on switching devices. In Table V,
cascaded H-bridge multilevel inverter is the best to reduce the
blocking voltage on switching device. MVR of the proposed
approach is 1 like that of [18], it means that they are unsuitable
for high voltage application although they can reduce the
number of switching devices and independent dc voltage
sources.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
TABLE IV
COMPARISON OF THE NUMBER OF CIRCUIT COMPONENTS.
TABLE V
COMPARISON OF THE BLOCKING VOLTAGE ON SWITCHING DEVICE.
IV. CONCLUSION
We proposed a multilevel PWM inverter which can
effectively increase the number of output voltage levels with a
single dc voltage source. In order to synthesize 7-level output
voltage, the proposed multilevel inverter needs a single dc
voltage source with a series connection of three capacitors, two
diodes, three active switches for synthesizing output voltage
levels, and an H-bridge cell. After theoretical analysis, we
implemented computer-aided simulations to verify the validity
of the proposed approach. Here we introduced a modified
switching scheme to solve voltage unbalancing occurred in
series-connected capacitors. Finally, we carried out
experiments using a 1 kW prototype, and compared with
previous multilevel inverters for the number of main
components, blocking voltage on switching device, and THDv.
As a result, we claim that the proposed 7-level PWM inverter
can be a good candidate, which can substitute for the
conventional PWM inverters in the power rating of a common
use.
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10.1109/TIE.2014.2370948, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 12

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Jin-Sung Choi received the B.S. and M.S. degrees in

the Department of Control and Instrumentation
Engineering at Hanbat National University, Daejeon,
Korea in 2012 and 2014, respectively. He is currently
an Assistant Manager in R&D Center of New Power
Plasma Co., LTD., Korea. His research interests are
in the area of power electronics including design and
control of multilevel inverters. He especially has
researched for multilevel inverter design for electric
vehicles.

Feel-soon Kang (S'00-M03) received the M.S. and

Ph.D. degrees from Pusan National University, Busan,
Korea in 2000 and 2003, respectively. From 2003 to
2004, he had been with the Department of Electrical
Engineering, Graduate School of Engineering, Osaka
University, Osaka, Japan as a Post-doctoral fellow.
Since Sept. 2004, he has been with the Department of
Electronics and Control Engineering, Hanbat
National University, Daejeon, Korea as a Professor.
His research activities are in the area of power
electronics including design and control of various
power conversion systems for display, renewable energy, electric vehicles, and
submarines. He received Award and Prizes from IEEE Industrial Electronics
Society. And he was honored Academic Awards from Pusan National
University and Hanbat National University in 2003 and 2005, respectively. He
also received several Best Paper Awards From KIEE, and KIPE. He served as a
vice-chairman of Organizing Committee for Intelec 2009, ICEMS 2010,
Maglev 2011, VPPC 2012, and ICEMS 2013. He served as an Associate Editor
of the IEEE Transactions on Industrial Electronics from 2004 to 2011. From
2012, He is an Editor of JICEMS. Dr. Kang is a member of KIEE, KIPE, and
IEEE.

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